diff options
author | Dave Airlie <airlied@redhat.com> | 2017-12-03 18:40:35 -0500 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2017-12-03 19:56:53 -0500 |
commit | ca797d29cd63e7b71b4eea29aff3b1cefd1ecb59 (patch) | |
tree | db1ada69f713da68b43c828bd15f90e250f86ab7 /drivers/gpu/drm/i915/intel_hdmi.c | |
parent | 2c1c55cb75a9c72f9726fabb8c3607947711a8df (diff) | |
parent | 010d118c20617021025a930bc8e90f371ab99da5 (diff) |
Merge tag 'drm-intel-next-2017-11-17-1' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
More change sets for 4.16:
- Many improvements for selftests and other igt tests (Chris)
- Forcewake with PUNIT->PMIC bus fixes and robustness (Hans)
- Define an engine class for uABI (Tvrtko)
- Context switch fixes and improvements (Chris)
- GT powersavings and power gating simplification and fixes (Chris)
- Other general driver clean-ups (Chris, Lucas, Ville)
- Removing old, useless and/or bad workarounds (Chris, Oscar, Radhakrishna)
- IPS, pipe config, etc in preparation for another Fast Boot attempt (Maarten)
- OA perf fixes and support to Coffee Lake and Cannonlake (Lionel)
- Fixes around GPU fault registers (Michel)
- GEM Proxy (Tina)
- Refactor of Geminilake and Cannonlake plane color handling (James)
- Generalize transcoder loop (Mika Kahola)
- New HW Workaround for Cannonlake and Geminilake (Rodrigo)
- Resume GuC before using GEM (Chris)
- Stolen Memory handling improvements (Ville)
- Initialize entry in PPAT for older compilers (Chris)
- Other fixes and robustness improvements on execbuf (Chris)
- Improve logs of GEM_BUG_ON (Mika Kuoppala)
- Rework with massive rename of GuC functions and files (Sagar)
- Don't sanitize frame start delay if pipe is off (Ville)
- Cannonlake clock fixes (Rodrigo)
- Cannonlake HDMI 2.0 support (Rodrigo)
- Add a GuC doorbells selftest (Michel)
- Add might_sleep() check to our wait_for() (Chris)
Many GVT changes for 4.16:
- CSB HWSP update support (Weinan)
- GVT debug helpers, dyndbg and debugfs (Chuanxiao, Shuo)
- full virtualized opregion (Xiaolin)
- VM health check for sane fallback (Fred)
- workload submission code refactor for future enabling (Zhi)
- Updated repo URL in MAINTAINERS (Zhenyu)
- other many misc fixes
* tag 'drm-intel-next-2017-11-17-1' of git://anongit.freedesktop.org/drm/drm-intel: (260 commits)
drm/i915: Update DRIVER_DATE to 20171117
drm/i915: Add a policy note for removing workarounds
drm/i915/selftests: Report ENOMEM clearly for an allocation failure
Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"
drm/i915: Calculate g4x intermediate watermarks correctly
drm/i915: Calculate vlv/chv intermediate watermarks correctly, v3.
drm/i915: Pass crtc_state to ips toggle functions, v2
drm/i915: Pass idle crtc_state to intel_dp_sink_crc
drm/i915: Enable FIFO underrun reporting after initial fastset, v4.
drm/i915: Mark the userptr invalidate workqueue as WQ_MEM_RECLAIM
drm/i915: Add might_sleep() check to wait_for()
drm/i915/selftests: Add a GuC doorbells selftest
drm/i915/cnl: Extend HDMI 2.0 support to CNL.
drm/i915/cnl: Simplify dco_fraction calculation.
drm/i915/cnl: Don't blindly replace qdiv.
drm/i915/cnl: Fix wrpll math for higher freqs.
drm/i915/cnl: Fix, simplify and unify wrpll variable sizes.
drm/i915/cnl: Remove useless conversion.
drm/i915/cnl: Remove spurious central_freq.
drm/i915/selftests: exercise_ggtt may have nothing to do
...
Diffstat (limited to 'drivers/gpu/drm/i915/intel_hdmi.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_hdmi.c | 98 |
1 files changed, 55 insertions, 43 deletions
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index e039702c1907..a40f35af225c 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c | |||
@@ -186,7 +186,7 @@ static bool g4x_infoframe_enabled(struct drm_encoder *encoder, | |||
186 | if ((val & VIDEO_DIP_ENABLE) == 0) | 186 | if ((val & VIDEO_DIP_ENABLE) == 0) |
187 | return false; | 187 | return false; |
188 | 188 | ||
189 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | 189 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) |
190 | return false; | 190 | return false; |
191 | 191 | ||
192 | return val & (VIDEO_DIP_ENABLE_AVI | | 192 | return val & (VIDEO_DIP_ENABLE_AVI | |
@@ -245,7 +245,7 @@ static bool ibx_infoframe_enabled(struct drm_encoder *encoder, | |||
245 | if ((val & VIDEO_DIP_ENABLE) == 0) | 245 | if ((val & VIDEO_DIP_ENABLE) == 0) |
246 | return false; | 246 | return false; |
247 | 247 | ||
248 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | 248 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) |
249 | return false; | 249 | return false; |
250 | 250 | ||
251 | return val & (VIDEO_DIP_ENABLE_AVI | | 251 | return val & (VIDEO_DIP_ENABLE_AVI | |
@@ -362,7 +362,7 @@ static bool vlv_infoframe_enabled(struct drm_encoder *encoder, | |||
362 | if ((val & VIDEO_DIP_ENABLE) == 0) | 362 | if ((val & VIDEO_DIP_ENABLE) == 0) |
363 | return false; | 363 | return false; |
364 | 364 | ||
365 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port)) | 365 | if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->base.port)) |
366 | return false; | 366 | return false; |
367 | 367 | ||
368 | return val & (VIDEO_DIP_ENABLE_AVI | | 368 | return val & (VIDEO_DIP_ENABLE_AVI | |
@@ -538,7 +538,7 @@ static void g4x_set_infoframes(struct drm_encoder *encoder, | |||
538 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | 538 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
539 | i915_reg_t reg = VIDEO_DIP_CTL; | 539 | i915_reg_t reg = VIDEO_DIP_CTL; |
540 | u32 val = I915_READ(reg); | 540 | u32 val = I915_READ(reg); |
541 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); | 541 | u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); |
542 | 542 | ||
543 | assert_hdmi_port_disabled(intel_hdmi); | 543 | assert_hdmi_port_disabled(intel_hdmi); |
544 | 544 | ||
@@ -689,7 +689,7 @@ static void ibx_set_infoframes(struct drm_encoder *encoder, | |||
689 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; | 689 | struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi; |
690 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); | 690 | i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe); |
691 | u32 val = I915_READ(reg); | 691 | u32 val = I915_READ(reg); |
692 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); | 692 | u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); |
693 | 693 | ||
694 | assert_hdmi_port_disabled(intel_hdmi); | 694 | assert_hdmi_port_disabled(intel_hdmi); |
695 | 695 | ||
@@ -785,7 +785,7 @@ static void vlv_set_infoframes(struct drm_encoder *encoder, | |||
785 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | 785 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); |
786 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); | 786 | i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); |
787 | u32 val = I915_READ(reg); | 787 | u32 val = I915_READ(reg); |
788 | u32 port = VIDEO_DIP_PORT(intel_dig_port->port); | 788 | u32 port = VIDEO_DIP_PORT(intel_dig_port->base.port); |
789 | 789 | ||
790 | assert_hdmi_port_disabled(intel_hdmi); | 790 | assert_hdmi_port_disabled(intel_hdmi); |
791 | 791 | ||
@@ -960,6 +960,8 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, | |||
960 | u32 tmp, flags = 0; | 960 | u32 tmp, flags = 0; |
961 | int dotclock; | 961 | int dotclock; |
962 | 962 | ||
963 | pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI); | ||
964 | |||
963 | tmp = I915_READ(intel_hdmi->hdmi_reg); | 965 | tmp = I915_READ(intel_hdmi->hdmi_reg); |
964 | 966 | ||
965 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) | 967 | if (tmp & SDVO_HSYNC_ACTIVE_HIGH) |
@@ -1207,7 +1209,8 @@ static void g4x_disable_hdmi(struct intel_encoder *encoder, | |||
1207 | const struct drm_connector_state *old_conn_state) | 1209 | const struct drm_connector_state *old_conn_state) |
1208 | { | 1210 | { |
1209 | if (old_crtc_state->has_audio) | 1211 | if (old_crtc_state->has_audio) |
1210 | intel_audio_codec_disable(encoder); | 1212 | intel_audio_codec_disable(encoder, |
1213 | old_crtc_state, old_conn_state); | ||
1211 | 1214 | ||
1212 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); | 1215 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
1213 | } | 1216 | } |
@@ -1217,7 +1220,8 @@ static void pch_disable_hdmi(struct intel_encoder *encoder, | |||
1217 | const struct drm_connector_state *old_conn_state) | 1220 | const struct drm_connector_state *old_conn_state) |
1218 | { | 1221 | { |
1219 | if (old_crtc_state->has_audio) | 1222 | if (old_crtc_state->has_audio) |
1220 | intel_audio_codec_disable(encoder); | 1223 | intel_audio_codec_disable(encoder, |
1224 | old_crtc_state, old_conn_state); | ||
1221 | } | 1225 | } |
1222 | 1226 | ||
1223 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, | 1227 | static void pch_post_disable_hdmi(struct intel_encoder *encoder, |
@@ -1227,24 +1231,34 @@ static void pch_post_disable_hdmi(struct intel_encoder *encoder, | |||
1227 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); | 1231 | intel_disable_hdmi(encoder, old_crtc_state, old_conn_state); |
1228 | } | 1232 | } |
1229 | 1233 | ||
1230 | static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv) | 1234 | static int intel_hdmi_source_max_tmds_clock(struct intel_encoder *encoder) |
1231 | { | 1235 | { |
1232 | if (IS_G4X(dev_priv)) | 1236 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1233 | return 165000; | 1237 | const struct ddi_vbt_port_info *info = |
1234 | else if (IS_GEMINILAKE(dev_priv)) | 1238 | &dev_priv->vbt.ddi_port_info[encoder->port]; |
1235 | return 594000; | 1239 | int max_tmds_clock; |
1236 | else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8) | 1240 | |
1237 | return 300000; | 1241 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
1242 | max_tmds_clock = 594000; | ||
1243 | else if (INTEL_GEN(dev_priv) >= 8 || IS_HASWELL(dev_priv)) | ||
1244 | max_tmds_clock = 300000; | ||
1245 | else if (INTEL_GEN(dev_priv) >= 5) | ||
1246 | max_tmds_clock = 225000; | ||
1238 | else | 1247 | else |
1239 | return 225000; | 1248 | max_tmds_clock = 165000; |
1249 | |||
1250 | if (info->max_tmds_clock) | ||
1251 | max_tmds_clock = min(max_tmds_clock, info->max_tmds_clock); | ||
1252 | |||
1253 | return max_tmds_clock; | ||
1240 | } | 1254 | } |
1241 | 1255 | ||
1242 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, | 1256 | static int hdmi_port_clock_limit(struct intel_hdmi *hdmi, |
1243 | bool respect_downstream_limits, | 1257 | bool respect_downstream_limits, |
1244 | bool force_dvi) | 1258 | bool force_dvi) |
1245 | { | 1259 | { |
1246 | struct drm_device *dev = intel_hdmi_to_dev(hdmi); | 1260 | struct intel_encoder *encoder = &hdmi_to_dig_port(hdmi)->base; |
1247 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev)); | 1261 | int max_tmds_clock = intel_hdmi_source_max_tmds_clock(encoder); |
1248 | 1262 | ||
1249 | if (respect_downstream_limits) { | 1263 | if (respect_downstream_limits) { |
1250 | struct intel_connector *connector = hdmi->attached_connector; | 1264 | struct intel_connector *connector = hdmi->attached_connector; |
@@ -1339,6 +1353,12 @@ static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state) | |||
1339 | if (HAS_GMCH_DISPLAY(dev_priv)) | 1353 | if (HAS_GMCH_DISPLAY(dev_priv)) |
1340 | return false; | 1354 | return false; |
1341 | 1355 | ||
1356 | if (crtc_state->pipe_bpp <= 8*3) | ||
1357 | return false; | ||
1358 | |||
1359 | if (!crtc_state->has_hdmi_sink) | ||
1360 | return false; | ||
1361 | |||
1342 | /* | 1362 | /* |
1343 | * HDMI 12bpc affects the clocks, so it's only possible | 1363 | * HDMI 12bpc affects the clocks, so it's only possible |
1344 | * when not cloning with other encoder types. | 1364 | * when not cloning with other encoder types. |
@@ -1464,9 +1484,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |||
1464 | * outputs. We also need to check that the higher clock still fits | 1484 | * outputs. We also need to check that the higher clock still fits |
1465 | * within limits. | 1485 | * within limits. |
1466 | */ | 1486 | */ |
1467 | if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi && | 1487 | if (hdmi_12bpc_possible(pipe_config) && |
1468 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK && | 1488 | hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK) { |
1469 | hdmi_12bpc_possible(pipe_config)) { | ||
1470 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); | 1489 | DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n"); |
1471 | desired_bpp = 12*3; | 1490 | desired_bpp = 12*3; |
1472 | 1491 | ||
@@ -1495,7 +1514,8 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, | |||
1495 | 1514 | ||
1496 | pipe_config->lane_count = 4; | 1515 | pipe_config->lane_count = 4; |
1497 | 1516 | ||
1498 | if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) { | 1517 | if (scdc->scrambling.supported && (INTEL_GEN(dev_priv) >= 10 || |
1518 | IS_GEMINILAKE(dev_priv))) { | ||
1499 | if (scdc->scrambling.low_rates) | 1519 | if (scdc->scrambling.low_rates) |
1500 | pipe_config->hdmi_scrambling = true; | 1520 | pipe_config->hdmi_scrambling = true; |
1501 | 1521 | ||
@@ -1529,7 +1549,7 @@ intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid) | |||
1529 | { | 1549 | { |
1530 | struct drm_i915_private *dev_priv = to_i915(connector->dev); | 1550 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
1531 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); | 1551 | struct intel_hdmi *hdmi = intel_attached_hdmi(connector); |
1532 | enum port port = hdmi_to_dig_port(hdmi)->port; | 1552 | enum port port = hdmi_to_dig_port(hdmi)->base.port; |
1533 | struct i2c_adapter *adapter = | 1553 | struct i2c_adapter *adapter = |
1534 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); | 1554 | intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus); |
1535 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); | 1555 | enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter); |
@@ -1613,12 +1633,9 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) | |||
1613 | 1633 | ||
1614 | intel_hdmi_unset_edid(connector); | 1634 | intel_hdmi_unset_edid(connector); |
1615 | 1635 | ||
1616 | if (intel_hdmi_set_edid(connector)) { | 1636 | if (intel_hdmi_set_edid(connector)) |
1617 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | ||
1618 | |||
1619 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | ||
1620 | status = connector_status_connected; | 1637 | status = connector_status_connected; |
1621 | } else | 1638 | else |
1622 | status = connector_status_disconnected; | 1639 | status = connector_status_disconnected; |
1623 | 1640 | ||
1624 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); | 1641 | intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS); |
@@ -1629,8 +1646,6 @@ intel_hdmi_detect(struct drm_connector *connector, bool force) | |||
1629 | static void | 1646 | static void |
1630 | intel_hdmi_force(struct drm_connector *connector) | 1647 | intel_hdmi_force(struct drm_connector *connector) |
1631 | { | 1648 | { |
1632 | struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector); | ||
1633 | |||
1634 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | 1649 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
1635 | connector->base.id, connector->name); | 1650 | connector->base.id, connector->name); |
1636 | 1651 | ||
@@ -1640,7 +1655,6 @@ intel_hdmi_force(struct drm_connector *connector) | |||
1640 | return; | 1655 | return; |
1641 | 1656 | ||
1642 | intel_hdmi_set_edid(connector); | 1657 | intel_hdmi_set_edid(connector); |
1643 | hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI; | ||
1644 | } | 1658 | } |
1645 | 1659 | ||
1646 | static int intel_hdmi_get_modes(struct drm_connector *connector) | 1660 | static int intel_hdmi_get_modes(struct drm_connector *connector) |
@@ -1673,10 +1687,9 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder, | |||
1673 | const struct drm_connector_state *conn_state) | 1687 | const struct drm_connector_state *conn_state) |
1674 | { | 1688 | { |
1675 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); | 1689 | struct intel_digital_port *dport = enc_to_dig_port(&encoder->base); |
1676 | struct drm_device *dev = encoder->base.dev; | 1690 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
1677 | struct drm_i915_private *dev_priv = to_i915(dev); | ||
1678 | 1691 | ||
1679 | vlv_phy_pre_encoder_enable(encoder); | 1692 | vlv_phy_pre_encoder_enable(encoder, pipe_config); |
1680 | 1693 | ||
1681 | /* HDMI 1.0V-2dB */ | 1694 | /* HDMI 1.0V-2dB */ |
1682 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, | 1695 | vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a, |
@@ -1697,7 +1710,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder, | |||
1697 | { | 1710 | { |
1698 | intel_hdmi_prepare(encoder, pipe_config); | 1711 | intel_hdmi_prepare(encoder, pipe_config); |
1699 | 1712 | ||
1700 | vlv_phy_pre_pll_enable(encoder); | 1713 | vlv_phy_pre_pll_enable(encoder, pipe_config); |
1701 | } | 1714 | } |
1702 | 1715 | ||
1703 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, | 1716 | static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, |
@@ -1706,14 +1719,14 @@ static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder, | |||
1706 | { | 1719 | { |
1707 | intel_hdmi_prepare(encoder, pipe_config); | 1720 | intel_hdmi_prepare(encoder, pipe_config); |
1708 | 1721 | ||
1709 | chv_phy_pre_pll_enable(encoder); | 1722 | chv_phy_pre_pll_enable(encoder, pipe_config); |
1710 | } | 1723 | } |
1711 | 1724 | ||
1712 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, | 1725 | static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder, |
1713 | const struct intel_crtc_state *old_crtc_state, | 1726 | const struct intel_crtc_state *old_crtc_state, |
1714 | const struct drm_connector_state *old_conn_state) | 1727 | const struct drm_connector_state *old_conn_state) |
1715 | { | 1728 | { |
1716 | chv_phy_post_pll_disable(encoder); | 1729 | chv_phy_post_pll_disable(encoder, old_crtc_state); |
1717 | } | 1730 | } |
1718 | 1731 | ||
1719 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, | 1732 | static void vlv_hdmi_post_disable(struct intel_encoder *encoder, |
@@ -1721,7 +1734,7 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder, | |||
1721 | const struct drm_connector_state *old_conn_state) | 1734 | const struct drm_connector_state *old_conn_state) |
1722 | { | 1735 | { |
1723 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ | 1736 | /* Reset lanes to avoid HDMI flicker (VLV w/a) */ |
1724 | vlv_phy_reset_lanes(encoder); | 1737 | vlv_phy_reset_lanes(encoder, old_crtc_state); |
1725 | } | 1738 | } |
1726 | 1739 | ||
1727 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, | 1740 | static void chv_hdmi_post_disable(struct intel_encoder *encoder, |
@@ -1734,7 +1747,7 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder, | |||
1734 | mutex_lock(&dev_priv->sb_lock); | 1747 | mutex_lock(&dev_priv->sb_lock); |
1735 | 1748 | ||
1736 | /* Assert data lane reset */ | 1749 | /* Assert data lane reset */ |
1737 | chv_data_lane_soft_reset(encoder, true); | 1750 | chv_data_lane_soft_reset(encoder, old_crtc_state, true); |
1738 | 1751 | ||
1739 | mutex_unlock(&dev_priv->sb_lock); | 1752 | mutex_unlock(&dev_priv->sb_lock); |
1740 | } | 1753 | } |
@@ -1747,7 +1760,7 @@ static void chv_hdmi_pre_enable(struct intel_encoder *encoder, | |||
1747 | struct drm_device *dev = encoder->base.dev; | 1760 | struct drm_device *dev = encoder->base.dev; |
1748 | struct drm_i915_private *dev_priv = to_i915(dev); | 1761 | struct drm_i915_private *dev_priv = to_i915(dev); |
1749 | 1762 | ||
1750 | chv_phy_pre_encoder_enable(encoder); | 1763 | chv_phy_pre_encoder_enable(encoder, pipe_config); |
1751 | 1764 | ||
1752 | /* FIXME: Program the support xxx V-dB */ | 1765 | /* FIXME: Program the support xxx V-dB */ |
1753 | /* Use 800mV-0dB */ | 1766 | /* Use 800mV-0dB */ |
@@ -2006,7 +2019,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |||
2006 | struct intel_encoder *intel_encoder = &intel_dig_port->base; | 2019 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
2007 | struct drm_device *dev = intel_encoder->base.dev; | 2020 | struct drm_device *dev = intel_encoder->base.dev; |
2008 | struct drm_i915_private *dev_priv = to_i915(dev); | 2021 | struct drm_i915_private *dev_priv = to_i915(dev); |
2009 | enum port port = intel_dig_port->port; | 2022 | enum port port = intel_encoder->port; |
2010 | 2023 | ||
2011 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", | 2024 | DRM_DEBUG_KMS("Adding HDMI connector on port %c\n", |
2012 | port_name(port)); | 2025 | port_name(port)); |
@@ -2024,7 +2037,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, | |||
2024 | connector->doublescan_allowed = 0; | 2037 | connector->doublescan_allowed = 0; |
2025 | connector->stereo_allowed = 1; | 2038 | connector->stereo_allowed = 1; |
2026 | 2039 | ||
2027 | if (IS_GEMINILAKE(dev_priv)) | 2040 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) |
2028 | connector->ycbcr_420_allowed = true; | 2041 | connector->ycbcr_420_allowed = true; |
2029 | 2042 | ||
2030 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); | 2043 | intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port); |
@@ -2126,7 +2139,6 @@ void intel_hdmi_init(struct drm_i915_private *dev_priv, | |||
2126 | if (IS_G4X(dev_priv)) | 2139 | if (IS_G4X(dev_priv)) |
2127 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; | 2140 | intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI; |
2128 | 2141 | ||
2129 | intel_dig_port->port = port; | ||
2130 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; | 2142 | intel_dig_port->hdmi.hdmi_reg = hdmi_reg; |
2131 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; | 2143 | intel_dig_port->dp.output_reg = INVALID_MMIO_REG; |
2132 | intel_dig_port->max_lanes = 4; | 2144 | intel_dig_port->max_lanes = 4; |