diff options
author | Marek Olšák <marek.olsak@amd.com> | 2018-04-03 13:05:03 -0400 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2018-05-15 14:43:32 -0400 |
commit | d240cd9eddd943dbe0267d081697195ff1e90b65 (patch) | |
tree | ff9648c93738e223b8da42489f5d64aa8caa9895 /drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | |
parent | 3f188453faf7ba5b59e8064df4afffbc946e25ec (diff) |
drm/amdgpu: optionally do a writeback but don't invalidate TC for IB fences
There is a new IB flag that enables this new behavior.
Full invalidation is unnecessary for RELEASE_MEM and doesn't make sense
when draw calls from two adjacent gfx IBs run in parallel. This will be
the new default for Mesa.
v2: bump the version
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 |
1 files changed, 6 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 311589e02d17..f70eeed9ed76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | |||
@@ -127,6 +127,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, | |||
127 | struct amdgpu_vm *vm; | 127 | struct amdgpu_vm *vm; |
128 | uint64_t fence_ctx; | 128 | uint64_t fence_ctx; |
129 | uint32_t status = 0, alloc_size; | 129 | uint32_t status = 0, alloc_size; |
130 | unsigned fence_flags = 0; | ||
130 | 131 | ||
131 | unsigned i; | 132 | unsigned i; |
132 | int r = 0; | 133 | int r = 0; |
@@ -227,7 +228,10 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, | |||
227 | #endif | 228 | #endif |
228 | amdgpu_asic_invalidate_hdp(adev, ring); | 229 | amdgpu_asic_invalidate_hdp(adev, ring); |
229 | 230 | ||
230 | r = amdgpu_fence_emit(ring, f); | 231 | if (ib->flags & AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE) |
232 | fence_flags |= AMDGPU_FENCE_FLAG_TC_WB_ONLY; | ||
233 | |||
234 | r = amdgpu_fence_emit(ring, f, fence_flags); | ||
231 | if (r) { | 235 | if (r) { |
232 | dev_err(adev->dev, "failed to emit fence (%d)\n", r); | 236 | dev_err(adev->dev, "failed to emit fence (%d)\n", r); |
233 | if (job && job->vmid) | 237 | if (job && job->vmid) |
@@ -242,7 +246,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, | |||
242 | /* wrap the last IB with fence */ | 246 | /* wrap the last IB with fence */ |
243 | if (job && job->uf_addr) { | 247 | if (job && job->uf_addr) { |
244 | amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, | 248 | amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, |
245 | AMDGPU_FENCE_FLAG_64BIT); | 249 | fence_flags | AMDGPU_FENCE_FLAG_64BIT); |
246 | } | 250 | } |
247 | 251 | ||
248 | if (patch_offset != ~0 && ring->funcs->patch_cond_exec) | 252 | if (patch_offset != ~0 && ring->funcs->patch_cond_exec) |