Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This starts to support NVIDIA volta hardware with nouveau, and adds
  amdgpu support for the GPU in the Kabylake-G (the intel + radeon
  single package chip), along with some initial Intel icelake enabling.

  Summary:

  New Drivers:
   - v3d - driver for broadcom V3D V3.x+ hardware
   - xen-front - XEN PV display frontend

  core:
   - handle zpos normalization in the core
   - stop looking at legacy pointers in atomic paths
   - improved scheduler documentation
   - improved aspect ratio validation
   - aspect ratio support for 64:27 and 256:135
   - drop unused control node code.

  i915:
   - Icelake (ICL) enabling
   - GuC/HuC refactoring
   - PSR/PSR2 enabling and fixes
   - DPLL management refactoring
   - DP MST fixes
   - NV12 enabling
   - HDCP improvements
   - GEM/Execlist/reset improvements
   - GVT improvements
   - stolen memory first 4k fix

  amdgpu:
   - Vega 20 support
   - VEGAM support (Kabylake-G)
   - preOS scanout buffer reservation
   - power management gfxoff support for raven
   - SR-IOV fixes
   - Vega10 power profiles and clock voltage control
   - scatter/gather display support on CZ/ST

  amdkfd:
   - GFX9 dGPU support
   - userptr memory mapping

  nouveau:
   - major refactoring for Volta GV100 support

  tda998x:
   - HDMI i2c CEC support

  etnaviv:
   - removed unused logging code
   - license text cleanups
   - MMU handling improvements
   - timeout fence fix for 50 days uptime

  tegra:
   - IOMMU support in gr2d/gr3d drivers
   - zpos support

  vc4:
   - syncobj support
   - CTM, plane alpha and async cursor support

  analogix_dp:
   - HPD and aux chan fixes

  sun4i:
   - MIPI DSI support

  tilcdc:
   - clock divider fixes for OMAP-l138 LCDK board

  rcar-du:
   - R8A77965 support
   - dma-buf fences fixes
   - hardware indexed crtc/du group handling
   - generic zplane property support

  atmel-hclcdc:
   - generic zplane property support

  mediatek:
   - use generic video mode function

  exynos:
   - S5PV210 FIMD variant support
   - IPP v2 framework
   - more HW overlays support"

* tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits)
  drm/amdgpu: fix 32-bit build warning
  drm/exynos: fimc: signedness bug in fimc_setup_clocks()
  drm/exynos: scaler: fix static checker warning
  drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC
  drm/amd/display: Remove use of division operator for long longs
  drm/amdgpu: Update GFX info structure to match what vega20 used
  drm/amdgpu/pp: remove duplicate assignment
  drm/sched: add rcu_barrier after entity fini
  drm/amdgpu: move VM BOs on LRU again
  drm/amdgpu: consistenly use VM moved flag
  drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories
  drm/amdgpu: further optimize amdgpu_vm_handle_moved
  drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2
  drm/amdgpu: rework VM state machine lock handling v2
  drm/amdgpu: Add runtime VCN PG support
  drm/amdgpu: Enable VCN static PG by default on RV
  drm/amdgpu: Add VCN static PG support on RV
  drm/amdgpu: Enable VCN CG by default on RV
  drm/amdgpu: Add static CG control for VCN on RV
  drm/exynos: Fix default value for zpos plane property
  ...

1 files changed, 37 insertions, 13 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 46b9ea4e6103..2c8e27370284 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -48,17 +48,25 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
                              struct drm_gem_object **obj)
 {
         struct amdgpu_bo *bo;
+        struct amdgpu_bo_param bp;
         int r;
 
+        memset(&bp, 0, sizeof(bp));
         *obj = NULL;
         /* At least align on page size */
         if (alignment < PAGE_SIZE) {
                 alignment = PAGE_SIZE;
         }
 
+        bp.size = size;
+        bp.byte_align = alignment;
+        bp.type = type;
+        bp.resv = resv;
+        bp.preferred_domain = initial_domain;
 retry:
-        r = amdgpu_bo_create(adev, size, alignment, initial_domain,
-                             flags, type, resv, &bo);
+        bp.flags = flags;
+        bp.domain = initial_domain;
+        r = amdgpu_bo_create(adev, &bp, &bo);
         if (r) {
                 if (r != -ERESTARTSYS) {
                         if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) {
@@ -221,12 +229,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
                 return -EINVAL;
 
         /* reject invalid gem domains */
-        if (args->in.domains & ~(AMDGPU_GEM_DOMAIN_CPU |
-                                 AMDGPU_GEM_DOMAIN_GTT |
-                                 AMDGPU_GEM_DOMAIN_VRAM |
-                                 AMDGPU_GEM_DOMAIN_GDS |
-                                 AMDGPU_GEM_DOMAIN_GWS |
-                                 AMDGPU_GEM_DOMAIN_OA))
+        if (args->in.domains & ~AMDGPU_GEM_DOMAIN_MASK)
                 return -EINVAL;
 
         /* create a gem object to contain this object in */
@@ -771,16 +774,23 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 }
 
 #if defined(CONFIG_DEBUG_FS)
+
+#define amdgpu_debugfs_gem_bo_print_flag(m, bo, flag)   \
+        if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
+                seq_printf((m), " " #flag);             \
+        }
+
 static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
 {
         struct drm_gem_object *gobj = ptr;
         struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
         struct seq_file *m = data;
 
+        struct dma_buf_attachment *attachment;
+        struct dma_buf *dma_buf;
         unsigned domain;
         const char *placement;
         unsigned pin_count;
-        uint64_t offset;
 
         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
         switch (domain) {
@@ -798,13 +808,27 @@ static int amdgpu_debugfs_gem_bo_info(int id, void *ptr, void *data)
         seq_printf(m, "\t0x%08x: %12ld byte %s",
                    id, amdgpu_bo_size(bo), placement);
 
-        offset = READ_ONCE(bo->tbo.mem.start);
-        if (offset != AMDGPU_BO_INVALID_OFFSET)
-                seq_printf(m, " @ 0x%010Lx", offset);
-
         pin_count = READ_ONCE(bo->pin_count);
         if (pin_count)
                 seq_printf(m, " pin count %d", pin_count);
+
+        dma_buf = READ_ONCE(bo->gem_base.dma_buf);
+        attachment = READ_ONCE(bo->gem_base.import_attach);
+
+        if (attachment)
+                seq_printf(m, " imported from %p", dma_buf);
+        else if (dma_buf)
+                seq_printf(m, " exported as %p", dma_buf);
+
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, NO_CPU_ACCESS);
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, CPU_GTT_USWC);
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CLEARED);
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, SHADOW);
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, VM_ALWAYS_VALID);
+        amdgpu_debugfs_gem_bo_print_flag(m, bo, EXPLICIT_SYNC);
+
         seq_printf(m, "\n");
 
         return 0;