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authorAlan Tull <atull@opensource.altera.com>2016-11-01 15:14:26 -0400
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2016-11-10 11:03:35 -0500
commit1df2865f8dd9d56cb76aa7aa1298921e7bece2af (patch)
tree13bfefb2d88b52d1d326867d91dd0c016cc83075 /drivers/fpga/fpga-mgr.c
parenta33ddf80b67a79530c3aa2c9f87e2bbd3aea3e22 (diff)
fpga-mgr: add fpga image information struct
This patch adds a minor change in the FPGA Manager API to hold information that is specific to an FPGA image file. This change is expected to bring little, if any, pain. The socfpga and zynq drivers are fixed up in this patch. An FPGA image file will have particulars that affect how the image is programmed to the FPGA. One example is that current 'flags' currently has one bit which shows whether the FPGA image was built for full reconfiguration or partial reconfiguration. Another example is timeout values for enabling or disabling the bridges in the FPGA. As the complexity of the FPGA design increases, the bridges in the FPGA may take longer times to enable or disable. This patch adds a new 'struct fpga_image_info', moves the current 'u32 flags' to it. Two other image-specific u32's are added for the bridge enable/disable timeouts. The FPGA Manager API functions are changed, replacing the 'u32 flag' parameter with a pointer to struct fpga_image_info. Subsequent patches fix the existing low level FPGA manager drivers. Signed-off-by: Alan Tull <atull@opensource.altera.com> Acked-by: Moritz Fischer <moritz.fischer@ettus.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
-rw-r--r--drivers/fpga/fpga-mgr.c17
1 files changed, 9 insertions, 8 deletions
diff --git a/drivers/fpga/fpga-mgr.c b/drivers/fpga/fpga-mgr.c
index b690e65d55fe..79ce2eea44db 100644
--- a/drivers/fpga/fpga-mgr.c
+++ b/drivers/fpga/fpga-mgr.c
@@ -32,7 +32,7 @@ static struct class *fpga_mgr_class;
32/** 32/**
33 * fpga_mgr_buf_load - load fpga from image in buffer 33 * fpga_mgr_buf_load - load fpga from image in buffer
34 * @mgr: fpga manager 34 * @mgr: fpga manager
35 * @flags: flags setting fpga confuration modes 35 * @info: fpga image specific information
36 * @buf: buffer contain fpga image 36 * @buf: buffer contain fpga image
37 * @count: byte count of buf 37 * @count: byte count of buf
38 * 38 *
@@ -44,8 +44,8 @@ static struct class *fpga_mgr_class;
44 * 44 *
45 * Return: 0 on success, negative error code otherwise. 45 * Return: 0 on success, negative error code otherwise.
46 */ 46 */
47int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf, 47int fpga_mgr_buf_load(struct fpga_manager *mgr, struct fpga_image_info *info,
48 size_t count) 48 const char *buf, size_t count)
49{ 49{
50 struct device *dev = &mgr->dev; 50 struct device *dev = &mgr->dev;
51 int ret; 51 int ret;
@@ -56,7 +56,7 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf,
56 * ready to receive an FPGA image. 56 * ready to receive an FPGA image.
57 */ 57 */
58 mgr->state = FPGA_MGR_STATE_WRITE_INIT; 58 mgr->state = FPGA_MGR_STATE_WRITE_INIT;
59 ret = mgr->mops->write_init(mgr, flags, buf, count); 59 ret = mgr->mops->write_init(mgr, info, buf, count);
60 if (ret) { 60 if (ret) {
61 dev_err(dev, "Error preparing FPGA for writing\n"); 61 dev_err(dev, "Error preparing FPGA for writing\n");
62 mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR; 62 mgr->state = FPGA_MGR_STATE_WRITE_INIT_ERR;
@@ -79,7 +79,7 @@ int fpga_mgr_buf_load(struct fpga_manager *mgr, u32 flags, const char *buf,
79 * steps to finish and set the FPGA into operating mode. 79 * steps to finish and set the FPGA into operating mode.
80 */ 80 */
81 mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE; 81 mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE;
82 ret = mgr->mops->write_complete(mgr, flags); 82 ret = mgr->mops->write_complete(mgr, info);
83 if (ret) { 83 if (ret) {
84 dev_err(dev, "Error after writing image data to FPGA\n"); 84 dev_err(dev, "Error after writing image data to FPGA\n");
85 mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR; 85 mgr->state = FPGA_MGR_STATE_WRITE_COMPLETE_ERR;
@@ -94,7 +94,7 @@ EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
94/** 94/**
95 * fpga_mgr_firmware_load - request firmware and load to fpga 95 * fpga_mgr_firmware_load - request firmware and load to fpga
96 * @mgr: fpga manager 96 * @mgr: fpga manager
97 * @flags: flags setting fpga confuration modes 97 * @info: fpga image specific information
98 * @image_name: name of image file on the firmware search path 98 * @image_name: name of image file on the firmware search path
99 * 99 *
100 * Request an FPGA image using the firmware class, then write out to the FPGA. 100 * Request an FPGA image using the firmware class, then write out to the FPGA.
@@ -105,7 +105,8 @@ EXPORT_SYMBOL_GPL(fpga_mgr_buf_load);
105 * 105 *
106 * Return: 0 on success, negative error code otherwise. 106 * Return: 0 on success, negative error code otherwise.
107 */ 107 */
108int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags, 108int fpga_mgr_firmware_load(struct fpga_manager *mgr,
109 struct fpga_image_info *info,
109 const char *image_name) 110 const char *image_name)
110{ 111{
111 struct device *dev = &mgr->dev; 112 struct device *dev = &mgr->dev;
@@ -123,7 +124,7 @@ int fpga_mgr_firmware_load(struct fpga_manager *mgr, u32 flags,
123 return ret; 124 return ret;
124 } 125 }
125 126
126 ret = fpga_mgr_buf_load(mgr, flags, fw->data, fw->size); 127 ret = fpga_mgr_buf_load(mgr, info, fw->data, fw->size);
127 128
128 release_firmware(fw); 129 release_firmware(fw);
129 130