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authorMax Filippov <jcmvbkbc@gmail.com>2019-05-12 23:28:25 -0400
committerMax Filippov <jcmvbkbc@gmail.com>2019-07-08 13:04:48 -0400
commitd6d5f19e21d98c0607ff029e4e2e508d4cdd1d5a (patch)
tree1780d36ac99c16f8ed506948a020017e84a89a9f /arch/xtensa/lib/memset.S
parent831c4f3da83e260df943dfb982d77cef5cba2c49 (diff)
xtensa: abstract 'entry' and 'retw' in assembly code
Provide abi_entry, abi_entry_default, abi_ret and abi_ret_default macros that allocate aligned stack frame in windowed and call0 ABIs. Provide XTENSA_SPILL_STACK_RESERVE macro that specifies required stack frame size when register spilling is involved. Replace all uses of 'entry' and 'retw' with the above macros. This makes most of the xtensa assembly code ready for XEA3 and call0 ABI. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Diffstat (limited to 'arch/xtensa/lib/memset.S')
-rw-r--r--arch/xtensa/lib/memset.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/xtensa/lib/memset.S b/arch/xtensa/lib/memset.S
index 8632eacbdc80..59b1524fd601 100644
--- a/arch/xtensa/lib/memset.S
+++ b/arch/xtensa/lib/memset.S
@@ -34,7 +34,7 @@
34ENTRY(__memset) 34ENTRY(__memset)
35WEAK(memset) 35WEAK(memset)
36 36
37 entry sp, 16 # minimal stack frame 37 abi_entry_default
38 # a2/ dst, a3/ c, a4/ length 38 # a2/ dst, a3/ c, a4/ length
39 extui a3, a3, 0, 8 # mask to just 8 bits 39 extui a3, a3, 0, 8 # mask to just 8 bits
40 slli a7, a3, 8 # duplicate character in all bytes of word 40 slli a7, a3, 8 # duplicate character in all bytes of word
@@ -48,7 +48,7 @@ WEAK(memset)
48 srli a7, a4, 4 # number of loop iterations with 16B 48 srli a7, a4, 4 # number of loop iterations with 16B
49 # per iteration 49 # per iteration
50 bnez a4, .Laligned 50 bnez a4, .Laligned
51 retw 51 abi_ret_default
52 52
53/* 53/*
54 * Destination is word-aligned. 54 * Destination is word-aligned.
@@ -95,7 +95,7 @@ EX(10f) s16i a3, a5, 0
95EX(10f) s8i a3, a5, 0 95EX(10f) s8i a3, a5, 0
96.L5: 96.L5:
97.Lret1: 97.Lret1:
98 retw 98 abi_ret_default
99 99
100/* 100/*
101 * Destination is unaligned 101 * Destination is unaligned
@@ -139,7 +139,7 @@ EX(10f) s8i a3, a5, 0
139 blt a5, a6, .Lbyteloop 139 blt a5, a6, .Lbyteloop
140#endif /* !XCHAL_HAVE_LOOPS */ 140#endif /* !XCHAL_HAVE_LOOPS */
141.Lbytesetdone: 141.Lbytesetdone:
142 retw 142 abi_ret_default
143 143
144ENDPROC(__memset) 144ENDPROC(__memset)
145 145
@@ -150,4 +150,4 @@ ENDPROC(__memset)
150 150
15110: 15110:
152 movi a2, 0 152 movi a2, 0
153 retw 153 abi_ret_default