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authorZang Roy-r61911 <tie-fei.zang@freescale.com>2007-07-10 06:46:35 -0400
committerKumar Gala <galak@kernel.crashing.org>2007-07-23 11:27:07 -0400
commit9ac4dd301eebb3cd8de801e02bfc91f296e56f63 (patch)
tree9f4dbb37dc809c94156151f997093ac00a38b928 /arch/powerpc/sysdev/fsl_pci.c
parent55c44991e2910519bab274c857d95a08100ff5f7 (diff)
[POWERPC] Rewrite Freescale PCI/PCIe support for 8{3,5,6}xx
Rewrite the Freescale PCI code to support PCI on 83xx/85xx/86xx and PCIe on 85xx/86xx. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/sysdev/fsl_pci.c')
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c244
1 files changed, 105 insertions, 139 deletions
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 24ba1b6b31fb..10c47b56702e 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,136 +1,98 @@
1/* 1/*
2 * MPC86XX pci setup code 2 * MPC85xx/86xx PCI/PCIE support routing.
3 * 3 *
4 * Recode: ZHANG WEI <wei.zhang@freescale.com> 4 * Copyright 2007 Freescale Semiconductor, Inc
5 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
6 * 5 *
7 * Copyright 2006 Freescale Semiconductor Inc. 6 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
7 * Recode: ZHANG WEI <wei.zhang@freescale.com>
8 * Rewrite the routing for Frescale PCI and PCI Express
9 * Roy Zang <tie-fei.zang@freescale.com>
8 * 10 *
9 * This program is free software; you can redistribute it and/or modify it 11 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the 12 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your 13 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version. 14 * option) any later version.
13 */ 15 */
14 16#include <linux/kernel.h>
15#include <linux/types.h>
16#include <linux/module.h>
17#include <linux/init.h>
18#include <linux/pci.h> 17#include <linux/pci.h>
19#include <linux/serial.h> 18#include <linux/delay.h>
19#include <linux/string.h>
20#include <linux/init.h>
21#include <linux/bootmem.h>
20 22
21#include <asm/system.h>
22#include <asm/atomic.h>
23#include <asm/io.h> 23#include <asm/io.h>
24#include <asm/prom.h> 24#include <asm/prom.h>
25#include <asm/pci-bridge.h> 25#include <asm/pci-bridge.h>
26#include <asm/machdep.h>
26#include <sysdev/fsl_soc.h> 27#include <sysdev/fsl_soc.h>
27#include <sysdev/fsl_pci.h> 28#include <sysdev/fsl_pci.h>
28 29
29#include "../platforms/86xx/mpc86xx.h" 30/* atmu setup for fsl pci/pcie controller */
30 31void __init setup_pci_atmu(struct pci_controller *hose, struct resource *rsrc)
31#undef DEBUG
32
33#ifdef DEBUG
34#define DBG(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
35#else
36#define DBG(fmt, args...)
37#endif
38
39struct pcie_outbound_window_regs {
40 uint pexotar; /* 0x.0 - PCI Express outbound translation address register */
41 uint pexotear; /* 0x.4 - PCI Express outbound translation extended address register */
42 uint pexowbar; /* 0x.8 - PCI Express outbound window base address register */
43 char res1[4];
44 uint pexowar; /* 0x.10 - PCI Express outbound window attributes register */
45 char res2[12];
46};
47
48struct pcie_inbound_window_regs {
49 uint pexitar; /* 0x.0 - PCI Express inbound translation address register */
50 char res1[4];
51 uint pexiwbar; /* 0x.8 - PCI Express inbound window base address register */
52 uint pexiwbear; /* 0x.c - PCI Express inbound window base extended address register */
53 uint pexiwar; /* 0x.10 - PCI Express inbound window attributes register */
54 char res2[12];
55};
56
57static void __init setup_pcie_atmu(struct pci_controller *hose, struct resource *rsrc)
58{ 32{
59 volatile struct ccsr_pex *pcie; 33 struct ccsr_pci __iomem *pci;
60 volatile struct pcie_outbound_window_regs *pcieow; 34 int i;
61 volatile struct pcie_inbound_window_regs *pcieiw;
62 int i = 0;
63 35
64 DBG("PCIE memory map start 0x%x, size 0x%x\n", rsrc->start, 36 pr_debug("PCI memory map start 0x%x, size 0x%x\n", rsrc->start,
65 rsrc->end - rsrc->start + 1); 37 rsrc->end - rsrc->start + 1);
66 pcie = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 38 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
67 39
68 /* Disable all windows (except pexowar0 since its ignored) */ 40 /* Disable all windows (except powar0 since its ignored) */
69 pcie->pexowar1 = 0; 41 for(i = 1; i < 5; i++)
70 pcie->pexowar2 = 0; 42 out_be32(&pci->pow[i].powar, 0);
71 pcie->pexowar3 = 0; 43 for(i = 0; i < 3; i++)
72 pcie->pexowar4 = 0; 44 out_be32(&pci->piw[i].piwar, 0);
73 pcie->pexiwar1 = 0; 45
74 pcie->pexiwar2 = 0; 46 /* Setup outbound MEM window */
75 pcie->pexiwar3 = 0; 47 for(i = 0; i < 3; i++)
76 48 if (hose->mem_resources[i].flags & IORESOURCE_MEM){
77 pcieow = (struct pcie_outbound_window_regs *)&pcie->pexotar1; 49 pr_debug("PCI MEM resource start 0x%08x, size 0x%08x.\n",
78 pcieiw = (struct pcie_inbound_window_regs *)&pcie->pexitar1; 50 hose->mem_resources[i].start,
79 51 hose->mem_resources[i].end
80 /* Setup outbound MEM window */ 52 - hose->mem_resources[i].start + 1);
81 for(i = 0; i < 3; i++) 53 out_be32(&pci->pow[i+1].potar,
82 if (hose->mem_resources[i].flags & IORESOURCE_MEM){ 54 (hose->mem_resources[i].start >> 12)
83 DBG("PCIE MEM resource start 0x%08x, size 0x%08x.\n", 55 & 0x000fffff);
84 hose->mem_resources[i].start, 56 out_be32(&pci->pow[i+1].potear, 0);
85 hose->mem_resources[i].end 57 out_be32(&pci->pow[i+1].powbar,
86 - hose->mem_resources[i].start + 1); 58 (hose->mem_resources[i].start >> 12)
87 pcieow->pexotar = (hose->mem_resources[i].start) >> 12 59 & 0x000fffff);
88 & 0x000fffff; 60 /* Enable, Mem R/W */
89 pcieow->pexotear = 0; 61 out_be32(&pci->pow[i+1].powar, 0x80044000
90 pcieow->pexowbar = (hose->mem_resources[i].start) >> 12 62 | (__ilog2(hose->mem_resources[i].end
91 & 0x000fffff; 63 - hose->mem_resources[i].start + 1) - 1));
92 /* Enable, Mem R/W */ 64 }
93 pcieow->pexowar = 0x80044000 | 65
94 (__ilog2(hose->mem_resources[i].end 66 /* Setup outbound IO window */
95 - hose->mem_resources[i].start + 1) 67 if (hose->io_resource.flags & IORESOURCE_IO){
96 - 1); 68 pr_debug("PCI IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n",
97 pcieow++; 69 hose->io_resource.start,
98 } 70 hose->io_resource.end - hose->io_resource.start + 1,
99 71 hose->io_base_phys);
100 /* Setup outbound IO window */ 72 out_be32(&pci->pow[i+1].potar, (hose->io_resource.start >> 12)
101 if (hose->io_resource.flags & IORESOURCE_IO){ 73 & 0x000fffff);
102 DBG("PCIE IO resource start 0x%08x, size 0x%08x, phy base 0x%08x.\n", 74 out_be32(&pci->pow[i+1].potear, 0);
103 hose->io_resource.start, 75 out_be32(&pci->pow[i+1].powbar, (hose->io_base_phys >> 12)
104 hose->io_resource.end - hose->io_resource.start + 1, 76 & 0x000fffff);
105 hose->io_base_phys); 77 /* Enable, IO R/W */
106 pcieow->pexotar = (hose->io_resource.start) >> 12 & 0x000fffff; 78 out_be32(&pci->pow[i+1].powar, 0x80088000
107 pcieow->pexotear = 0; 79 | (__ilog2(hose->io_resource.end
108 pcieow->pexowbar = (hose->io_base_phys) >> 12 & 0x000fffff; 80 - hose->io_resource.start + 1) - 1));
109 /* Enable, IO R/W */ 81 }
110 pcieow->pexowar = 0x80088000 | (__ilog2(hose->io_resource.end 82
111 - hose->io_resource.start + 1) - 1); 83 /* Setup 2G inbound Memory Window @ 1 */
112 } 84 out_be32(&pci->piw[2].pitar, 0x00000000);
113 85 out_be32(&pci->piw[2].piwbar,0x00000000);
114 /* Setup 2G inbound Memory Window @ 0 */ 86 out_be32(&pci->piw[2].piwar, PIWAR_2G);
115 pcieiw->pexitar = 0x00000000;
116 pcieiw->pexiwbar = 0x00000000;
117 /* Enable, Prefetch, Local Mem, Snoop R/W, 2G */
118 pcieiw->pexiwar = 0xa0f5501e;
119} 87}
120 88
121static void __init 89void __init setup_pci_cmd(struct pci_controller *hose)
122mpc86xx_setup_pcie(struct pci_controller *hose, u32 pcie_offset, u32 pcie_size)
123{ 90{
124 u16 cmd; 91 u16 cmd;
125
126 DBG("PCIE host controller register offset 0x%08x, size 0x%08x.\n",
127 pcie_offset, pcie_size);
128
129 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd); 92 early_read_config_word(hose, 0, 0, PCI_COMMAND, &cmd);
130 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY 93 cmd |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY
131 | PCI_COMMAND_IO; 94 | PCI_COMMAND_IO;
132 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd); 95 early_write_config_word(hose, 0, 0, PCI_COMMAND, cmd);
133
134 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80); 96 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
135} 97}
136 98
@@ -167,72 +129,76 @@ static void __devinit quirk_fsl_pcie_transparent(struct pci_dev *dev)
167 } 129 }
168} 130}
169 131
132int __init fsl_pcie_check_link(struct pci_controller *hose)
133{
134 u16 val;
135 early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val);
136 if (val < PCIE_LTSSM_L0)
137 return 1;
138 return 0;
139}
170 140
171DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent); 141int __init fsl_add_bridge(struct device_node *dev, int is_primary)
172DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
173
174#define PCIE_LTSSM 0x404 /* PCIe Link Training and Status */
175#define PCIE_LTSSM_L0 0x16 /* L0 state */
176
177int __init mpc86xx_add_bridge(struct device_node *dev)
178{ 142{
179 int len; 143 int len;
180 struct pci_controller *hose; 144 struct pci_controller *hose;
181 struct resource rsrc; 145 struct resource rsrc;
182 const int *bus_range; 146 const int *bus_range;
183 int has_address = 0;
184 int primary = 0;
185 u16 val;
186 147
187 DBG("Adding PCIE host bridge %s\n", dev->full_name); 148 pr_debug("Adding PCI host bridge %s\n", dev->full_name);
188 149
189 /* Fetch host bridge registers address */ 150 /* Fetch host bridge registers address */
190 has_address = (of_address_to_resource(dev, 0, &rsrc) == 0); 151 if (of_address_to_resource(dev, 0, &rsrc)) {
152 printk(KERN_WARNING "Can't get pci register base!");
153 return -ENOMEM;
154 }
191 155
192 /* Get bus range if any */ 156 /* Get bus range if any */
193 bus_range = of_get_property(dev, "bus-range", &len); 157 bus_range = of_get_property(dev, "bus-range", &len);
194 if (bus_range == NULL || len < 2 * sizeof(int)) 158 if (bus_range == NULL || len < 2 * sizeof(int))
195 printk(KERN_WARNING "Can't get bus-range for %s, assume" 159 printk(KERN_WARNING "Can't get bus-range for %s, assume"
196 " bus 0\n", dev->full_name); 160 " bus 0\n", dev->full_name);
197 161
198 pci_assign_all_buses = 1; 162 pci_assign_all_buses = 1;
199 hose = pcibios_alloc_controller(dev); 163 hose = pcibios_alloc_controller(dev);
200 if (!hose) 164 if (!hose)
201 return -ENOMEM; 165 return -ENOMEM;
202 166
203 hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
204 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
205
206 hose->first_busno = bus_range ? bus_range[0] : 0x0; 167 hose->first_busno = bus_range ? bus_range[0] : 0x0;
207 hose->last_busno = bus_range ? bus_range[1] : 0xff; 168 hose->last_busno = bus_range ? bus_range[1] : 0xff;
208 169
209 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4); 170 /* check PCI express bridge */
210 171 if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") ||
211 /* Probe the hose link training status */ 172 of_device_is_compatible(dev, "fsl,mpc8641-pcie"))
212 early_read_config_word(hose, 0, 0, PCIE_LTSSM, &val); 173 hose->indirect_type = PPC_INDIRECT_TYPE_EXT_REG |
213 if (val < PCIE_LTSSM_L0) 174 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS;
214 return -ENXIO;
215 175
216 /* Setup the PCIE host controller. */ 176 setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4);
217 mpc86xx_setup_pcie(hose, rsrc.start, rsrc.end - rsrc.start + 1); 177 setup_pci_cmd(hose);
218 178
219 if ((rsrc.start & 0xfffff) == 0x8000) 179 /* check PCI express link status */
220 primary = 1; 180 if (of_device_is_compatible(dev, "fsl,mpc8548-pcie") ||
181 of_device_is_compatible(dev, "fsl,mpc8641-pcie"))
182 if (fsl_pcie_check_link(hose))
183 return -ENXIO;
221 184
222 printk(KERN_INFO "Found MPC86xx PCIE host bridge at 0x%08lx. " 185 printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx."
223 "Firmware bus number: %d->%d\n", 186 "Firmware bus number: %d->%d\n",
224 (unsigned long) rsrc.start, 187 (unsigned long long)rsrc.start, hose->first_busno,
225 hose->first_busno, hose->last_busno); 188 hose->last_busno);
226 189
227 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n", 190 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
228 hose, hose->cfg_addr, hose->cfg_data); 191 hose, hose->cfg_addr, hose->cfg_data);
229 192
230 /* Interpret the "ranges" property */ 193 /* Interpret the "ranges" property */
231 /* This also maps the I/O region and sets isa_io/mem_base */ 194 /* This also maps the I/O region and sets isa_io/mem_base */
232 pci_process_bridge_OF_ranges(hose, dev, primary); 195 pci_process_bridge_OF_ranges(hose, dev, is_primary);
233 196
234 /* Setup PEX window registers */ 197 /* Setup PEX window registers */
235 setup_pcie_atmu(hose, &rsrc); 198 setup_pci_atmu(hose, &rsrc);
236 199
237 return 0; 200 return 0;
238} 201}
202
203DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7010, quirk_fsl_pcie_transparent);
204DECLARE_PCI_FIXUP_EARLY(0x1957, 0x7011, quirk_fsl_pcie_transparent);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-26 22:41:18 -0500