diff options
| author | Christophe Leroy <christophe.leroy@c-s.fr> | 2018-08-09 04:14:41 -0400 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-08-10 08:12:35 -0400 |
| commit | fa54a981ea7a852c145b05c95abba11e81fc1157 (patch) | |
| tree | cea88a64419bfe83d3e94e84cd154c0595278fa5 /arch/powerpc/lib | |
| parent | cd813e1cd7122f2c261dce5b54d1e0c97f80e1a5 (diff) | |
powerpc/lib: Use patch_site to patch copy_32 functions once cache is enabled
The symbol memcpy_nocache_branch defined in order to allow patching
of memset function once cache is enabled leads to confusing reports
by perf tool.
Using the new patch_site functionality solves this issue.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/lib')
| -rw-r--r-- | arch/powerpc/lib/copy_32.S | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S index da425bb6b369..ba66846fe973 100644 --- a/arch/powerpc/lib/copy_32.S +++ b/arch/powerpc/lib/copy_32.S | |||
| @@ -13,6 +13,7 @@ | |||
| 13 | #include <asm/errno.h> | 13 | #include <asm/errno.h> |
| 14 | #include <asm/ppc_asm.h> | 14 | #include <asm/ppc_asm.h> |
| 15 | #include <asm/export.h> | 15 | #include <asm/export.h> |
| 16 | #include <asm/code-patching-asm.h> | ||
| 16 | 17 | ||
| 17 | #define COPY_16_BYTES \ | 18 | #define COPY_16_BYTES \ |
| 18 | lwz r7,4(r4); \ | 19 | lwz r7,4(r4); \ |
| @@ -107,8 +108,8 @@ _GLOBAL(memset) | |||
| 107 | * Skip optimised bloc until cache is enabled. Will be replaced | 108 | * Skip optimised bloc until cache is enabled. Will be replaced |
| 108 | * by 'bne' during boot to use normal procedure if r4 is not zero | 109 | * by 'bne' during boot to use normal procedure if r4 is not zero |
| 109 | */ | 110 | */ |
| 110 | _GLOBAL(memset_nocache_branch) | 111 | 5: b 2f |
| 111 | b 2f | 112 | patch_site 5b, patch__memset_nocache |
| 112 | 113 | ||
| 113 | clrlwi r7,r6,32-LG_CACHELINE_BYTES | 114 | clrlwi r7,r6,32-LG_CACHELINE_BYTES |
| 114 | add r8,r7,r5 | 115 | add r8,r7,r5 |
| @@ -168,7 +169,9 @@ _GLOBAL(memmove) | |||
| 168 | /* fall through */ | 169 | /* fall through */ |
| 169 | 170 | ||
| 170 | _GLOBAL(memcpy) | 171 | _GLOBAL(memcpy) |
| 171 | b generic_memcpy | 172 | 1: b generic_memcpy |
| 173 | patch_site 1b, patch__memcpy_nocache | ||
| 174 | |||
| 172 | add r7,r3,r5 /* test if the src & dst overlap */ | 175 | add r7,r3,r5 /* test if the src & dst overlap */ |
| 173 | add r8,r4,r5 | 176 | add r8,r4,r5 |
| 174 | cmplw 0,r4,r7 | 177 | cmplw 0,r4,r7 |
