ARM: imx: support arm power off in cpuidle for i.mx6sx

This patch introduces an independent cpuidle driver for
i.MX6SX, and supports arm power off in idle, totally
3 levels of cpuidle are supported as below:

1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.

ARM power off can save at least 5mW power.

This patch also replaces imx6q_enable_rbc with imx6_enable_rbc.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

1 files changed, 23 insertions, 2 deletions

diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 5f3602ec74fa..745caa18ab2c 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -20,6 +20,10 @@
 
 #define GPC_IMR1                0x008
 #define GPC_PGC_CPU_PDN         0x2a0
+#define GPC_PGC_CPU_PUPSCR      0x2a4
+#define GPC_PGC_CPU_PDNSCR      0x2a8
+#define GPC_PGC_SW2ISO_SHIFT    0x8
+#define GPC_PGC_SW_SHIFT        0x0
 
 #define IMR_NUM                 4
 
@@ -27,6 +31,23 @@ static void __iomem *gpc_base;
 static u32 gpc_wake_irqs[IMR_NUM];
 static u32 gpc_saved_imrs[IMR_NUM];
 
+void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw)
+{
+        writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
+                (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PUPSCR);
+}
+
+void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw)
+{
+        writel_relaxed((sw2iso << GPC_PGC_SW2ISO_SHIFT) |
+                (sw << GPC_PGC_SW_SHIFT), gpc_base + GPC_PGC_CPU_PDNSCR);
+}
+
+void imx_gpc_set_arm_power_in_lpm(bool power_off)
+{
+        writel_relaxed(power_off, gpc_base + GPC_PGC_CPU_PDN);
+}
+
 void imx_gpc_pre_suspend(bool arm_power_off)
 {
         void __iomem *reg_imr1 = gpc_base + GPC_IMR1;
@@ -34,7 +55,7 @@ void imx_gpc_pre_suspend(bool arm_power_off)
 
         /* Tell GPC to power off ARM core when suspend */
         if (arm_power_off)
-                writel_relaxed(0x1, gpc_base + GPC_PGC_CPU_PDN);
+                imx_gpc_set_arm_power_in_lpm(arm_power_off);
 
         for (i = 0; i < IMR_NUM; i++) {
                 gpc_saved_imrs[i] = readl_relaxed(reg_imr1 + i * 4);
@@ -48,7 +69,7 @@ void imx_gpc_post_resume(void)
         int i;
 
         /* Keep ARM core powered on for other low-power modes */
-        writel_relaxed(0x0, gpc_base + GPC_PGC_CPU_PDN);
+        imx_gpc_set_arm_power_in_lpm(false);
 
         for (i = 0; i < IMR_NUM; i++)
                 writel_relaxed(gpc_saved_imrs[i], reg_imr1 + i * 4);