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authorVineet Gupta <vgupta@synopsys.com>2013-05-13 09:00:41 -0400
committerVineet Gupta <vgupta@synopsys.com>2015-06-22 04:36:55 -0400
commit1f6ccfff6314672743ad7252160654709e997a2a (patch)
treef2027c01b8d010b9d1aaa3685c7c4d0644271f53 /arch/arc/kernel/head.S
parent820970a5aa3c98be26e1df64da4b93294d20d4e7 (diff)
ARCv2: Support for ARCv2 ISA and HS38x cores
The notable features are: - SMP configurations of upto 4 cores with coherency - Optional L2 Cache and IO-Coherency - Revised Interrupt Architecture (multiple priorites, reg banks, auto stack switch, auto regfile save/restore) - MMUv4 (PIPT dcache, Huge Pages) - Instructions for * 64bit load/store: LDD, STD * Hardware assisted divide/remainder: DIV, REM * Function prologue/epilogue: ENTER_S, LEAVE_S * IRQ enable/disable: CLRI, SETI * pop count: FFS, FLS * SETcc, BMSKN, XBFU... Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Diffstat (limited to 'arch/arc/kernel/head.S')
-rw-r--r--arch/arc/kernel/head.S2
1 files changed, 0 insertions, 2 deletions
diff --git a/arch/arc/kernel/head.S b/arch/arc/kernel/head.S
index 64a92e0b1e53..812f95e6ae69 100644
--- a/arch/arc/kernel/head.S
+++ b/arch/arc/kernel/head.S
@@ -49,8 +49,6 @@
491: 491:
50.endm 50.endm
51 51
52 .cpu A7
53
54 .section .init.text, "ax",@progbits 52 .section .init.text, "ax",@progbits
55 .type stext, @function 53 .type stext, @function
56 .globl stext 54 .globl stext