aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorBen Goz <ben.goz@amd.com>2014-10-07 07:43:07 -0400
committerOded Gabbay <oded.gabbay@gmail.com>2015-07-20 02:16:48 -0400
commitff758a12b45b0513dbe9905deba2a29b20412138 (patch)
tree9814e56e5d7223141310e3c06e250714f3580ddf
parent32c22e994f44e7e5cc54b52375012311d1693b0d (diff)
drm/amdgpu: Add amdgpu <--> amdkfd gfx8 interface
This patch adds the gfx8 interface file between amdgpu and amdkfd. This interface file is currently in use when running on a Carrizo-based system. The interface itself is represented by a pointer to struct kfd_dev. The pointer is located inside amdgpu_device structure. All the register accesses that amdkfd need are done using this interface. This allows us to avoid direct register accesses in amdkfd proper, while also allows us to avoid locking between amdkfd and amdgpu. The single exception is the doorbells that are used in both of the drivers. However, because they are located in separate pci bar pages, the danger of sharing registers between the drivers is minimal. Having said that, we are planning to move the doorbells as well to amdgpu. Signed-off-by: Ben Goz <ben.goz@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
Diffstat
-rw-r--r--MAINTAINERS2
-rw-r--r--drivers/gpu/drm/amd/amdgpu/Makefile3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c3
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h1
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c543
-rw-r--r--drivers/gpu/drm/amd/amdgpu/vid.h5
-rw-r--r--drivers/gpu/drm/amd/include/vi_structs.h417
7 files changed, 973 insertions, 1 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 5cc07349b523..9c9dd5fc7aff 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -639,9 +639,11 @@ S: Supported
639F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c 639F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
640F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h 640F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
641F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c 641F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c
642F: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
642F: drivers/gpu/drm/amd/amdkfd/ 643F: drivers/gpu/drm/amd/amdkfd/
643F: drivers/gpu/drm/amd/include/cik_structs.h 644F: drivers/gpu/drm/amd/include/cik_structs.h
644F: drivers/gpu/drm/amd/include/kgd_kfd_interface.h 645F: drivers/gpu/drm/amd/include/kgd_kfd_interface.h
646F: drivers/gpu/drm/amd/include/vi_structs.h
645F: drivers/gpu/drm/radeon/radeon_kfd.c 647F: drivers/gpu/drm/radeon/radeon_kfd.c
646F: drivers/gpu/drm/radeon/radeon_kfd.h 648F: drivers/gpu/drm/radeon/radeon_kfd.h
647F: include/uapi/linux/kfd_ioctl.h 649F: include/uapi/linux/kfd_ioctl.h
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index af5397c40ea3..908360584e4d 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -74,7 +74,8 @@ amdgpu-y += \
74# add amdkfd interfaces 74# add amdkfd interfaces
75amdgpu-y += \ 75amdgpu-y += \
76 amdgpu_amdkfd.o \ 76 amdgpu_amdkfd.o \
77 amdgpu_amdkfd_gfx_v7.o 77 amdgpu_amdkfd_gfx_v7.o \
78 amdgpu_amdkfd_gfx_v8.o
78 79
79amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o 80amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o
80amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o 81amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
index 7aa5ab09ed09..bc763e0c8f4c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c
@@ -53,6 +53,9 @@ bool amdgpu_amdkfd_load_interface(struct amdgpu_device *rdev)
53 case CHIP_KAVERI: 53 case CHIP_KAVERI:
54 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions(); 54 kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
55 break; 55 break;
56 case CHIP_CARRIZO:
57 kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
58 break;
56 default: 59 default:
57 return false; 60 return false;
58 } 61 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
index c81242e84aba..a8be765542e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h
@@ -50,6 +50,7 @@ void amdgpu_amdkfd_device_init(struct amdgpu_device *rdev);
50void amdgpu_amdkfd_device_fini(struct amdgpu_device *rdev); 50void amdgpu_amdkfd_device_fini(struct amdgpu_device *rdev);
51 51
52struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void); 52struct kfd2kgd_calls *amdgpu_amdkfd_gfx_7_get_functions(void);
53struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions(void);
53 54
54/* Shared API */ 55/* Shared API */
55int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, 56int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
new file mode 100644
index 000000000000..dfd1d503bccf
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c
@@ -0,0 +1,543 @@
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23#include <linux/module.h>
24#include <linux/fdtable.h>
25#include <linux/uaccess.h>
26#include <linux/firmware.h>
27#include <drm/drmP.h>
28#include "amdgpu.h"
29#include "amdgpu_amdkfd.h"
30#include "amdgpu_ucode.h"
31#include "gca/gfx_8_0_sh_mask.h"
32#include "gca/gfx_8_0_d.h"
33#include "gca/gfx_8_0_enum.h"
34#include "oss/oss_3_0_sh_mask.h"
35#include "oss/oss_3_0_d.h"
36#include "gmc/gmc_8_1_sh_mask.h"
37#include "gmc/gmc_8_1_d.h"
38#include "vi_structs.h"
39#include "vid.h"
40
41#define VI_PIPE_PER_MEC (4)
42
43struct cik_sdma_rlc_registers;
44
45/*
46 * Register access functions
47 */
48
49static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
50 uint32_t sh_mem_config,
51 uint32_t sh_mem_ape1_base, uint32_t sh_mem_ape1_limit,
52 uint32_t sh_mem_bases);
53static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
54 unsigned int vmid);
55static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
56 uint32_t hpd_size, uint64_t hpd_gpu_addr);
57static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id);
58static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
59 uint32_t queue_id, uint32_t __user *wptr);
60static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd);
61static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
62 uint32_t pipe_id, uint32_t queue_id);
63static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd);
64static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
65 unsigned int timeout, uint32_t pipe_id,
66 uint32_t queue_id);
67static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
68 unsigned int timeout);
69static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
70static int kgd_address_watch_disable(struct kgd_dev *kgd);
71static int kgd_address_watch_execute(struct kgd_dev *kgd,
72 unsigned int watch_point_id,
73 uint32_t cntl_val,
74 uint32_t addr_hi,
75 uint32_t addr_lo);
76static int kgd_wave_control_execute(struct kgd_dev *kgd,
77 uint32_t gfx_index_val,
78 uint32_t sq_cmd);
79static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
80 unsigned int watch_point_id,
81 unsigned int reg_offset);
82
83static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
84 uint8_t vmid);
85static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
86 uint8_t vmid);
87static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid);
88static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type);
89
90static const struct kfd2kgd_calls kfd2kgd = {
91 .init_gtt_mem_allocation = alloc_gtt_mem,
92 .free_gtt_mem = free_gtt_mem,
93 .get_vmem_size = get_vmem_size,
94 .get_gpu_clock_counter = get_gpu_clock_counter,
95 .get_max_engine_clock_in_mhz = get_max_engine_clock_in_mhz,
96 .program_sh_mem_settings = kgd_program_sh_mem_settings,
97 .set_pasid_vmid_mapping = kgd_set_pasid_vmid_mapping,
98 .init_pipeline = kgd_init_pipeline,
99 .init_interrupts = kgd_init_interrupts,
100 .hqd_load = kgd_hqd_load,
101 .hqd_sdma_load = kgd_hqd_sdma_load,
102 .hqd_is_occupied = kgd_hqd_is_occupied,
103 .hqd_sdma_is_occupied = kgd_hqd_sdma_is_occupied,
104 .hqd_destroy = kgd_hqd_destroy,
105 .hqd_sdma_destroy = kgd_hqd_sdma_destroy,
106 .address_watch_disable = kgd_address_watch_disable,
107 .address_watch_execute = kgd_address_watch_execute,
108 .wave_control_execute = kgd_wave_control_execute,
109 .address_watch_get_offset = kgd_address_watch_get_offset,
110 .get_atc_vmid_pasid_mapping_pasid =
111 get_atc_vmid_pasid_mapping_pasid,
112 .get_atc_vmid_pasid_mapping_valid =
113 get_atc_vmid_pasid_mapping_valid,
114 .write_vmid_invalidate_request = write_vmid_invalidate_request,
115 .get_fw_version = get_fw_version
116};
117
118struct kfd2kgd_calls *amdgpu_amdkfd_gfx_8_0_get_functions()
119{
120 return (struct kfd2kgd_calls *)&kfd2kgd;
121}
122
123static inline struct amdgpu_device *get_amdgpu_device(struct kgd_dev *kgd)
124{
125 return (struct amdgpu_device *)kgd;
126}
127
128static void lock_srbm(struct kgd_dev *kgd, uint32_t mec, uint32_t pipe,
129 uint32_t queue, uint32_t vmid)
130{
131 struct amdgpu_device *adev = get_amdgpu_device(kgd);
132 uint32_t value = PIPEID(pipe) | MEID(mec) | VMID(vmid) | QUEUEID(queue);
133
134 mutex_lock(&adev->srbm_mutex);
135 WREG32(mmSRBM_GFX_CNTL, value);
136}
137
138static void unlock_srbm(struct kgd_dev *kgd)
139{
140 struct amdgpu_device *adev = get_amdgpu_device(kgd);
141
142 WREG32(mmSRBM_GFX_CNTL, 0);
143 mutex_unlock(&adev->srbm_mutex);
144}
145
146static void acquire_queue(struct kgd_dev *kgd, uint32_t pipe_id,
147 uint32_t queue_id)
148{
149 uint32_t mec = (++pipe_id / VI_PIPE_PER_MEC) + 1;
150 uint32_t pipe = (pipe_id % VI_PIPE_PER_MEC);
151
152 lock_srbm(kgd, mec, pipe, queue_id, 0);
153}
154
155static void release_queue(struct kgd_dev *kgd)
156{
157 unlock_srbm(kgd);
158}
159
160static void kgd_program_sh_mem_settings(struct kgd_dev *kgd, uint32_t vmid,
161 uint32_t sh_mem_config,
162 uint32_t sh_mem_ape1_base,
163 uint32_t sh_mem_ape1_limit,
164 uint32_t sh_mem_bases)
165{
166 struct amdgpu_device *adev = get_amdgpu_device(kgd);
167
168 lock_srbm(kgd, 0, 0, 0, vmid);
169
170 WREG32(mmSH_MEM_CONFIG, sh_mem_config);
171 WREG32(mmSH_MEM_APE1_BASE, sh_mem_ape1_base);
172 WREG32(mmSH_MEM_APE1_LIMIT, sh_mem_ape1_limit);
173 WREG32(mmSH_MEM_BASES, sh_mem_bases);
174
175 unlock_srbm(kgd);
176}
177
178static int kgd_set_pasid_vmid_mapping(struct kgd_dev *kgd, unsigned int pasid,
179 unsigned int vmid)
180{
181 struct amdgpu_device *adev = get_amdgpu_device(kgd);
182
183 /*
184 * We have to assume that there is no outstanding mapping.
185 * The ATC_VMID_PASID_MAPPING_UPDATE_STATUS bit could be 0 because
186 * a mapping is in progress or because a mapping finished
187 * and the SW cleared it.
188 * So the protocol is to always wait & clear.
189 */
190 uint32_t pasid_mapping = (pasid == 0) ? 0 : (uint32_t)pasid |
191 ATC_VMID0_PASID_MAPPING__VALID_MASK;
192
193 WREG32(mmATC_VMID0_PASID_MAPPING + vmid, pasid_mapping);
194
195 while (!(RREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS) & (1U << vmid)))
196 cpu_relax();
197 WREG32(mmATC_VMID_PASID_MAPPING_UPDATE_STATUS, 1U << vmid);
198
199 /* Mapping vmid to pasid also for IH block */
200 WREG32(mmIH_VMID_0_LUT + vmid, pasid_mapping);
201
202 return 0;
203}
204
205static int kgd_init_pipeline(struct kgd_dev *kgd, uint32_t pipe_id,
206 uint32_t hpd_size, uint64_t hpd_gpu_addr)
207{
208 return 0;
209}
210
211static int kgd_init_interrupts(struct kgd_dev *kgd, uint32_t pipe_id)
212{
213 struct amdgpu_device *adev = get_amdgpu_device(kgd);
214 uint32_t mec;
215 uint32_t pipe;
216
217 mec = (++pipe_id / VI_PIPE_PER_MEC) + 1;
218 pipe = (pipe_id % VI_PIPE_PER_MEC);
219
220 lock_srbm(kgd, mec, pipe, 0, 0);
221
222 WREG32(mmCPC_INT_CNTL, CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK);
223
224 unlock_srbm(kgd);
225
226 return 0;
227}
228
229static inline uint32_t get_sdma_base_addr(struct cik_sdma_rlc_registers *m)
230{
231 return 0;
232}
233
234static inline struct vi_mqd *get_mqd(void *mqd)
235{
236 return (struct vi_mqd *)mqd;
237}
238
239static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd)
240{
241 return (struct cik_sdma_rlc_registers *)mqd;
242}
243
244static int kgd_hqd_load(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
245 uint32_t queue_id, uint32_t __user *wptr)
246{
247 struct vi_mqd *m;
248 uint32_t shadow_wptr, valid_wptr;
249 struct amdgpu_device *adev = get_amdgpu_device(kgd);
250
251 m = get_mqd(mqd);
252
253 valid_wptr = copy_from_user(&shadow_wptr, wptr, sizeof(shadow_wptr));
254 acquire_queue(kgd, pipe_id, queue_id);
255
256 WREG32(mmCP_MQD_CONTROL, m->cp_mqd_control);
257 WREG32(mmCP_MQD_BASE_ADDR, m->cp_mqd_base_addr_lo);
258 WREG32(mmCP_MQD_BASE_ADDR_HI, m->cp_mqd_base_addr_hi);
259
260 WREG32(mmCP_HQD_VMID, m->cp_hqd_vmid);
261 WREG32(mmCP_HQD_PERSISTENT_STATE, m->cp_hqd_persistent_state);
262 WREG32(mmCP_HQD_PIPE_PRIORITY, m->cp_hqd_pipe_priority);
263 WREG32(mmCP_HQD_QUEUE_PRIORITY, m->cp_hqd_queue_priority);
264 WREG32(mmCP_HQD_QUANTUM, m->cp_hqd_quantum);
265 WREG32(mmCP_HQD_PQ_BASE, m->cp_hqd_pq_base_lo);
266 WREG32(mmCP_HQD_PQ_BASE_HI, m->cp_hqd_pq_base_hi);
267 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR, m->cp_hqd_pq_rptr_report_addr_lo);
268 WREG32(mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
269 m->cp_hqd_pq_rptr_report_addr_hi);
270
271 if (valid_wptr > 0)
272 WREG32(mmCP_HQD_PQ_WPTR, shadow_wptr);
273
274 WREG32(mmCP_HQD_PQ_CONTROL, m->cp_hqd_pq_control);
275 WREG32(mmCP_HQD_PQ_DOORBELL_CONTROL, m->cp_hqd_pq_doorbell_control);
276
277 WREG32(mmCP_HQD_EOP_BASE_ADDR, m->cp_hqd_eop_base_addr_lo);
278 WREG32(mmCP_HQD_EOP_BASE_ADDR_HI, m->cp_hqd_eop_base_addr_hi);
279 WREG32(mmCP_HQD_EOP_CONTROL, m->cp_hqd_eop_control);
280 WREG32(mmCP_HQD_EOP_RPTR, m->cp_hqd_eop_rptr);
281 WREG32(mmCP_HQD_EOP_WPTR, m->cp_hqd_eop_wptr);
282 WREG32(mmCP_HQD_EOP_EVENTS, m->cp_hqd_eop_done_events);
283
284 WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_LO, m->cp_hqd_ctx_save_base_addr_lo);
285 WREG32(mmCP_HQD_CTX_SAVE_BASE_ADDR_HI, m->cp_hqd_ctx_save_base_addr_hi);
286 WREG32(mmCP_HQD_CTX_SAVE_CONTROL, m->cp_hqd_ctx_save_control);
287 WREG32(mmCP_HQD_CNTL_STACK_OFFSET, m->cp_hqd_cntl_stack_offset);
288 WREG32(mmCP_HQD_CNTL_STACK_SIZE, m->cp_hqd_cntl_stack_size);
289 WREG32(mmCP_HQD_WG_STATE_OFFSET, m->cp_hqd_wg_state_offset);
290 WREG32(mmCP_HQD_CTX_SAVE_SIZE, m->cp_hqd_ctx_save_size);
291
292 WREG32(mmCP_HQD_IB_CONTROL, m->cp_hqd_ib_control);
293
294 WREG32(mmCP_HQD_DEQUEUE_REQUEST, m->cp_hqd_dequeue_request);
295 WREG32(mmCP_HQD_ERROR, m->cp_hqd_error);
296 WREG32(mmCP_HQD_EOP_WPTR_MEM, m->cp_hqd_eop_wptr_mem);
297 WREG32(mmCP_HQD_EOP_DONES, m->cp_hqd_eop_dones);
298
299 WREG32(mmCP_HQD_ACTIVE, m->cp_hqd_active);
300
301 release_queue(kgd);
302
303 return 0;
304}
305
306static int kgd_hqd_sdma_load(struct kgd_dev *kgd, void *mqd)
307{
308 return 0;
309}
310
311static bool kgd_hqd_is_occupied(struct kgd_dev *kgd, uint64_t queue_address,
312 uint32_t pipe_id, uint32_t queue_id)
313{
314 struct amdgpu_device *adev = get_amdgpu_device(kgd);
315 uint32_t act;
316 bool retval = false;
317 uint32_t low, high;
318
319 acquire_queue(kgd, pipe_id, queue_id);
320 act = RREG32(mmCP_HQD_ACTIVE);
321 if (act) {
322 low = lower_32_bits(queue_address >> 8);
323 high = upper_32_bits(queue_address >> 8);
324
325 if (low == RREG32(mmCP_HQD_PQ_BASE) &&
326 high == RREG32(mmCP_HQD_PQ_BASE_HI))
327 retval = true;
328 }
329 release_queue(kgd);
330 return retval;
331}
332
333static bool kgd_hqd_sdma_is_occupied(struct kgd_dev *kgd, void *mqd)
334{
335 struct amdgpu_device *adev = get_amdgpu_device(kgd);
336 struct cik_sdma_rlc_registers *m;
337 uint32_t sdma_base_addr;
338 uint32_t sdma_rlc_rb_cntl;
339
340 m = get_sdma_mqd(mqd);
341 sdma_base_addr = get_sdma_base_addr(m);
342
343 sdma_rlc_rb_cntl = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
344
345 if (sdma_rlc_rb_cntl & SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK)
346 return true;
347
348 return false;
349}
350
351static int kgd_hqd_destroy(struct kgd_dev *kgd, uint32_t reset_type,
352 unsigned int timeout, uint32_t pipe_id,
353 uint32_t queue_id)
354{
355 struct amdgpu_device *adev = get_amdgpu_device(kgd);
356 uint32_t temp;
357
358 acquire_queue(kgd, pipe_id, queue_id);
359
360 WREG32(mmCP_HQD_DEQUEUE_REQUEST, reset_type);
361
362 while (true) {
363 temp = RREG32(mmCP_HQD_ACTIVE);
364 if (temp & CP_HQD_ACTIVE__ACTIVE_MASK)
365 break;
366 if (timeout == 0) {
367 pr_err("kfd: cp queue preemption time out (%dms)\n",
368 temp);
369 release_queue(kgd);
370 return -ETIME;
371 }
372 msleep(20);
373 timeout -= 20;
374 }
375
376 release_queue(kgd);
377 return 0;
378}
379
380static int kgd_hqd_sdma_destroy(struct kgd_dev *kgd, void *mqd,
381 unsigned int timeout)
382{
383 struct amdgpu_device *adev = get_amdgpu_device(kgd);
384 struct cik_sdma_rlc_registers *m;
385 uint32_t sdma_base_addr;
386 uint32_t temp;
387
388 m = get_sdma_mqd(mqd);
389 sdma_base_addr = get_sdma_base_addr(m);
390
391 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL);
392 temp = temp & ~SDMA0_RLC0_RB_CNTL__RB_ENABLE_MASK;
393 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_CNTL, temp);
394
395 while (true) {
396 temp = RREG32(sdma_base_addr + mmSDMA0_RLC0_CONTEXT_STATUS);
397 if (temp & SDMA0_STATUS_REG__RB_CMD_IDLE__SHIFT)
398 break;
399 if (timeout == 0)
400 return -ETIME;
401 msleep(20);
402 timeout -= 20;
403 }
404
405 WREG32(sdma_base_addr + mmSDMA0_RLC0_DOORBELL, 0);
406 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_RPTR, 0);
407 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_WPTR, 0);
408 WREG32(sdma_base_addr + mmSDMA0_RLC0_RB_BASE, 0);
409
410 return 0;
411}
412
413static bool get_atc_vmid_pasid_mapping_valid(struct kgd_dev *kgd,
414 uint8_t vmid)
415{
416 uint32_t reg;
417 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
418
419 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
420 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
421}
422
423static uint16_t get_atc_vmid_pasid_mapping_pasid(struct kgd_dev *kgd,
424 uint8_t vmid)
425{
426 uint32_t reg;
427 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
428
429 reg = RREG32(mmATC_VMID0_PASID_MAPPING + vmid);
430 return reg & ATC_VMID0_PASID_MAPPING__VALID_MASK;
431}
432
433static void write_vmid_invalidate_request(struct kgd_dev *kgd, uint8_t vmid)
434{
435 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
436
437 WREG32(mmVM_INVALIDATE_REQUEST, 1 << vmid);
438}
439
440static int kgd_address_watch_disable(struct kgd_dev *kgd)
441{
442 return 0;
443}
444
445static int kgd_address_watch_execute(struct kgd_dev *kgd,
446 unsigned int watch_point_id,
447 uint32_t cntl_val,
448 uint32_t addr_hi,
449 uint32_t addr_lo)
450{
451 return 0;
452}
453
454static int kgd_wave_control_execute(struct kgd_dev *kgd,
455 uint32_t gfx_index_val,
456 uint32_t sq_cmd)
457{
458 struct amdgpu_device *adev = get_amdgpu_device(kgd);
459 uint32_t data = 0;
460
461 mutex_lock(&adev->grbm_idx_mutex);
462
463 WREG32(mmGRBM_GFX_INDEX, gfx_index_val);
464 WREG32(mmSQ_CMD, sq_cmd);
465
466 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
467 INSTANCE_BROADCAST_WRITES, 1);
468 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
469 SH_BROADCAST_WRITES, 1);
470 data = REG_SET_FIELD(data, GRBM_GFX_INDEX,
471 SE_BROADCAST_WRITES, 1);
472
473 WREG32(mmGRBM_GFX_INDEX, data);
474 mutex_unlock(&adev->grbm_idx_mutex);
475
476 return 0;
477}
478
479static uint32_t kgd_address_watch_get_offset(struct kgd_dev *kgd,
480 unsigned int watch_point_id,
481 unsigned int reg_offset)
482{
483 return 0;
484}
485
486static uint16_t get_fw_version(struct kgd_dev *kgd, enum kgd_engine_type type)
487{
488 struct amdgpu_device *adev = (struct amdgpu_device *) kgd;
489 const union amdgpu_firmware_header *hdr;
490
491 BUG_ON(kgd == NULL);
492
493 switch (type) {
494 case KGD_ENGINE_PFP:
495 hdr = (const union amdgpu_firmware_header *)
496 adev->gfx.pfp_fw->data;
497 break;
498
499 case KGD_ENGINE_ME:
500 hdr = (const union amdgpu_firmware_header *)
501 adev->gfx.me_fw->data;
502 break;
503
504 case KGD_ENGINE_CE:
505 hdr = (const union amdgpu_firmware_header *)
506 adev->gfx.ce_fw->data;
507 break;
508
509 case KGD_ENGINE_MEC1:
510 hdr = (const union amdgpu_firmware_header *)
511 adev->gfx.mec_fw->data;
512 break;
513
514 case KGD_ENGINE_MEC2:
515 hdr = (const union amdgpu_firmware_header *)
516 adev->gfx.mec2_fw->data;
517 break;
518
519 case KGD_ENGINE_RLC:
520 hdr = (const union amdgpu_firmware_header *)
521 adev->gfx.rlc_fw->data;
522 break;
523
524 case KGD_ENGINE_SDMA1:
525 hdr = (const union amdgpu_firmware_header *)
526 adev->sdma[0].fw->data;
527 break;
528
529 case KGD_ENGINE_SDMA2:
530 hdr = (const union amdgpu_firmware_header *)
531 adev->sdma[1].fw->data;
532 break;
533
534 default:
535 return 0;
536 }
537
538 if (hdr == NULL)
539 return 0;
540
541 /* Only 12 bit in use*/
542 return hdr->common.ucode_version;
543}
diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h
index 31bb89452e12..d98aa9d82fa1 100644
--- a/drivers/gpu/drm/amd/amdgpu/vid.h
+++ b/drivers/gpu/drm/amd/amdgpu/vid.h
@@ -66,6 +66,11 @@
66 66
67#define AMDGPU_NUM_OF_VMIDS 8 67#define AMDGPU_NUM_OF_VMIDS 8
68 68
69#define PIPEID(x) ((x) << 0)
70#define MEID(x) ((x) << 2)
71#define VMID(x) ((x) << 4)
72#define QUEUEID(x) ((x) << 8)
73
69#define RB_BITMAP_WIDTH_PER_SH 2 74#define RB_BITMAP_WIDTH_PER_SH 2
70 75
71#define MC_SEQ_MISC0__MT__MASK 0xf0000000 76#define MC_SEQ_MISC0__MT__MASK 0xf0000000
diff --git a/drivers/gpu/drm/amd/include/vi_structs.h b/drivers/gpu/drm/amd/include/vi_structs.h
new file mode 100644
index 000000000000..65cfacd7a66c
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/vi_structs.h
@@ -0,0 +1,417 @@
1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef VI_STRUCTS_H_
25#define VI_STRUCTS_H_
26
27struct vi_sdma_mqd {
28 uint32_t sdmax_rlcx_rb_cntl;
29 uint32_t sdmax_rlcx_rb_base;
30 uint32_t sdmax_rlcx_rb_base_hi;
31 uint32_t sdmax_rlcx_rb_rptr;
32 uint32_t sdmax_rlcx_rb_wptr;
33 uint32_t sdmax_rlcx_rb_wptr_poll_cntl;
34 uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi;
35 uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo;
36 uint32_t sdmax_rlcx_rb_rptr_addr_hi;
37 uint32_t sdmax_rlcx_rb_rptr_addr_lo;
38 uint32_t sdmax_rlcx_ib_cntl;
39 uint32_t sdmax_rlcx_ib_rptr;
40 uint32_t sdmax_rlcx_ib_offset;
41 uint32_t sdmax_rlcx_ib_base_lo;
42 uint32_t sdmax_rlcx_ib_base_hi;
43 uint32_t sdmax_rlcx_ib_size;
44 uint32_t sdmax_rlcx_skip_cntl;
45 uint32_t sdmax_rlcx_context_status;
46 uint32_t sdmax_rlcx_doorbell;
47 uint32_t sdmax_rlcx_virtual_addr;
48 uint32_t sdmax_rlcx_ape1_cntl;
49 uint32_t sdmax_rlcx_doorbell_log;
50 uint32_t reserved_22;
51 uint32_t reserved_23;
52 uint32_t reserved_24;
53 uint32_t reserved_25;
54 uint32_t reserved_26;
55 uint32_t reserved_27;
56 uint32_t reserved_28;
57 uint32_t reserved_29;
58 uint32_t reserved_30;
59 uint32_t reserved_31;
60 uint32_t reserved_32;
61 uint32_t reserved_33;
62 uint32_t reserved_34;
63 uint32_t reserved_35;
64 uint32_t reserved_36;
65 uint32_t reserved_37;
66 uint32_t reserved_38;
67 uint32_t reserved_39;
68 uint32_t reserved_40;
69 uint32_t reserved_41;
70 uint32_t reserved_42;
71 uint32_t reserved_43;
72 uint32_t reserved_44;
73 uint32_t reserved_45;
74 uint32_t reserved_46;
75 uint32_t reserved_47;
76 uint32_t reserved_48;
77 uint32_t reserved_49;
78 uint32_t reserved_50;
79 uint32_t reserved_51;
80 uint32_t reserved_52;
81 uint32_t reserved_53;
82 uint32_t reserved_54;
83 uint32_t reserved_55;
84 uint32_t reserved_56;
85 uint32_t reserved_57;
86 uint32_t reserved_58;
87 uint32_t reserved_59;
88 uint32_t reserved_60;
89 uint32_t reserved_61;
90 uint32_t reserved_62;
91 uint32_t reserved_63;
92 uint32_t reserved_64;
93 uint32_t reserved_65;
94 uint32_t reserved_66;
95 uint32_t reserved_67;
96 uint32_t reserved_68;
97 uint32_t reserved_69;
98 uint32_t reserved_70;
99 uint32_t reserved_71;
100 uint32_t reserved_72;
101 uint32_t reserved_73;
102 uint32_t reserved_74;
103 uint32_t reserved_75;
104 uint32_t reserved_76;
105 uint32_t reserved_77;
106 uint32_t reserved_78;
107 uint32_t reserved_79;
108 uint32_t reserved_80;
109 uint32_t reserved_81;
110 uint32_t reserved_82;
111 uint32_t reserved_83;
112 uint32_t reserved_84;
113 uint32_t reserved_85;
114 uint32_t reserved_86;
115 uint32_t reserved_87;
116 uint32_t reserved_88;
117 uint32_t reserved_89;
118 uint32_t reserved_90;
119 uint32_t reserved_91;
120 uint32_t reserved_92;
121 uint32_t reserved_93;
122 uint32_t reserved_94;
123 uint32_t reserved_95;
124 uint32_t reserved_96;
125 uint32_t reserved_97;
126 uint32_t reserved_98;
127 uint32_t reserved_99;
128 uint32_t reserved_100;
129 uint32_t reserved_101;
130 uint32_t reserved_102;
131 uint32_t reserved_103;
132 uint32_t reserved_104;
133 uint32_t reserved_105;
134 uint32_t reserved_106;
135 uint32_t reserved_107;
136 uint32_t reserved_108;
137 uint32_t reserved_109;
138 uint32_t reserved_110;
139 uint32_t reserved_111;
140 uint32_t reserved_112;
141 uint32_t reserved_113;
142 uint32_t reserved_114;
143 uint32_t reserved_115;
144 uint32_t reserved_116;
145 uint32_t reserved_117;
146 uint32_t reserved_118;
147 uint32_t reserved_119;
148 uint32_t reserved_120;
149 uint32_t reserved_121;
150 uint32_t reserved_122;
151 uint32_t reserved_123;
152 uint32_t reserved_124;
153 uint32_t reserved_125;
154 uint32_t reserved_126;
155 uint32_t reserved_127;
156};
157
158struct vi_mqd {
159 uint32_t header;
160 uint32_t compute_dispatch_initiator;
161 uint32_t compute_dim_x;
162 uint32_t compute_dim_y;
163 uint32_t compute_dim_z;
164 uint32_t compute_start_x;
165 uint32_t compute_start_y;
166 uint32_t compute_start_z;
167 uint32_t compute_num_thread_x;
168 uint32_t compute_num_thread_y;
169 uint32_t compute_num_thread_z;
170 uint32_t compute_pipelinestat_enable;
171 uint32_t compute_perfcount_enable;
172 uint32_t compute_pgm_lo;
173 uint32_t compute_pgm_hi;
174 uint32_t compute_tba_lo;
175 uint32_t compute_tba_hi;
176 uint32_t compute_tma_lo;
177 uint32_t compute_tma_hi;
178 uint32_t compute_pgm_rsrc1;
179 uint32_t compute_pgm_rsrc2;
180 uint32_t compute_vmid;
181 uint32_t compute_resource_limits;
182 uint32_t compute_static_thread_mgmt_se0;
183 uint32_t compute_static_thread_mgmt_se1;
184 uint32_t compute_tmpring_size;
185 uint32_t compute_static_thread_mgmt_se2;
186 uint32_t compute_static_thread_mgmt_se3;
187 uint32_t compute_restart_x;
188 uint32_t compute_restart_y;
189 uint32_t compute_restart_z;
190 uint32_t compute_thread_trace_enable;
191 uint32_t compute_misc_reserved;
192 uint32_t compute_dispatch_id;
193 uint32_t compute_threadgroup_id;
194 uint32_t compute_relaunch;
195 uint32_t compute_wave_restore_addr_lo;
196 uint32_t compute_wave_restore_addr_hi;
197 uint32_t compute_wave_restore_control;
198 uint32_t reserved_39;
199 uint32_t reserved_40;
200 uint32_t reserved_41;
201 uint32_t reserved_42;
202 uint32_t reserved_43;
203 uint32_t reserved_44;
204 uint32_t reserved_45;
205 uint32_t reserved_46;
206 uint32_t reserved_47;
207 uint32_t reserved_48;
208 uint32_t reserved_49;
209 uint32_t reserved_50;
210 uint32_t reserved_51;
211 uint32_t reserved_52;
212 uint32_t reserved_53;
213 uint32_t reserved_54;
214 uint32_t reserved_55;
215 uint32_t reserved_56;
216 uint32_t reserved_57;
217 uint32_t reserved_58;
218 uint32_t reserved_59;
219 uint32_t reserved_60;
220 uint32_t reserved_61;
221 uint32_t reserved_62;
222 uint32_t reserved_63;
223 uint32_t reserved_64;
224 uint32_t compute_user_data_0;
225 uint32_t compute_user_data_1;
226 uint32_t compute_user_data_2;
227 uint32_t compute_user_data_3;
228 uint32_t compute_user_data_4;
229 uint32_t compute_user_data_5;
230 uint32_t compute_user_data_6;
231 uint32_t compute_user_data_7;
232 uint32_t compute_user_data_8;
233 uint32_t compute_user_data_9;
234 uint32_t compute_user_data_10;
235 uint32_t compute_user_data_11;
236 uint32_t compute_user_data_12;
237 uint32_t compute_user_data_13;
238 uint32_t compute_user_data_14;
239 uint32_t compute_user_data_15;
240 uint32_t cp_compute_csinvoc_count_lo;
241 uint32_t cp_compute_csinvoc_count_hi;
242 uint32_t reserved_83;
243 uint32_t reserved_84;
244 uint32_t reserved_85;
245 uint32_t cp_mqd_query_time_lo;
246 uint32_t cp_mqd_query_time_hi;
247 uint32_t cp_mqd_connect_start_time_lo;
248 uint32_t cp_mqd_connect_start_time_hi;
249 uint32_t cp_mqd_connect_end_time_lo;
250 uint32_t cp_mqd_connect_end_time_hi;
251 uint32_t cp_mqd_connect_end_wf_count;
252 uint32_t cp_mqd_connect_end_pq_rptr;
253 uint32_t cp_mqd_connect_end_pq_wptr;
254 uint32_t cp_mqd_connect_end_ib_rptr;
255 uint32_t reserved_96;
256 uint32_t reserved_97;
257 uint32_t cp_mqd_save_start_time_lo;
258 uint32_t cp_mqd_save_start_time_hi;
259 uint32_t cp_mqd_save_end_time_lo;
260 uint32_t cp_mqd_save_end_time_hi;
261 uint32_t cp_mqd_restore_start_time_lo;
262 uint32_t cp_mqd_restore_start_time_hi;
263 uint32_t cp_mqd_restore_end_time_lo;
264 uint32_t cp_mqd_restore_end_time_hi;
265 uint32_t reserved_106;
266 uint32_t reserved_107;
267 uint32_t gds_cs_ctxsw_cnt0;
268 uint32_t gds_cs_ctxsw_cnt1;
269 uint32_t gds_cs_ctxsw_cnt2;
270 uint32_t gds_cs_ctxsw_cnt3;
271 uint32_t reserved_112;
272 uint32_t reserved_113;
273 uint32_t cp_pq_exe_status_lo;
274 uint32_t cp_pq_exe_status_hi;
275 uint32_t cp_packet_id_lo;
276 uint32_t cp_packet_id_hi;
277 uint32_t cp_packet_exe_status_lo;
278 uint32_t cp_packet_exe_status_hi;
279 uint32_t gds_save_base_addr_lo;
280 uint32_t gds_save_base_addr_hi;
281 uint32_t gds_save_mask_lo;
282 uint32_t gds_save_mask_hi;
283 uint32_t ctx_save_base_addr_lo;
284 uint32_t ctx_save_base_addr_hi;
285 uint32_t reserved_126;
286 uint32_t reserved_127;
287 uint32_t cp_mqd_base_addr_lo;
288 uint32_t cp_mqd_base_addr_hi;
289 uint32_t cp_hqd_active;
290 uint32_t cp_hqd_vmid;
291 uint32_t cp_hqd_persistent_state;
292 uint32_t cp_hqd_pipe_priority;
293 uint32_t cp_hqd_queue_priority;
294 uint32_t cp_hqd_quantum;
295 uint32_t cp_hqd_pq_base_lo;
296 uint32_t cp_hqd_pq_base_hi;
297 uint32_t cp_hqd_pq_rptr;
298 uint32_t cp_hqd_pq_rptr_report_addr_lo;
299 uint32_t cp_hqd_pq_rptr_report_addr_hi;
300 uint32_t cp_hqd_pq_wptr_poll_addr_lo;
301 uint32_t cp_hqd_pq_wptr_poll_addr_hi;
302 uint32_t cp_hqd_pq_doorbell_control;
303 uint32_t cp_hqd_pq_wptr;
304 uint32_t cp_hqd_pq_control;
305 uint32_t cp_hqd_ib_base_addr_lo;
306 uint32_t cp_hqd_ib_base_addr_hi;
307 uint32_t cp_hqd_ib_rptr;
308 uint32_t cp_hqd_ib_control;
309 uint32_t cp_hqd_iq_timer;
310 uint32_t cp_hqd_iq_rptr;
311 uint32_t cp_hqd_dequeue_request;
312 uint32_t cp_hqd_dma_offload;
313 uint32_t cp_hqd_sema_cmd;
314 uint32_t cp_hqd_msg_type;
315 uint32_t cp_hqd_atomic0_preop_lo;
316 uint32_t cp_hqd_atomic0_preop_hi;
317 uint32_t cp_hqd_atomic1_preop_lo;
318 uint32_t cp_hqd_atomic1_preop_hi;
319 uint32_t cp_hqd_hq_status0;
320 uint32_t cp_hqd_hq_control0;
321 uint32_t cp_mqd_control;
322 uint32_t cp_hqd_hq_status1;
323 uint32_t cp_hqd_hq_control1;
324 uint32_t cp_hqd_eop_base_addr_lo;
325 uint32_t cp_hqd_eop_base_addr_hi;
326 uint32_t cp_hqd_eop_control;
327 uint32_t cp_hqd_eop_rptr;
328 uint32_t cp_hqd_eop_wptr;
329 uint32_t cp_hqd_eop_done_events;
330 uint32_t cp_hqd_ctx_save_base_addr_lo;
331 uint32_t cp_hqd_ctx_save_base_addr_hi;
332 uint32_t cp_hqd_ctx_save_control;
333 uint32_t cp_hqd_cntl_stack_offset;
334 uint32_t cp_hqd_cntl_stack_size;
335 uint32_t cp_hqd_wg_state_offset;
336 uint32_t cp_hqd_ctx_save_size;
337 uint32_t cp_hqd_gds_resource_state;
338 uint32_t cp_hqd_error;
339 uint32_t cp_hqd_eop_wptr_mem;
340 uint32_t cp_hqd_eop_dones;
341 uint32_t reserved_182;
342 uint32_t reserved_183;
343 uint32_t reserved_184;
344 uint32_t reserved_185;
345 uint32_t reserved_186;
346 uint32_t reserved_187;
347 uint32_t reserved_188;
348 uint32_t reserved_189;
349 uint32_t reserved_190;
350 uint32_t reserved_191;
351 uint32_t iqtimer_pkt_header;
352 uint32_t iqtimer_pkt_dw0;
353 uint32_t iqtimer_pkt_dw1;
354 uint32_t iqtimer_pkt_dw2;
355 uint32_t iqtimer_pkt_dw3;
356 uint32_t iqtimer_pkt_dw4;
357 uint32_t iqtimer_pkt_dw5;
358 uint32_t iqtimer_pkt_dw6;
359 uint32_t iqtimer_pkt_dw7;
360 uint32_t iqtimer_pkt_dw8;
361 uint32_t iqtimer_pkt_dw9;
362 uint32_t iqtimer_pkt_dw10;
363 uint32_t iqtimer_pkt_dw11;
364 uint32_t iqtimer_pkt_dw12;
365 uint32_t iqtimer_pkt_dw13;
366 uint32_t iqtimer_pkt_dw14;
367 uint32_t iqtimer_pkt_dw15;
368 uint32_t iqtimer_pkt_dw16;
369 uint32_t iqtimer_pkt_dw17;
370 uint32_t iqtimer_pkt_dw18;
371 uint32_t iqtimer_pkt_dw19;
372 uint32_t iqtimer_pkt_dw20;
373 uint32_t iqtimer_pkt_dw21;
374 uint32_t iqtimer_pkt_dw22;
375 uint32_t iqtimer_pkt_dw23;
376 uint32_t iqtimer_pkt_dw24;
377 uint32_t iqtimer_pkt_dw25;
378 uint32_t iqtimer_pkt_dw26;
379 uint32_t iqtimer_pkt_dw27;
380 uint32_t iqtimer_pkt_dw28;
381 uint32_t iqtimer_pkt_dw29;
382 uint32_t iqtimer_pkt_dw30;
383 uint32_t iqtimer_pkt_dw31;
384 uint32_t reserved_225;
385 uint32_t reserved_226;
386 uint32_t reserved_227;
387 uint32_t set_resources_header;
388 uint32_t set_resources_dw1;
389 uint32_t set_resources_dw2;
390 uint32_t set_resources_dw3;
391 uint32_t set_resources_dw4;
392 uint32_t set_resources_dw5;
393 uint32_t set_resources_dw6;
394 uint32_t set_resources_dw7;
395 uint32_t reserved_236;
396 uint32_t reserved_237;
397 uint32_t reserved_238;
398 uint32_t reserved_239;
399 uint32_t queue_doorbell_id0;
400 uint32_t queue_doorbell_id1;
401 uint32_t queue_doorbell_id2;
402 uint32_t queue_doorbell_id3;
403 uint32_t queue_doorbell_id4;
404 uint32_t queue_doorbell_id5;
405 uint32_t queue_doorbell_id6;
406 uint32_t queue_doorbell_id7;
407 uint32_t queue_doorbell_id8;
408 uint32_t queue_doorbell_id9;
409 uint32_t queue_doorbell_id10;
410 uint32_t queue_doorbell_id11;
411 uint32_t queue_doorbell_id12;
412 uint32_t queue_doorbell_id13;
413 uint32_t queue_doorbell_id14;
414 uint32_t queue_doorbell_id15;
415};
416
417#endif /* VI_STRUCTS_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-11 18:30:29 -0400