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authorBen Widawsky <benjamin.widawsky@intel.com>2014-04-28 22:29:25 -0400
committerDaniel Vetter <daniel.vetter@ffwll.ch>2014-05-05 10:01:58 -0400
commit9bcb144c83d4df12c8150352fa876aeff289e39c (patch)
treeda8a9e0208c9b32704cad6eeb76e844cb8e24e01
parent192d47a64ea3f50387079e1f91276f9b683bee46 (diff)
drm/i915: Support 64b execbuf
Previously, our code only had a 32b offset value for where the batchbuffer starts. With full PPGTT, and 64b canonical GPU address space, that is an insufficient value. The code to expand is pretty straight forward, and only one platform needs to do anything with the extra bits. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c2
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c16
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.h2
3 files changed, 10 insertions, 10 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 6cc004f5d017..3c4e77024dcd 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1049,7 +1049,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1049 struct i915_hw_context *ctx; 1049 struct i915_hw_context *ctx;
1050 struct i915_address_space *vm; 1050 struct i915_address_space *vm;
1051 const u32 ctx_id = i915_execbuffer2_get_context_id(*args); 1051 const u32 ctx_id = i915_execbuffer2_get_context_id(*args);
1052 u32 exec_start = args->batch_start_offset, exec_len; 1052 u64 exec_start = args->batch_start_offset, exec_len;
1053 u32 mask, flags; 1053 u32 mask, flags;
1054 int ret, mode, i; 1054 int ret, mode, i;
1055 bool need_relocs; 1055 bool need_relocs;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e0c7bf27eafd..40a7aa4db589 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1210,7 +1210,7 @@ gen8_ring_put_irq(struct intel_ring_buffer *ring)
1210 1210
1211static int 1211static int
1212i965_dispatch_execbuffer(struct intel_ring_buffer *ring, 1212i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1213 u32 offset, u32 length, 1213 u64 offset, u32 length,
1214 unsigned flags) 1214 unsigned flags)
1215{ 1215{
1216 int ret; 1216 int ret;
@@ -1233,7 +1233,7 @@ i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1233#define I830_BATCH_LIMIT (256*1024) 1233#define I830_BATCH_LIMIT (256*1024)
1234static int 1234static int
1235i830_dispatch_execbuffer(struct intel_ring_buffer *ring, 1235i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1236 u32 offset, u32 len, 1236 u64 offset, u32 len,
1237 unsigned flags) 1237 unsigned flags)
1238{ 1238{
1239 int ret; 1239 int ret;
@@ -1284,7 +1284,7 @@ i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1284 1284
1285static int 1285static int
1286i915_dispatch_execbuffer(struct intel_ring_buffer *ring, 1286i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1287 u32 offset, u32 len, 1287 u64 offset, u32 len,
1288 unsigned flags) 1288 unsigned flags)
1289{ 1289{
1290 int ret; 1290 int ret;
@@ -1797,7 +1797,7 @@ static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1797 1797
1798static int 1798static int
1799gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 1799gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1800 u32 offset, u32 len, 1800 u64 offset, u32 len,
1801 unsigned flags) 1801 unsigned flags)
1802{ 1802{
1803 struct drm_i915_private *dev_priv = ring->dev->dev_private; 1803 struct drm_i915_private *dev_priv = ring->dev->dev_private;
@@ -1811,8 +1811,8 @@ gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1811 1811
1812 /* FIXME(BDW): Address space and security selectors. */ 1812 /* FIXME(BDW): Address space and security selectors. */
1813 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8)); 1813 intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | (ppgtt<<8));
1814 intel_ring_emit(ring, offset); 1814 intel_ring_emit(ring, lower_32_bits(offset));
1815 intel_ring_emit(ring, 0); 1815 intel_ring_emit(ring, upper_32_bits(offset));
1816 intel_ring_emit(ring, MI_NOOP); 1816 intel_ring_emit(ring, MI_NOOP);
1817 intel_ring_advance(ring); 1817 intel_ring_advance(ring);
1818 1818
@@ -1821,7 +1821,7 @@ gen8_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1821 1821
1822static int 1822static int
1823hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 1823hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1824 u32 offset, u32 len, 1824 u64 offset, u32 len,
1825 unsigned flags) 1825 unsigned flags)
1826{ 1826{
1827 int ret; 1827 int ret;
@@ -1842,7 +1842,7 @@ hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1842 1842
1843static int 1843static int
1844gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, 1844gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1845 u32 offset, u32 len, 1845 u64 offset, u32 len,
1846 unsigned flags) 1846 unsigned flags)
1847{ 1847{
1848 int ret; 1848 int ret;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 0fdf0300c2a3..72c3c15f6240 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -112,7 +112,7 @@ struct intel_ring_buffer {
112 void (*set_seqno)(struct intel_ring_buffer *ring, 112 void (*set_seqno)(struct intel_ring_buffer *ring,
113 u32 seqno); 113 u32 seqno);
114 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring, 114 int (*dispatch_execbuffer)(struct intel_ring_buffer *ring,
115 u32 offset, u32 length, 115 u64 offset, u32 length,
116 unsigned flags); 116 unsigned flags);
117#define I915_DISPATCH_SECURE 0x1 117#define I915_DISPATCH_SECURE 0x1
118#define I915_DISPATCH_PINNED 0x2 118#define I915_DISPATCH_PINNED 0x2