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authorSuganath Prabu <suganath-prabu.subramani@broadcom.com>2018-10-25 10:03:40 -0400
committerMartin K. Petersen <martin.petersen@oracle.com>2018-11-06 20:16:01 -0500
commitff92b9dd9268507e23fc10cc4341626cef50367c (patch)
tree94c07ec904164fc5b95c4000f464ac45aab60844
parent651022382c7f8da46cb4872a545ee1da6d097d2a (diff)
scsi: mpt3sas: Update MPI headers to support Aero controllers
Updating MPI headers to the latest version 2.6.7 to add support to the driver to detect the new 3816 and 3916 chip based controllers. Separate out firmware image data from mpi2_ioc.h to new file mpi2_image.h Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2.h17
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h94
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_image.h506
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_init.h2
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_ioc.h359
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_pci.h11
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_raid.h2
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_sas.h2
-rw-r--r--drivers/scsi/mpt3sas/mpi/mpi2_tool.h72
-rw-r--r--drivers/scsi/mpt3sas/mpt3sas_base.h1
10 files changed, 678 insertions, 388 deletions
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2.h b/drivers/scsi/mpt3sas/mpi/mpi2.h
index 1e45268a78fc..7efd17a3c25b 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2.h
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * 4 *
5 * 5 *
6 * Name: mpi2.h 6 * Name: mpi2.h
@@ -9,7 +9,7 @@
9 * scatter/gather formats. 9 * scatter/gather formats.
10 * Creation Date: June 21, 2006 10 * Creation Date: June 21, 2006
11 * 11 *
12 * mpi2.h Version: 02.00.50 12 * mpi2.h Version: 02.00.53
13 * 13 *
14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 14 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
15 * prefix are for use only on MPI v2.5 products, and must not be used 15 * prefix are for use only on MPI v2.5 products, and must not be used
@@ -116,7 +116,12 @@
116 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. 116 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT.
117 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. 117 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT.
118 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. 118 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT.
119 * -------------------------------------------------------------------------- 119 * 07-22-18 02.00.51 Added SECURE_BOOT define.
120 * Bumped MPI2_HEADER_VERSION_UNIT
121 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT.
122 * 08-28-18 02.00.53 Bumped MPI2_HEADER_VERSION_UNIT.
123 * Added MPI2_IOCSTATUS_FAILURE
124 * --------------------------------------------------------------------------
120 */ 125 */
121 126
122#ifndef MPI2_H 127#ifndef MPI2_H
@@ -156,7 +161,7 @@
156 161
157 162
158/* Unit and Dev versioning for this MPI header set */ 163/* Unit and Dev versioning for this MPI header set */
159#define MPI2_HEADER_VERSION_UNIT (0x32) 164#define MPI2_HEADER_VERSION_UNIT (0x35)
160#define MPI2_HEADER_VERSION_DEV (0x00) 165#define MPI2_HEADER_VERSION_DEV (0x00)
161#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 166#define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00)
162#define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 167#define MPI2_HEADER_VERSION_UNIT_SHIFT (8)
@@ -257,6 +262,8 @@ typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS {
257 */ 262 */
258#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 263#define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008)
259 264
265#define MPI26_DIAG_SECURE_BOOT (0x80000000)
266
260#define MPI2_DIAG_SBR_RELOAD (0x00002000) 267#define MPI2_DIAG_SBR_RELOAD (0x00002000)
261 268
262#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 269#define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800)
@@ -687,7 +694,9 @@ typedef union _MPI2_REPLY_DESCRIPTORS_UNION {
687#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 694#define MPI2_IOCSTATUS_INVALID_FIELD (0x0007)
688#define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 695#define MPI2_IOCSTATUS_INVALID_STATE (0x0008)
689#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 696#define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009)
697/*MPI v2.6 and later */
690#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 698#define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A)
699#define MPI2_IOCSTATUS_FAILURE (0x000F)
691 700
692/**************************************************************************** 701/****************************************************************************
693* Config IOCStatus values 702* Config IOCStatus values
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h b/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h
index 5122920a961a..398fa6fde960 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_cnfg.h
@@ -1,13 +1,13 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * 4 *
5 * 5 *
6 * Name: mpi2_cnfg.h 6 * Name: mpi2_cnfg.h
7 * Title: MPI Configuration messages and pages 7 * Title: MPI Configuration messages and pages
8 * Creation Date: November 10, 2006 8 * Creation Date: November 10, 2006
9 * 9 *
10 * mpi2_cnfg.h Version: 02.00.42 10 * mpi2_cnfg.h Version: 02.00.46
11 * 11 *
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used 13 * prefix are for use only on MPI v2.5 products, and must not be used
@@ -231,6 +231,18 @@
231 * Added NOIOB field to PCIe Device Page 2. 231 * Added NOIOB field to PCIe Device Page 2.
232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to 232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to
233 * the Capabilities field of PCIe Device Page 2. 233 * the Capabilities field of PCIe Device Page 2.
234 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816.
235 * Added WRiteCache defines to IO Unit Page 1.
236 * Added MaxEnclosureLevel to BIOS Page 1.
237 * Added OEMRD to SAS Enclosure Page 1.
238 * Added DMDReportPCIe to PCIe IO Unit Page 1.
239 * Added Flags field and flags for Retimers to
240 * PCIe Switch Page 1.
241 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7.
242 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1
243 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1
244 * Added DMDReport Delay Time defines to
245 * PCIeIOUnitPage1
234 * -------------------------------------------------------------------------- 246 * --------------------------------------------------------------------------
235 */ 247 */
236 248
@@ -568,8 +580,17 @@ typedef struct _MPI2_CONFIG_REPLY {
568#define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 580#define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1)
569#define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 581#define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2)
570 582
571#define MPI26_MFGPAGE_DEVID_SAS3816 (0x00A1) 583#define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 (0x0003)
572#define MPI26_MFGPAGE_DEVID_SAS3916 (0x00A0) 584#define MPI26_MFGPAGE_DEVID_INVALID0_3916 (0x00E0)
585#define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 (0x00E1)
586#define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 (0x00E2)
587#define MPI26_MFGPAGE_DEVID_INVALID1_3916 (0x00E3)
588
589#define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 (0x0003)
590#define MPI26_MFGPAGE_DEVID_INVALID0_3816 (0x00E4)
591#define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 (0x00E5)
592#define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 (0x00E6)
593#define MPI26_MFGPAGE_DEVID_INVALID1_3816 (0x00E7)
573 594
574 595
575/*Manufacturing Page 0 */ 596/*Manufacturing Page 0 */
@@ -932,7 +953,11 @@ typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 {
932 953
933#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 954#define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
934 955
935/*IO Unit Page 1 Flags defines */ 956/* IO Unit Page 1 Flags defines */
957#define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000)
958#define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00000000)
959#define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00010000)
960#define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00020000)
936#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 961#define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000)
937#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 962#define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000)
938#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 963#define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000)
@@ -1511,7 +1536,7 @@ typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1511 U32 BiosOptions; /*0x04 */ 1536 U32 BiosOptions; /*0x04 */
1512 U32 IOCSettings; /*0x08 */ 1537 U32 IOCSettings; /*0x08 */
1513 U8 SSUTimeout; /*0x0C */ 1538 U8 SSUTimeout; /*0x0C */
1514 U8 Reserved1; /*0x0D */ 1539 U8 MaxEnclosureLevel; /*0x0D */
1515 U16 Reserved2; /*0x0E */ 1540 U16 Reserved2; /*0x0E */
1516 U32 DeviceSettings; /*0x10 */ 1541 U32 DeviceSettings; /*0x10 */
1517 U16 NumberOfDevices; /*0x14 */ 1542 U16 NumberOfDevices; /*0x14 */
@@ -1531,7 +1556,6 @@ typedef struct _MPI2_CONFIG_PAGE_BIOS_1 {
1531#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1556#define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000)
1532 1557
1533#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1558#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1534#define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800)
1535#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1559#define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000)
1536#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1560#define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800)
1537#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1561#define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000)
@@ -3271,10 +3295,12 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3271 U16 NumSlots; /*0x18 */ 3295 U16 NumSlots; /*0x18 */
3272 U16 StartSlot; /*0x1A */ 3296 U16 StartSlot; /*0x1A */
3273 U8 ChassisSlot; /*0x1C */ 3297 U8 ChassisSlot; /*0x1C */
3274 U8 EnclosureLeve; /*0x1D */ 3298 U8 EnclosureLevel; /*0x1D */
3275 U16 SEPDevHandle; /*0x1E */ 3299 U16 SEPDevHandle; /*0x1E */
3276 U32 Reserved3; /*0x20 */ 3300 U8 OEMRD; /*0x20 */
3277 U32 Reserved4; /*0x24 */ 3301 U8 Reserved1a; /*0x21 */
3302 U16 Reserved2; /*0x22 */
3303 U32 Reserved3; /*0x24 */
3278} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3304} MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3279 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3305 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
3280 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t, 3306 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t,
@@ -3285,6 +3311,8 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3285#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3311#define MPI2_SASENCLOSURE0_PAGEVERSION (0x04)
3286 3312
3287/*values for SAS Enclosure Page 0 Flags field */ 3313/*values for SAS Enclosure Page 0 Flags field */
3314#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3315#define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3288#define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3316#define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3289#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3317#define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3290#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3318#define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
@@ -3298,6 +3326,8 @@ typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 {
3298#define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3326#define MPI26_ENCLOSURE0_PAGEVERSION (0x04)
3299 3327
3300/*Values for Enclosure Page 0 Flags field */ 3328/*Values for Enclosure Page 0 Flags field */
3329#define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080)
3330#define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040)
3301#define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3331#define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020)
3302#define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3332#define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010)
3303#define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3333#define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F)
@@ -3696,8 +3726,9 @@ typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA {
3696 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t; 3726 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t;
3697 3727
3698/*values for LinkFlags */ 3728/*values for LinkFlags */
3699#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) 3729#define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00)
3700#define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) 3730#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01)
3731#define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02)
3701 3732
3702/* 3733/*
3703 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3734 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
@@ -3714,7 +3745,7 @@ typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 {
3714 U16 AdditionalControlFlags; /*0x0C */ 3745 U16 AdditionalControlFlags; /*0x0C */
3715 U16 NVMeMaxQueueDepth; /*0x0E */ 3746 U16 NVMeMaxQueueDepth; /*0x0E */
3716 U8 NumPhys; /*0x10 */ 3747 U8 NumPhys; /*0x10 */
3717 U8 Reserved1; /*0x11 */ 3748 U8 DMDReportPCIe; /*0x11 */
3718 U16 Reserved2; /*0x12 */ 3749 U16 Reserved2; /*0x12 */
3719 MPI26_PCIE_IO_UNIT1_PHY_DATA 3750 MPI26_PCIE_IO_UNIT1_PHY_DATA
3720 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */ 3751 PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/*0x14 */
@@ -3736,6 +3767,12 @@ typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 {
3736#define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3767#define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40)
3737#define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3768#define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50)
3738 3769
3770/*values for PCIe IO Unit Page 1 DMDReportPCIe */
3771#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK (0x80)
3772#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC (0x00)
3773#define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC (0x80)
3774#define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK (0x7F)
3775
3739/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3776/*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo
3740 *values 3777 *values
3741 */ 3778 */
@@ -3788,6 +3825,9 @@ typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 {
3788 3825
3789/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3826/*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
3790 3827
3828/* defines for the Flags field */
3829#define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002)
3830#define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001)
3791 3831
3792/**************************************************************************** 3832/****************************************************************************
3793* PCIe Device Config Pages (MPI v2.6 and later) 3833* PCIe Device Config Pages (MPI v2.6 and later)
@@ -3849,19 +3889,21 @@ typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 {
3849 *field 3889 *field
3850 */ 3890 */
3851 3891
3852/*values for PCIe Device Page 0 Flags field */ 3892/*values for PCIe Device Page 0 Flags field*/
3853#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 3893#define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000)
3854#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) 3894#define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000)
3855#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) 3895#define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000)
3856#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) 3896#define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000)
3857#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) 3897#define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000)
3858#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 3898#define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400)
3859#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) 3899#define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200)
3860#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) 3900#define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100)
3861#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) 3901#define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080)
3862#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) 3902#define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040)
3863#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) 3903#define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020)
3864#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) 3904#define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010)
3905#define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002)
3906#define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001)
3865 3907
3866/* values for PCIe Device Page 0 SupportedLinkRates field */ 3908/* values for PCIe Device Page 0 SupportedLinkRates field */
3867#define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3909#define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08)
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_image.h b/drivers/scsi/mpt3sas/mpi/mpi2_image.h
new file mode 100644
index 000000000000..4959585f029d
--- /dev/null
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_image.h
@@ -0,0 +1,506 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright 2016-2020 Broadcom Limited. All rights reserved.
4 *
5 * Name: mpi2_image.h
6 * Description: Contains definitions for firmware and other component images
7 * Creation Date: 04/02/2018
8 * Version: 02.06.03
9 *
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 08-01-18 02.06.00 Initial version for MPI 2.6.5.
17 * 08-14-18 02.06.01 Corrected define for MPI26_IMAGE_HEADER_SIGNATURE0_MPI26
18 * 08-28-18 02.06.02 Added MPI2_EXT_IMAGE_TYPE_RDE
19 * 09-07-18 02.06.03 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES
20 */
21#ifndef MPI2_IMAGE_H
22#define MPI2_IMAGE_H
23
24
25/*FW Image Header */
26typedef struct _MPI2_FW_IMAGE_HEADER {
27 U32 Signature; /*0x00 */
28 U32 Signature0; /*0x04 */
29 U32 Signature1; /*0x08 */
30 U32 Signature2; /*0x0C */
31 MPI2_VERSION_UNION MPIVersion; /*0x10 */
32 MPI2_VERSION_UNION FWVersion; /*0x14 */
33 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */
34 MPI2_VERSION_UNION PackageVersion; /*0x1C */
35 U16 VendorID; /*0x20 */
36 U16 ProductID; /*0x22 */
37 U16 ProtocolFlags; /*0x24 */
38 U16 Reserved26; /*0x26 */
39 U32 IOCCapabilities; /*0x28 */
40 U32 ImageSize; /*0x2C */
41 U32 NextImageHeaderOffset; /*0x30 */
42 U32 Checksum; /*0x34 */
43 U32 Reserved38; /*0x38 */
44 U32 Reserved3C; /*0x3C */
45 U32 Reserved40; /*0x40 */
46 U32 Reserved44; /*0x44 */
47 U32 Reserved48; /*0x48 */
48 U32 Reserved4C; /*0x4C */
49 U32 Reserved50; /*0x50 */
50 U32 Reserved54; /*0x54 */
51 U32 Reserved58; /*0x58 */
52 U32 Reserved5C; /*0x5C */
53 U32 BootFlags; /*0x60 */
54 U32 FirmwareVersionNameWhat; /*0x64 */
55 U8 FirmwareVersionName[32]; /*0x68 */
56 U32 VendorNameWhat; /*0x88 */
57 U8 VendorName[32]; /*0x8C */
58 U32 PackageNameWhat; /*0x88 */
59 U8 PackageName[32]; /*0x8C */
60 U32 ReservedD0; /*0xD0 */
61 U32 ReservedD4; /*0xD4 */
62 U32 ReservedD8; /*0xD8 */
63 U32 ReservedDC; /*0xDC */
64 U32 ReservedE0; /*0xE0 */
65 U32 ReservedE4; /*0xE4 */
66 U32 ReservedE8; /*0xE8 */
67 U32 ReservedEC; /*0xEC */
68 U32 ReservedF0; /*0xF0 */
69 U32 ReservedF4; /*0xF4 */
70 U32 ReservedF8; /*0xF8 */
71 U32 ReservedFC; /*0xFC */
72} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
73 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
74
75/*Signature field */
76#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
77#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
78#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
79#define MPI26_FW_HEADER_SIGNATURE (0xEB000000)
80
81/*Signature0 field */
82#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
83#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
84/*Last byte is defined by architecture */
85#define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500)
86#define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A)
87#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
88#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
89/*legacy (0x5AEAA55A) */
90#define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02)
91#define MPI26_FW_HEADER_SIGNATURE0 \
92 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0)
93#define MPI26_FW_HEADER_SIGNATURE0_3516 \
94 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
95#define MPI26_FW_HEADER_SIGNATURE0_4008 \
96 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3)
97
98/*Signature1 field */
99#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
100#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
101#define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5)
102
103/*Signature2 field */
104#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
105#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
106#define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA)
107
108/*defines for using the ProductID field */
109#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
110#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
111
112#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
113#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
114#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
115#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
116
117#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
118/*SAS ProductID Family bits */
119#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
120#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
121#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
122#define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028)
123#define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031)
124
125/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
126
127/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
128
129#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
130#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
131
132#define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60)
133#define MPI2_FW_HEADER_BOOTFLAGS_ISSI32M_FLAG (0x00000001)
134#define MPI2_FW_HEADER_BOOTFLAGS_W25Q256JW_FLAG (0x00000002)
135/*This image has a auto-discovery version of SPI */
136#define MPI2_FW_HEADER_BOOTFLAGS_AUTO_SPI_FLAG (0x00000004)
137
138
139#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
140
141#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
142
143#define MPI2_FW_HEADER_SIZE (0x100)
144
145
146/****************************************************************************
147 * Component Image Format and related defines *
148 ****************************************************************************/
149
150/*Maximum number of Hash Exclusion entries in a Component Image Header */
151#define MPI26_COMP_IMG_HDR_NUM_HASH_EXCL (4)
152
153/*Hash Exclusion Format */
154typedef struct _MPI26_HASH_EXCLUSION_FORMAT {
155 U32 Offset; /*0x00 */
156 U32 Size; /*0x04 */
157} MPI26_HASH_EXCLUSION_FORMAT,
158 *PTR_MPI26_HASH_EXCLUSION_FORMAT,
159 Mpi26HashSxclusionFormat_t,
160 *pMpi26HashExclusionFormat_t;
161
162/*FW Image Header */
163typedef struct _MPI26_COMPONENT_IMAGE_HEADER {
164 U32 Signature0; /*0x00 */
165 U32 LoadAddress; /*0x04 */
166 U32 DataSize; /*0x08 */
167 U32 StartAddress; /*0x0C */
168 U32 Signature1; /*0x10 */
169 U32 FlashOffset; /*0x14 */
170 U32 FlashSize; /*0x18 */
171 U32 VersionStringOffset; /*0x1C */
172 U32 BuildDateStringOffset; /*0x20 */
173 U32 BuildTimeStringOffset; /*0x24 */
174 U32 EnvironmentVariableOffset; /*0x28 */
175 U32 ApplicationSpecific; /*0x2C */
176 U32 Signature2; /*0x30 */
177 U32 HeaderSize; /*0x34 */
178 U32 Crc; /*0x38 */
179 U8 NotFlashImage; /*0x3C */
180 U8 Compressed; /*0x3D */
181 U16 Reserved3E; /*0x3E */
182 U32 SecondaryFlashOffset; /*0x40 */
183 U32 Reserved44; /*0x44 */
184 U32 Reserved48; /*0x48 */
185 MPI2_VERSION_UNION RMCInterfaceVersion; /*0x4C */
186 MPI2_VERSION_UNION Reserved50; /*0x50 */
187 MPI2_VERSION_UNION FWVersion; /*0x54 */
188 MPI2_VERSION_UNION NvdataVersion; /*0x58 */
189 MPI26_HASH_EXCLUSION_FORMAT
190 HashExclusion[MPI26_COMP_IMG_HDR_NUM_HASH_EXCL];/*0x5C */
191 U32 NextImageHeaderOffset; /*0x7C */
192 U32 Reserved80[32]; /*0x80 -- 0xFC */
193} MPI26_COMPONENT_IMAGE_HEADER,
194 *PTR_MPI26_COMPONENT_IMAGE_HEADER,
195 Mpi26ComponentImageHeader_t,
196 *pMpi26ComponentImageHeader_t;
197
198
199/**** Definitions for Signature0 field ****/
200#define MPI26_IMAGE_HEADER_SIGNATURE0_MPI26 (0xEB000042)
201
202/**** Definitions for Signature1 field ****/
203#define MPI26_IMAGE_HEADER_SIGNATURE1_APPLICATION (0x20505041)
204#define MPI26_IMAGE_HEADER_SIGNATURE1_CBB (0x20424243)
205#define MPI26_IMAGE_HEADER_SIGNATURE1_MFG (0x2047464D)
206#define MPI26_IMAGE_HEADER_SIGNATURE1_BIOS (0x534F4942)
207#define MPI26_IMAGE_HEADER_SIGNATURE1_HIIM (0x4D494948)
208#define MPI26_IMAGE_HEADER_SIGNATURE1_HIIA (0x41494948)
209#define MPI26_IMAGE_HEADER_SIGNATURE1_CPLD (0x444C5043)
210#define MPI26_IMAGE_HEADER_SIGNATURE1_SPD (0x20445053)
211#define MPI26_IMAGE_HEADER_SIGNATURE1_NVDATA (0x5444564E)
212#define MPI26_IMAGE_HEADER_SIGNATURE1_GAS_GAUGE (0x20534147)
213#define MPI26_IMAGE_HEADER_SIGNATURE1_PBLP (0x50424C50)
214
215/**** Definitions for Signature2 field ****/
216#define MPI26_IMAGE_HEADER_SIGNATURE2_VALUE (0x50584546)
217
218/**** Offsets for Image Header Fields ****/
219#define MPI26_IMAGE_HEADER_SIGNATURE0_OFFSET (0x00)
220#define MPI26_IMAGE_HEADER_LOAD_ADDRESS_OFFSET (0x04)
221#define MPI26_IMAGE_HEADER_DATA_SIZE_OFFSET (0x08)
222#define MPI26_IMAGE_HEADER_START_ADDRESS_OFFSET (0x0C)
223#define MPI26_IMAGE_HEADER_SIGNATURE1_OFFSET (0x10)
224#define MPI26_IMAGE_HEADER_FLASH_OFFSET_OFFSET (0x14)
225#define MPI26_IMAGE_HEADER_FLASH_SIZE_OFFSET (0x18)
226#define MPI26_IMAGE_HEADER_VERSION_STRING_OFFSET_OFFSET (0x1C)
227#define MPI26_IMAGE_HEADER_BUILD_DATE_STRING_OFFSET_OFFSET (0x20)
228#define MPI26_IMAGE_HEADER_BUILD_TIME_OFFSET_OFFSET (0x24)
229#define MPI26_IMAGE_HEADER_ENVIROMENT_VAR_OFFSET_OFFSET (0x28)
230#define MPI26_IMAGE_HEADER_APPLICATION_SPECIFIC_OFFSET (0x2C)
231#define MPI26_IMAGE_HEADER_SIGNATURE2_OFFSET (0x30)
232#define MPI26_IMAGE_HEADER_HEADER_SIZE_OFFSET (0x34)
233#define MPI26_IMAGE_HEADER_CRC_OFFSET (0x38)
234#define MPI26_IMAGE_HEADER_NOT_FLASH_IMAGE_OFFSET (0x3C)
235#define MPI26_IMAGE_HEADER_COMPRESSED_OFFSET (0x3D)
236#define MPI26_IMAGE_HEADER_SECONDARY_FLASH_OFFSET_OFFSET (0x40)
237#define MPI26_IMAGE_HEADER_RMC_INTERFACE_VER_OFFSET (0x4C)
238#define MPI26_IMAGE_HEADER_COMPONENT_IMAGE_VER_OFFSET (0x54)
239#define MPI26_IMAGE_HEADER_HASH_EXCLUSION_OFFSET (0x5C)
240#define MPI26_IMAGE_HEADER_NEXT_IMAGE_HEADER_OFFSET_OFFSET (0x7C)
241
242
243#define MPI26_IMAGE_HEADER_SIZE (0x100)
244
245
246/*Extended Image Header */
247typedef struct _MPI2_EXT_IMAGE_HEADER {
248 U8 ImageType; /*0x00 */
249 U8 Reserved1; /*0x01 */
250 U16 Reserved2; /*0x02 */
251 U32 Checksum; /*0x04 */
252 U32 ImageSize; /*0x08 */
253 U32 NextImageHeaderOffset; /*0x0C */
254 U32 PackageVersion; /*0x10 */
255 U32 Reserved3; /*0x14 */
256 U32 Reserved4; /*0x18 */
257 U32 Reserved5; /*0x1C */
258 U8 IdentifyString[32]; /*0x20 */
259} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
260 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
261
262/*useful offsets */
263#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
264#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
265#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
266#define MPI2_EXT_IMAGE_PACKAGEVERSION_OFFSET (0x10)
267
268#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
269
270/*defines for the ImageType field */
271#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
272#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
273#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
274#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
275#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
276#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
277#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
278#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
279#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
280#define MPI2_EXT_IMAGE_TYPE_RDE (0x0A)
281#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
282#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
283
284#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
285
286/*FLASH Layout Extended Image Data */
287
288/*
289 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
290 *one and check RegionsPerLayout at runtime.
291 */
292#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
293#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
294#endif
295
296/*
297 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
298 *one and check NumberOfLayouts at runtime.
299 */
300#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
301#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
302#endif
303
304typedef struct _MPI2_FLASH_REGION {
305 U8 RegionType; /*0x00 */
306 U8 Reserved1; /*0x01 */
307 U16 Reserved2; /*0x02 */
308 U32 RegionOffset; /*0x04 */
309 U32 RegionSize; /*0x08 */
310 U32 Reserved3; /*0x0C */
311} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
312 Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
313
314typedef struct _MPI2_FLASH_LAYOUT {
315 U32 FlashSize; /*0x00 */
316 U32 Reserved1; /*0x04 */
317 U32 Reserved2; /*0x08 */
318 U32 Reserved3; /*0x0C */
319 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
320} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
321 Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
322
323typedef struct _MPI2_FLASH_LAYOUT_DATA {
324 U8 ImageRevision; /*0x00 */
325 U8 Reserved1; /*0x01 */
326 U8 SizeOfRegion; /*0x02 */
327 U8 Reserved2; /*0x03 */
328 U16 NumberOfLayouts; /*0x04 */
329 U16 RegionsPerLayout; /*0x06 */
330 U16 MinimumSectorAlignment; /*0x08 */
331 U16 Reserved3; /*0x0A */
332 U32 Reserved4; /*0x0C */
333 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
334} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
335 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
336
337/*defines for the RegionType field */
338#define MPI2_FLASH_REGION_UNUSED (0x00)
339#define MPI2_FLASH_REGION_FIRMWARE (0x01)
340#define MPI2_FLASH_REGION_BIOS (0x02)
341#define MPI2_FLASH_REGION_NVDATA (0x03)
342#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
343#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
344#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
345#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
346#define MPI2_FLASH_REGION_MEGARAID (0x09)
347#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
348#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
349#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
350#define MPI2_FLASH_REGION_SBR (0x0E)
351#define MPI2_FLASH_REGION_SBR_BACKUP (0x0F)
352#define MPI2_FLASH_REGION_HIIM (0x10)
353#define MPI2_FLASH_REGION_HIIA (0x11)
354#define MPI2_FLASH_REGION_CTLR (0x12)
355#define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13)
356#define MPI2_FLASH_REGION_MR_NVDATA (0x14)
357#define MPI2_FLASH_REGION_CPLD (0x15)
358#define MPI2_FLASH_REGION_PSOC (0x16)
359
360/*ImageRevision */
361#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
362
363/*Supported Devices Extended Image Data */
364
365/*
366 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
367 *one and check NumberOfDevices at runtime.
368 */
369#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
370#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
371#endif
372
373typedef struct _MPI2_SUPPORTED_DEVICE {
374 U16 DeviceID; /*0x00 */
375 U16 VendorID; /*0x02 */
376 U16 DeviceIDMask; /*0x04 */
377 U16 Reserved1; /*0x06 */
378 U8 LowPCIRev; /*0x08 */
379 U8 HighPCIRev; /*0x09 */
380 U16 Reserved2; /*0x0A */
381 U32 Reserved3; /*0x0C */
382} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
383 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
384
385typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
386 U8 ImageRevision; /*0x00 */
387 U8 Reserved1; /*0x01 */
388 U8 NumberOfDevices; /*0x02 */
389 U8 Reserved2; /*0x03 */
390 U32 Reserved3; /*0x04 */
391 MPI2_SUPPORTED_DEVICE
392 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
393} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
394 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
395
396/*ImageRevision */
397#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
398
399/*Init Extended Image Data */
400
401typedef struct _MPI2_INIT_IMAGE_FOOTER {
402 U32 BootFlags; /*0x00 */
403 U32 ImageSize; /*0x04 */
404 U32 Signature0; /*0x08 */
405 U32 Signature1; /*0x0C */
406 U32 Signature2; /*0x10 */
407 U32 ResetVector; /*0x14 */
408} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
409 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
410
411/*defines for the BootFlags field */
412#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
413
414/*defines for the ImageSize field */
415#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
416
417/*defines for the Signature0 field */
418#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
419#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
420
421/*defines for the Signature1 field */
422#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
423#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
424
425/*defines for the Signature2 field */
426#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
427#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
428
429/*Signature fields as individual bytes */
430#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
431#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
432#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
433#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
434
435#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
436#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
437#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
438#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
439
440#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
441#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
442#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
443#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
444
445/*defines for the ResetVector field */
446#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
447
448
449/* Encrypted Hash Extended Image Data */
450
451typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
452 U8 HashImageType; /*0x00 */
453 U8 HashAlgorithm; /*0x01 */
454 U8 EncryptionAlgorithm; /*0x02 */
455 U8 Reserved1; /*0x03 */
456 U32 Reserved2; /*0x04 */
457 U32 EncryptedHash[1]; /*0x08 */ /* variable length */
458} MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
459Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
460
461/* values for HashImageType */
462#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00)
463#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01)
464#define MPI25_HASH_IMAGE_TYPE_BIOS (0x02)
465
466#define MPI26_HASH_IMAGE_TYPE_UNUSED (0x00)
467#define MPI26_HASH_IMAGE_TYPE_FIRMWARE (0x01)
468#define MPI26_HASH_IMAGE_TYPE_BIOS (0x02)
469#define MPI26_HASH_IMAGE_TYPE_KEY_HASH (0x03)
470
471/* values for HashAlgorithm */
472#define MPI25_HASH_ALGORITHM_UNUSED (0x00)
473#define MPI25_HASH_ALGORITHM_SHA256 (0x01)
474
475#define MPI26_HASH_ALGORITHM_VERSION_MASK (0xE0)
476#define MPI26_HASH_ALGORITHM_VERSION_NONE (0x00)
477#define MPI26_HASH_ALGORITHM_VERSION_SHA1 (0x20)
478#define MPI26_HASH_ALGORITHM_VERSION_SHA2 (0x40)
479#define MPI26_HASH_ALGORITHM_VERSION_SHA3 (0x60)
480#define MPI26_HASH_ALGORITHM_SIZE_MASK (0x1F)
481#define MPI26_HASH_ALGORITHM_SIZE_256 (0x01)
482#define MPI26_HASH_ALGORITHM_SIZE_512 (0x02)
483
484
485/* values for EncryptionAlgorithm */
486#define MPI25_ENCRYPTION_ALG_UNUSED (0x00)
487#define MPI25_ENCRYPTION_ALG_RSA256 (0x01)
488
489#define MPI26_ENCRYPTION_ALG_UNUSED (0x00)
490#define MPI26_ENCRYPTION_ALG_RSA256 (0x01)
491#define MPI26_ENCRYPTION_ALG_RSA512 (0x02)
492#define MPI26_ENCRYPTION_ALG_RSA1024 (0x03)
493#define MPI26_ENCRYPTION_ALG_RSA2048 (0x04)
494#define MPI26_ENCRYPTION_ALG_RSA4096 (0x05)
495
496typedef struct _MPI25_ENCRYPTED_HASH_DATA {
497 U8 ImageVersion; /*0x00 */
498 U8 NumHash; /*0x01 */
499 U16 Reserved1; /*0x02 */
500 U32 Reserved2; /*0x04 */
501 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /*0x08 */
502} MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
503Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
504
505
506#endif /* MPI2_IMAGE_H */
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_init.h b/drivers/scsi/mpt3sas/mpi/mpi2_init.h
index 6213ce6791ac..8f1b903fe0a9 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2_init.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_init.h
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * 4 *
5 * 5 *
6 * Name: mpi2_init.h 6 * Name: mpi2_init.h
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h b/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
index 1faec3a93e69..68ea408cd5c5 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_ioc.h
@@ -1,13 +1,13 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * 4 *
5 * 5 *
6 * Name: mpi2_ioc.h 6 * Name: mpi2_ioc.h
7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 7 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages
8 * Creation Date: October 11, 2006 8 * Creation Date: October 11, 2006
9 * 9 *
10 * mpi2_ioc.h Version: 02.00.34 10 * mpi2_ioc.h Version: 02.00.37
11 * 11 *
12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
13 * prefix are for use only on MPI v2.5 products, and must not be used 13 * prefix are for use only on MPI v2.5 products, and must not be used
@@ -171,6 +171,10 @@
171 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED 171 * 09-29-17 02.00.34 Added MPI26_EVENT_PCIDEV_STAT_RC_PCIE_HOT_RESET_FAILED
172 * to the ReasonCode field in PCIe Device Status Change 172 * to the ReasonCode field in PCIe Device Status Change
173 * Event Data. 173 * Event Data.
174 * 07-22-18 02.00.35 Added FW_DOWNLOAD_ITYPE_CPLD and _PSOC.
175 * Moved FW image definitions ionto new mpi2_image,h
176 * 08-14-18 02.00.36 Fixed definition of MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
177 * 09-07-18 02.00.37 Added MPI26_EVENT_PCIE_TOPO_PI_16_LANES
174 * -------------------------------------------------------------------------- 178 * --------------------------------------------------------------------------
175 */ 179 */
176 180
@@ -1255,6 +1259,7 @@ typedef struct _MPI26_EVENT_PCIE_TOPO_PORT_ENTRY {
1255#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20) 1259#define MPI26_EVENT_PCIE_TOPO_PI_2_LANES (0x20)
1256#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30) 1260#define MPI26_EVENT_PCIE_TOPO_PI_4_LANES (0x30)
1257#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40) 1261#define MPI26_EVENT_PCIE_TOPO_PI_8_LANES (0x40)
1262#define MPI26_EVENT_PCIE_TOPO_PI_16_LANES (0x50)
1258 1263
1259#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F) 1264#define MPI26_EVENT_PCIE_TOPO_PI_RATE_MASK (0x0F)
1260#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00) 1265#define MPI26_EVENT_PCIE_TOPO_PI_RATE_UNKNOWN (0x00)
@@ -1450,7 +1455,11 @@ typedef struct _MPI2_FW_DOWNLOAD_REQUEST {
1450#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12) 1455#define MPI2_FW_DOWNLOAD_ITYPE_CTLR (0x12)
1451#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13) 1456#define MPI2_FW_DOWNLOAD_ITYPE_IMR_FIRMWARE (0x13)
1452#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14) 1457#define MPI2_FW_DOWNLOAD_ITYPE_MR_NVDATA (0x14)
1458/*MPI v2.6 and newer */
1459#define MPI2_FW_DOWNLOAD_ITYPE_CPLD (0x15)
1460#define MPI2_FW_DOWNLOAD_ITYPE_PSOC (0x16)
1453#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1461#define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0)
1462#define MPI2_FW_DOWNLOAD_ITYPE_TERMINATE (0xFF)
1454 1463
1455/*MPI v2.0 FWDownload TransactionContext Element */ 1464/*MPI v2.0 FWDownload TransactionContext Element */
1456typedef struct _MPI2_FW_DOWNLOAD_TCSGE { 1465typedef struct _MPI2_FW_DOWNLOAD_TCSGE {
@@ -1597,352 +1606,6 @@ typedef struct _MPI2_FW_UPLOAD_REPLY {
1597} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY, 1606} MPI2_FW_UPLOAD_REPLY, *PTR_MPI2_FW_UPLOAD_REPLY,
1598 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t; 1607 Mpi2FWUploadReply_t, *pMPi2FWUploadReply_t;
1599 1608
1600/*FW Image Header */
1601typedef struct _MPI2_FW_IMAGE_HEADER {
1602 U32 Signature; /*0x00 */
1603 U32 Signature0; /*0x04 */
1604 U32 Signature1; /*0x08 */
1605 U32 Signature2; /*0x0C */
1606 MPI2_VERSION_UNION MPIVersion; /*0x10 */
1607 MPI2_VERSION_UNION FWVersion; /*0x14 */
1608 MPI2_VERSION_UNION NVDATAVersion; /*0x18 */
1609 MPI2_VERSION_UNION PackageVersion; /*0x1C */
1610 U16 VendorID; /*0x20 */
1611 U16 ProductID; /*0x22 */
1612 U16 ProtocolFlags; /*0x24 */
1613 U16 Reserved26; /*0x26 */
1614 U32 IOCCapabilities; /*0x28 */
1615 U32 ImageSize; /*0x2C */
1616 U32 NextImageHeaderOffset; /*0x30 */
1617 U32 Checksum; /*0x34 */
1618 U32 Reserved38; /*0x38 */
1619 U32 Reserved3C; /*0x3C */
1620 U32 Reserved40; /*0x40 */
1621 U32 Reserved44; /*0x44 */
1622 U32 Reserved48; /*0x48 */
1623 U32 Reserved4C; /*0x4C */
1624 U32 Reserved50; /*0x50 */
1625 U32 Reserved54; /*0x54 */
1626 U32 Reserved58; /*0x58 */
1627 U32 Reserved5C; /*0x5C */
1628 U32 BootFlags; /*0x60 */
1629 U32 FirmwareVersionNameWhat; /*0x64 */
1630 U8 FirmwareVersionName[32]; /*0x68 */
1631 U32 VendorNameWhat; /*0x88 */
1632 U8 VendorName[32]; /*0x8C */
1633 U32 PackageNameWhat; /*0x88 */
1634 U8 PackageName[32]; /*0x8C */
1635 U32 ReservedD0; /*0xD0 */
1636 U32 ReservedD4; /*0xD4 */
1637 U32 ReservedD8; /*0xD8 */
1638 U32 ReservedDC; /*0xDC */
1639 U32 ReservedE0; /*0xE0 */
1640 U32 ReservedE4; /*0xE4 */
1641 U32 ReservedE8; /*0xE8 */
1642 U32 ReservedEC; /*0xEC */
1643 U32 ReservedF0; /*0xF0 */
1644 U32 ReservedF4; /*0xF4 */
1645 U32 ReservedF8; /*0xF8 */
1646 U32 ReservedFC; /*0xFC */
1647} MPI2_FW_IMAGE_HEADER, *PTR_MPI2_FW_IMAGE_HEADER,
1648 Mpi2FWImageHeader_t, *pMpi2FWImageHeader_t;
1649
1650/*Signature field */
1651#define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00)
1652#define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000)
1653#define MPI2_FW_HEADER_SIGNATURE (0xEA000000)
1654#define MPI26_FW_HEADER_SIGNATURE (0xEB000000)
1655
1656/*Signature0 field */
1657#define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04)
1658#define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A)
1659/* Last byte is defined by architecture */
1660#define MPI26_FW_HEADER_SIGNATURE0_BASE (0x5AEAA500)
1661#define MPI26_FW_HEADER_SIGNATURE0_ARC_0 (0x5A)
1662#define MPI26_FW_HEADER_SIGNATURE0_ARC_1 (0x00)
1663#define MPI26_FW_HEADER_SIGNATURE0_ARC_2 (0x01)
1664/* legacy (0x5AEAA55A) */
1665#define MPI26_FW_HEADER_SIGNATURE0_ARC_3 (0x02)
1666#define MPI26_FW_HEADER_SIGNATURE0 \
1667 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_0)
1668#define MPI26_FW_HEADER_SIGNATURE0_3516 \
1669 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_1)
1670#define MPI26_FW_HEADER_SIGNATURE0_4008 \
1671 (MPI26_FW_HEADER_SIGNATURE0_BASE+MPI26_FW_HEADER_SIGNATURE0_ARC_3)
1672
1673/*Signature1 field */
1674#define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08)
1675#define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5)
1676#define MPI26_FW_HEADER_SIGNATURE1 (0xA55AEAA5)
1677
1678/*Signature2 field */
1679#define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C)
1680#define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA)
1681#define MPI26_FW_HEADER_SIGNATURE2 (0x5AA55AEA)
1682
1683/*defines for using the ProductID field */
1684#define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000)
1685#define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000)
1686
1687#define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00)
1688#define MPI2_FW_HEADER_PID_PROD_A (0x0000)
1689#define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200)
1690#define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700)
1691
1692#define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF)
1693/*SAS ProductID Family bits */
1694#define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013)
1695#define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014)
1696#define MPI25_FW_HEADER_PID_FAMILY_3108_SAS (0x0021)
1697#define MPI26_FW_HEADER_PID_FAMILY_3324_SAS (0x0028)
1698#define MPI26_FW_HEADER_PID_FAMILY_3516_SAS (0x0031)
1699
1700/*use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */
1701
1702/*use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */
1703
1704#define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C)
1705#define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30)
1706#define MPI26_FW_HEADER_BOOTFLAGS_OFFSET (0x60)
1707#define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64)
1708
1709#define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840)
1710
1711#define MPI2_FW_HEADER_SIZE (0x100)
1712
1713/*Extended Image Header */
1714typedef struct _MPI2_EXT_IMAGE_HEADER {
1715 U8 ImageType; /*0x00 */
1716 U8 Reserved1; /*0x01 */
1717 U16 Reserved2; /*0x02 */
1718 U32 Checksum; /*0x04 */
1719 U32 ImageSize; /*0x08 */
1720 U32 NextImageHeaderOffset; /*0x0C */
1721 U32 PackageVersion; /*0x10 */
1722 U32 Reserved3; /*0x14 */
1723 U32 Reserved4; /*0x18 */
1724 U32 Reserved5; /*0x1C */
1725 U8 IdentifyString[32]; /*0x20 */
1726} MPI2_EXT_IMAGE_HEADER, *PTR_MPI2_EXT_IMAGE_HEADER,
1727 Mpi2ExtImageHeader_t, *pMpi2ExtImageHeader_t;
1728
1729/*useful offsets */
1730#define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00)
1731#define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08)
1732#define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C)
1733
1734#define MPI2_EXT_IMAGE_HEADER_SIZE (0x40)
1735
1736/*defines for the ImageType field */
1737#define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00)
1738#define MPI2_EXT_IMAGE_TYPE_FW (0x01)
1739#define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03)
1740#define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04)
1741#define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05)
1742#define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06)
1743#define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07)
1744#define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08)
1745#define MPI2_EXT_IMAGE_TYPE_ENCRYPTED_HASH (0x09)
1746#define MPI2_EXT_IMAGE_TYPE_MIN_PRODUCT_SPECIFIC (0x80)
1747#define MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC (0xFF)
1748
1749#define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MAX_PRODUCT_SPECIFIC)
1750
1751/*FLASH Layout Extended Image Data */
1752
1753/*
1754 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1755 *one and check RegionsPerLayout at runtime.
1756 */
1757#ifndef MPI2_FLASH_NUMBER_OF_REGIONS
1758#define MPI2_FLASH_NUMBER_OF_REGIONS (1)
1759#endif
1760
1761/*
1762 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1763 *one and check NumberOfLayouts at runtime.
1764 */
1765#ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS
1766#define MPI2_FLASH_NUMBER_OF_LAYOUTS (1)
1767#endif
1768
1769typedef struct _MPI2_FLASH_REGION {
1770 U8 RegionType; /*0x00 */
1771 U8 Reserved1; /*0x01 */
1772 U16 Reserved2; /*0x02 */
1773 U32 RegionOffset; /*0x04 */
1774 U32 RegionSize; /*0x08 */
1775 U32 Reserved3; /*0x0C */
1776} MPI2_FLASH_REGION, *PTR_MPI2_FLASH_REGION,
1777 Mpi2FlashRegion_t, *pMpi2FlashRegion_t;
1778
1779typedef struct _MPI2_FLASH_LAYOUT {
1780 U32 FlashSize; /*0x00 */
1781 U32 Reserved1; /*0x04 */
1782 U32 Reserved2; /*0x08 */
1783 U32 Reserved3; /*0x0C */
1784 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS]; /*0x10 */
1785} MPI2_FLASH_LAYOUT, *PTR_MPI2_FLASH_LAYOUT,
1786 Mpi2FlashLayout_t, *pMpi2FlashLayout_t;
1787
1788typedef struct _MPI2_FLASH_LAYOUT_DATA {
1789 U8 ImageRevision; /*0x00 */
1790 U8 Reserved1; /*0x01 */
1791 U8 SizeOfRegion; /*0x02 */
1792 U8 Reserved2; /*0x03 */
1793 U16 NumberOfLayouts; /*0x04 */
1794 U16 RegionsPerLayout; /*0x06 */
1795 U16 MinimumSectorAlignment; /*0x08 */
1796 U16 Reserved3; /*0x0A */
1797 U32 Reserved4; /*0x0C */
1798 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS]; /*0x10 */
1799} MPI2_FLASH_LAYOUT_DATA, *PTR_MPI2_FLASH_LAYOUT_DATA,
1800 Mpi2FlashLayoutData_t, *pMpi2FlashLayoutData_t;
1801
1802/*defines for the RegionType field */
1803#define MPI2_FLASH_REGION_UNUSED (0x00)
1804#define MPI2_FLASH_REGION_FIRMWARE (0x01)
1805#define MPI2_FLASH_REGION_BIOS (0x02)
1806#define MPI2_FLASH_REGION_NVDATA (0x03)
1807#define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05)
1808#define MPI2_FLASH_REGION_MFG_INFORMATION (0x06)
1809#define MPI2_FLASH_REGION_CONFIG_1 (0x07)
1810#define MPI2_FLASH_REGION_CONFIG_2 (0x08)
1811#define MPI2_FLASH_REGION_MEGARAID (0x09)
1812#define MPI2_FLASH_REGION_COMMON_BOOT_BLOCK (0x0A)
1813#define MPI2_FLASH_REGION_INIT (MPI2_FLASH_REGION_COMMON_BOOT_BLOCK)
1814#define MPI2_FLASH_REGION_CBB_BACKUP (0x0D)
1815#define MPI2_FLASH_REGION_SBR (0x0E)
1816#define MPI2_FLASH_REGION_SBR_BACKUP (0x0F)
1817#define MPI2_FLASH_REGION_HIIM (0x10)
1818#define MPI2_FLASH_REGION_HIIA (0x11)
1819#define MPI2_FLASH_REGION_CTLR (0x12)
1820#define MPI2_FLASH_REGION_IMR_FIRMWARE (0x13)
1821#define MPI2_FLASH_REGION_MR_NVDATA (0x14)
1822
1823/*ImageRevision */
1824#define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00)
1825
1826/*Supported Devices Extended Image Data */
1827
1828/*
1829 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1830 *one and check NumberOfDevices at runtime.
1831 */
1832#ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES
1833#define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1)
1834#endif
1835
1836typedef struct _MPI2_SUPPORTED_DEVICE {
1837 U16 DeviceID; /*0x00 */
1838 U16 VendorID; /*0x02 */
1839 U16 DeviceIDMask; /*0x04 */
1840 U16 Reserved1; /*0x06 */
1841 U8 LowPCIRev; /*0x08 */
1842 U8 HighPCIRev; /*0x09 */
1843 U16 Reserved2; /*0x0A */
1844 U32 Reserved3; /*0x0C */
1845} MPI2_SUPPORTED_DEVICE, *PTR_MPI2_SUPPORTED_DEVICE,
1846 Mpi2SupportedDevice_t, *pMpi2SupportedDevice_t;
1847
1848typedef struct _MPI2_SUPPORTED_DEVICES_DATA {
1849 U8 ImageRevision; /*0x00 */
1850 U8 Reserved1; /*0x01 */
1851 U8 NumberOfDevices; /*0x02 */
1852 U8 Reserved2; /*0x03 */
1853 U32 Reserved3; /*0x04 */
1854 MPI2_SUPPORTED_DEVICE
1855 SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES];/*0x08 */
1856} MPI2_SUPPORTED_DEVICES_DATA, *PTR_MPI2_SUPPORTED_DEVICES_DATA,
1857 Mpi2SupportedDevicesData_t, *pMpi2SupportedDevicesData_t;
1858
1859/*ImageRevision */
1860#define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00)
1861
1862/*Init Extended Image Data */
1863
1864typedef struct _MPI2_INIT_IMAGE_FOOTER {
1865 U32 BootFlags; /*0x00 */
1866 U32 ImageSize; /*0x04 */
1867 U32 Signature0; /*0x08 */
1868 U32 Signature1; /*0x0C */
1869 U32 Signature2; /*0x10 */
1870 U32 ResetVector; /*0x14 */
1871} MPI2_INIT_IMAGE_FOOTER, *PTR_MPI2_INIT_IMAGE_FOOTER,
1872 Mpi2InitImageFooter_t, *pMpi2InitImageFooter_t;
1873
1874/*defines for the BootFlags field */
1875#define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00)
1876
1877/*defines for the ImageSize field */
1878#define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04)
1879
1880/*defines for the Signature0 field */
1881#define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08)
1882#define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA)
1883
1884/*defines for the Signature1 field */
1885#define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C)
1886#define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5)
1887
1888/*defines for the Signature2 field */
1889#define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10)
1890#define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A)
1891
1892/*Signature fields as individual bytes */
1893#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA)
1894#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A)
1895#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5)
1896#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A)
1897
1898#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5)
1899#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA)
1900#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A)
1901#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5)
1902
1903#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A)
1904#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5)
1905#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA)
1906#define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A)
1907
1908/*defines for the ResetVector field */
1909#define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14)
1910
1911
1912/* Encrypted Hash Extended Image Data */
1913
1914typedef struct _MPI25_ENCRYPTED_HASH_ENTRY {
1915 U8 HashImageType; /* 0x00 */
1916 U8 HashAlgorithm; /* 0x01 */
1917 U8 EncryptionAlgorithm; /* 0x02 */
1918 U8 Reserved1; /* 0x03 */
1919 U32 Reserved2; /* 0x04 */
1920 U32 EncryptedHash[1]; /* 0x08 */ /* variable length */
1921} MPI25_ENCRYPTED_HASH_ENTRY, *PTR_MPI25_ENCRYPTED_HASH_ENTRY,
1922Mpi25EncryptedHashEntry_t, *pMpi25EncryptedHashEntry_t;
1923
1924/* values for HashImageType */
1925#define MPI25_HASH_IMAGE_TYPE_UNUSED (0x00)
1926#define MPI25_HASH_IMAGE_TYPE_FIRMWARE (0x01)
1927#define MPI25_HASH_IMAGE_TYPE_BIOS (0x02)
1928
1929/* values for HashAlgorithm */
1930#define MPI25_HASH_ALGORITHM_UNUSED (0x00)
1931#define MPI25_HASH_ALGORITHM_SHA256 (0x01)
1932
1933/* values for EncryptionAlgorithm */
1934#define MPI25_ENCRYPTION_ALG_UNUSED (0x00)
1935#define MPI25_ENCRYPTION_ALG_RSA256 (0x01)
1936
1937typedef struct _MPI25_ENCRYPTED_HASH_DATA {
1938 U8 ImageVersion; /* 0x00 */
1939 U8 NumHash; /* 0x01 */
1940 U16 Reserved1; /* 0x02 */
1941 U32 Reserved2; /* 0x04 */
1942 MPI25_ENCRYPTED_HASH_ENTRY EncryptedHashEntry[1]; /* 0x08 */
1943} MPI25_ENCRYPTED_HASH_DATA, *PTR_MPI25_ENCRYPTED_HASH_DATA,
1944Mpi25EncryptedHashData_t, *pMpi25EncryptedHashData_t;
1945
1946 1609
1947/**************************************************************************** 1610/****************************************************************************
1948* PowerManagementControl message 1611* PowerManagementControl message
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_pci.h b/drivers/scsi/mpt3sas/mpi/mpi2_pci.h
index f0281f943ec9..63a09509d7d1 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2_pci.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_pci.h
@@ -1,12 +1,12 @@
1/* 1/*
2 * Copyright 2012-2015 Avago Technologies. All rights reserved. 2 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
3 * 3 *
4 * 4 *
5 * Name: mpi2_pci.h 5 * Name: mpi2_pci.h
6 * Title: MPI PCIe Attached Devices structures and definitions. 6 * Title: MPI PCIe Attached Devices structures and definitions.
7 * Creation Date: October 9, 2012 7 * Creation Date: October 9, 2012
8 * 8 *
9 * mpi2_pci.h Version: 02.00.02 9 * mpi2_pci.h Version: 02.00.03
10 * 10 *
11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 11 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25
12 * prefix are for use only on MPI v2.5 products, and must not be used 12 * prefix are for use only on MPI v2.5 products, and must not be used
@@ -23,6 +23,7 @@
23 * Removed SOP support. 23 * Removed SOP support.
24 * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to 24 * 07-01-16 02.00.02 Added MPI26_NVME_FLAGS_FORCE_ADMIN_ERR_RESP to
25 * NVME Encapsulated Request. 25 * NVME Encapsulated Request.
26 * 07-22-18 02.00.03 Updted flags field for NVME Encapsulated req
26 * -------------------------------------------------------------------------- 27 * --------------------------------------------------------------------------
27 */ 28 */
28 29
@@ -75,10 +76,10 @@ typedef struct _MPI26_NVME_ENCAPSULATED_REQUEST {
75#define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0010) 76#define MPI26_NVME_FLAGS_SUBMISSIONQ_ADMIN (0x0010)
76/*Error Response Address Space */ 77/*Error Response Address Space */
77#define MPI26_NVME_FLAGS_MASK_ERROR_RSP_ADDR (0x000C) 78#define MPI26_NVME_FLAGS_MASK_ERROR_RSP_ADDR (0x000C)
79#define MPI26_NVME_FLAGS_MASK_ERROR_RSP_ADDR_MASK (0x000C)
78#define MPI26_NVME_FLAGS_SYSTEM_RSP_ADDR (0x0000) 80#define MPI26_NVME_FLAGS_SYSTEM_RSP_ADDR (0x0000)
79#define MPI26_NVME_FLAGS_IOCPLB_RSP_ADDR (0x0008) 81#define MPI26_NVME_FLAGS_IOCCTL_RSP_ADDR (0x0008)
80#define MPI26_NVME_FLAGS_IOCPLBNTA_RSP_ADDR (0x000C) 82/* Data Direction*/
81/*Data Direction*/
82#define MPI26_NVME_FLAGS_DATADIRECTION_MASK (0x0003) 83#define MPI26_NVME_FLAGS_DATADIRECTION_MASK (0x0003)
83#define MPI26_NVME_FLAGS_NODATATRANSFER (0x0000) 84#define MPI26_NVME_FLAGS_NODATATRANSFER (0x0000)
84#define MPI26_NVME_FLAGS_WRITE (0x0001) 85#define MPI26_NVME_FLAGS_WRITE (0x0001)
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_raid.h b/drivers/scsi/mpt3sas/mpi/mpi2_raid.h
index b9bb1c178f12..b770eb516c14 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2_raid.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_raid.h
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Copyright 2000-2014 Avago Technologies. All rights reserved. 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * 4 *
5 * 5 *
6 * Name: mpi2_raid.h 6 * Name: mpi2_raid.h
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_sas.h b/drivers/scsi/mpt3sas/mpi/mpi2_sas.h
index afa17ff246b4..16c922a8a02b 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2_sas.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_sas.h
@@ -1,6 +1,6 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Copyright 2000-2015 Avago Technologies. All rights reserved. 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * 4 *
5 * 5 *
6 * Name: mpi2_sas.h 6 * Name: mpi2_sas.h
diff --git a/drivers/scsi/mpt3sas/mpi/mpi2_tool.h b/drivers/scsi/mpt3sas/mpi/mpi2_tool.h
index 629296ee9236..3f966b6796b3 100644
--- a/drivers/scsi/mpt3sas/mpi/mpi2_tool.h
+++ b/drivers/scsi/mpt3sas/mpi/mpi2_tool.h
@@ -1,13 +1,13 @@
1/* SPDX-License-Identifier: GPL-2.0 */ 1/* SPDX-License-Identifier: GPL-2.0 */
2/* 2/*
3 * Copyright 2000-2014 Avago Technologies. All rights reserved. 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved.
4 * 4 *
5 * 5 *
6 * Name: mpi2_tool.h 6 * Name: mpi2_tool.h
7 * Title: MPI diagnostic tool structures and definitions 7 * Title: MPI diagnostic tool structures and definitions
8 * Creation Date: March 26, 2007 8 * Creation Date: March 26, 2007
9 * 9 *
10 * mpi2_tool.h Version: 02.00.14 10 * mpi2_tool.h Version: 02.00.15
11 * 11 *
12 * Version History 12 * Version History
13 * --------------- 13 * ---------------
@@ -38,6 +38,8 @@
38 * 11-18-14 02.00.13 Updated copyright information. 38 * 11-18-14 02.00.13 Updated copyright information.
39 * 08-25-16 02.00.14 Added new values for the Flags field of Toolbox Clean 39 * 08-25-16 02.00.14 Added new values for the Flags field of Toolbox Clean
40 * Tool Request Message. 40 * Tool Request Message.
41 * 07-22-18 02.00.15 Added defines for new TOOLBOX_PCIE_LANE_MARGINING tool.
42 * Added option for DeviceInfo field in ISTWI tool.
41 * -------------------------------------------------------------------------- 43 * --------------------------------------------------------------------------
42 */ 44 */
43 45
@@ -58,6 +60,7 @@
58#define MPI2_TOOLBOX_BEACON_TOOL (0x05) 60#define MPI2_TOOLBOX_BEACON_TOOL (0x05)
59#define MPI2_TOOLBOX_DIAGNOSTIC_CLI_TOOL (0x06) 61#define MPI2_TOOLBOX_DIAGNOSTIC_CLI_TOOL (0x06)
60#define MPI2_TOOLBOX_TEXT_DISPLAY_TOOL (0x07) 62#define MPI2_TOOLBOX_TEXT_DISPLAY_TOOL (0x07)
63#define MPI26_TOOLBOX_BACKEND_PCIE_LANE_MARGIN (0x08)
61 64
62/**************************************************************************** 65/****************************************************************************
63* Toolbox reply 66* Toolbox reply
@@ -226,6 +229,13 @@ typedef struct _MPI2_TOOLBOX_ISTWI_READ_WRITE_REQUEST {
226#define MPI2_TOOL_ISTWI_FLAG_AUTO_RESERVE_RELEASE (0x80) 229#define MPI2_TOOL_ISTWI_FLAG_AUTO_RESERVE_RELEASE (0x80)
227#define MPI2_TOOL_ISTWI_FLAG_PAGE_ADDR_MASK (0x07) 230#define MPI2_TOOL_ISTWI_FLAG_PAGE_ADDR_MASK (0x07)
228 231
232/*MPI26 TOOLBOX Request MsgFlags defines */
233#define MPI26_TOOLBOX_REQ_MSGFLAGS_ADDRESSING_MASK (0x01)
234/*Request uses Man Page 43 device index addressing */
235#define MPI26_TOOLBOX_REQ_MSGFLAGS_ADDRESSING_DEVINDEX (0x00)
236/*Request uses Man Page 43 device info struct addressing */
237#define MPI26_TOOLBOX_REQ_MSGFLAGS_ADDRESSING_DEVINFO (0x01)
238
229/*Toolbox ISTWI Read Write Tool reply message */ 239/*Toolbox ISTWI Read Write Tool reply message */
230typedef struct _MPI2_TOOLBOX_ISTWI_REPLY { 240typedef struct _MPI2_TOOLBOX_ISTWI_REPLY {
231 U8 Tool; /*0x00 */ 241 U8 Tool; /*0x00 */
@@ -387,6 +397,64 @@ Mpi2ToolboxTextDisplayRequest_t,
387#define MPI2_TOOLBOX_CONSOLE_FLAG_TIMESTAMP (0x01) 397#define MPI2_TOOLBOX_CONSOLE_FLAG_TIMESTAMP (0x01)
388 398
389 399
400/***************************************************************************
401 * Toolbox Backend Lane Margining Tool
402 ***************************************************************************
403 */
404
405/*Toolbox Backend Lane Margining Tool request message */
406typedef struct _MPI26_TOOLBOX_LANE_MARGINING_REQUEST {
407 U8 Tool; /*0x00 */
408 U8 Reserved1; /*0x01 */
409 U8 ChainOffset; /*0x02 */
410 U8 Function; /*0x03 */
411 U16 Reserved2; /*0x04 */
412 U8 Reserved3; /*0x06 */
413 U8 MsgFlags; /*0x07 */
414 U8 VP_ID; /*0x08 */
415 U8 VF_ID; /*0x09 */
416 U16 Reserved4; /*0x0A */
417 U8 Command; /*0x0C */
418 U8 SwitchPort; /*0x0D */
419 U16 DevHandle; /*0x0E */
420 U8 RegisterOffset; /*0x10 */
421 U8 Reserved5; /*0x11 */
422 U16 DataLength; /*0x12 */
423 MPI25_SGE_IO_UNION SGL; /*0x14 */
424} MPI26_TOOLBOX_LANE_MARGINING_REQUEST,
425 *PTR_MPI2_TOOLBOX_LANE_MARGINING_REQUEST,
426 Mpi26ToolboxLaneMarginingRequest_t,
427 *pMpi2ToolboxLaneMarginingRequest_t;
428
429/* defines for the Command field */
430#define MPI26_TOOL_MARGIN_COMMAND_ENTER_MARGIN_MODE (0x01)
431#define MPI26_TOOL_MARGIN_COMMAND_READ_REGISTER_DATA (0x02)
432#define MPI26_TOOL_MARGIN_COMMAND_WRITE_REGISTER_DATA (0x03)
433#define MPI26_TOOL_MARGIN_COMMAND_EXIT_MARGIN_MODE (0x04)
434
435
436/*Toolbox Backend Lane Margining Tool reply message */
437typedef struct _MPI26_TOOLBOX_LANE_MARGINING_REPLY {
438 U8 Tool; /*0x00 */
439 U8 Reserved1; /*0x01 */
440 U8 MsgLength; /*0x02 */
441 U8 Function; /*0x03 */
442 U16 Reserved2; /*0x04 */
443 U8 Reserved3; /*0x06 */
444 U8 MsgFlags; /*0x07 */
445 U8 VP_ID; /*0x08 */
446 U8 VF_ID; /*0x09 */
447 U16 Reserved4; /*0x0A */
448 U16 Reserved5; /*0x0C */
449 U16 IOCStatus; /*0x0E */
450 U32 IOCLogInfo; /*0x10 */
451 U16 ReturnedDataLength; /*0x14 */
452 U16 Reserved6; /*0x16 */
453} MPI26_TOOLBOX_LANE_MARGINING_REPLY,
454 *PTR_MPI26_TOOLBOX_LANE_MARGINING_REPLY,
455 Mpi26ToolboxLaneMarginingReply_t,
456 *pMpi26ToolboxLaneMarginingReply_t;
457
390 458
391/***************************************************************************** 459/*****************************************************************************
392* 460*
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
index 8f1d6b071b39..3698776c3322 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
@@ -55,6 +55,7 @@
55#include "mpi/mpi2_tool.h" 55#include "mpi/mpi2_tool.h"
56#include "mpi/mpi2_sas.h" 56#include "mpi/mpi2_sas.h"
57#include "mpi/mpi2_pci.h" 57#include "mpi/mpi2_pci.h"
58#include "mpi/mpi2_image.h"
58 59
59#include <scsi/scsi.h> 60#include <scsi/scsi.h>
60#include <scsi/scsi_cmnd.h> 61#include <scsi/scsi_cmnd.h>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 20:37:03 -0400