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authorLinus Torvalds <torvalds@linux-foundation.org>2018-04-10 14:39:22 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2018-04-10 14:39:22 -0400
commit948869fa9f391664cfe008fa9968a1110bfd14fd (patch)
tree8cab813f6064d9bfa03fdfe6524277ca41e65305
parent2a56bb596b2c1fb612f9988afda9655c8c872a6e (diff)
parenta5075e6226c42a8e64ea1b862eec7747dc46cb32 (diff)
Merge tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips
Pull MIPS updates from James Hogan: "These are the main MIPS changes for 4.17. Rough overview: (1) generic platform: Add support for Microsemi Ocelot SoCs (2) crypto: Add CRC32 and CRC32C HW acceleration module (3) Various cleanups and misc improvements More detailed summary: Miscellaneous: - hang more efficiently on halt/powerdown/restart - pm-cps: Block system suspend when a JTAG probe is present - expand make help text for generic defconfigs - refactor handling of legacy defconfigs - determine the entry point from the ELF file header to fix microMIPS for certain toolchains - introduce isa-rev.h for MIPS_ISA_REV and use to simplify other code Minor cleanups: - DTS: boston/ci20: Unit name cleanups and correction - kdump: Make the default for PHYSICAL_START always 64-bit - constify gpio_led in Alchemy, AR7, and TXX9 - silence a couple of W=1 warnings - remove duplicate includes Platform support: Generic platform: - add support for Microsemi Ocelot - dt-bindings: Add vendor prefix for Microsemi Corporation - dt-bindings: Add bindings for Microsemi SoCs - add ocelot SoC & PCB123 board DTS files - MAINTAINERS: Add entry for Microsemi MIPS SoCs - enable crc32-mips on r6 configs ath79: - fix AR724X_PLL_REG_PCIE_CONFIG offset BCM47xx: - firmware: Use mac_pton() for MAC address parsing - add Luxul XAP1500/XWR1750 WiFi LEDs - use standard reset button for Luxul XWR-1750 BMIPS: - enable CONFIG_BRCMSTB_PM in bmips_stb_defconfig for build coverage - add STB PM, wake-up timer, watchdog DT nodes Octeon: - drop '.' after newlines in printk calls ralink: - pci-mt7621: Enable PCIe on MT7688" * tag 'mips_4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/jhogan/mips: (37 commits) MIPS: BCM47XX: Use standard reset button for Luxul XWR-1750 MIPS: BCM47XX: Add Luxul XAP1500/XWR1750 WiFi LEDs MIPS: Make the default for PHYSICAL_START always 64-bit MIPS: Use the entry point from the ELF file header MAINTAINERS: Add entry for Microsemi MIPS SoCs MIPS: generic: Add support for Microsemi Ocelot MIPS: mscc: Add ocelot PCB123 device tree MIPS: mscc: Add ocelot dtsi dt-bindings: mips: Add bindings for Microsemi SoCs dt-bindings: Add vendor prefix for Microsemi Corporation MIPS: ath79: Fix AR724X_PLL_REG_PCIE_CONFIG offset MIPS: pci-mt7620: Enable PCIe on MT7688 MIPS: pm-cps: Block system suspend when a JTAG probe is present MIPS: VDSO: Replace __mips_isa_rev with MIPS_ISA_REV MIPS: BPF: Replace __mips_isa_rev with MIPS_ISA_REV MIPS: cpu-features.h: Replace __mips_isa_rev with MIPS_ISA_REV MIPS: Introduce isa-rev.h to define MIPS_ISA_REV MIPS: Hang more efficiently on halt/powerdown/restart FIRMWARE: bcm47xx_nvram: Replace mac address parsing MIPS: BMIPS: Add Broadcom STB watchdog nodes ...
Diffstat
-rw-r--r--Documentation/devicetree/bindings/mips/mscc.txt43
-rw-r--r--Documentation/devicetree/bindings/vendor-prefixes.txt1
-rw-r--r--MAINTAINERS9
-rw-r--r--arch/mips/Kconfig7
-rw-r--r--arch/mips/Makefile64
-rw-r--r--arch/mips/alchemy/board-gpr.c2
-rw-r--r--arch/mips/alchemy/board-mtx1.c2
-rw-r--r--arch/mips/ar7/platform.c14
-rw-r--r--arch/mips/bcm47xx/buttons.c2
-rw-r--r--arch/mips/bcm47xx/leds.c21
-rw-r--r--arch/mips/boot/dts/Makefile1
-rw-r--r--arch/mips/boot/dts/brcm/bcm7125.dtsi7
-rw-r--r--arch/mips/boot/dts/brcm/bcm7346.dtsi62
-rw-r--r--arch/mips/boot/dts/brcm/bcm7358.dtsi17
-rw-r--r--arch/mips/boot/dts/brcm/bcm7360.dtsi62
-rw-r--r--arch/mips/boot/dts/brcm/bcm7362.dtsi62
-rw-r--r--arch/mips/boot/dts/brcm/bcm7420.dtsi7
-rw-r--r--arch/mips/boot/dts/brcm/bcm7425.dtsi89
-rw-r--r--arch/mips/boot/dts/brcm/bcm7435.dtsi89
-rw-r--r--arch/mips/boot/dts/brcm/bcm97125cbmb.dts4
-rw-r--r--arch/mips/boot/dts/brcm/bcm97346dbsmb.dts8
-rw-r--r--arch/mips/boot/dts/brcm/bcm97358svmb.dts8
-rw-r--r--arch/mips/boot/dts/brcm/bcm97360svmb.dts8
-rw-r--r--arch/mips/boot/dts/brcm/bcm97362svmb.dts8
-rw-r--r--arch/mips/boot/dts/brcm/bcm97420c.dts4
-rw-r--r--arch/mips/boot/dts/brcm/bcm97425svmb.dts8
-rw-r--r--arch/mips/boot/dts/brcm/bcm97435svmb.dts8
-rw-r--r--arch/mips/boot/dts/img/boston.dts2
-rw-r--r--arch/mips/boot/dts/ingenic/ci20.dts8
-rw-r--r--arch/mips/boot/dts/mscc/Makefile3
-rw-r--r--arch/mips/boot/dts/mscc/ocelot.dtsi117
-rw-r--r--arch/mips/boot/dts/mscc/ocelot_pcb123.dts27
-rw-r--r--arch/mips/cavium-octeon/octeon-irq.c10
-rw-r--r--arch/mips/configs/bmips_stb_defconfig1
-rw-r--r--arch/mips/configs/generic/32r6.config2
-rw-r--r--arch/mips/configs/generic/64r6.config2
-rw-r--r--arch/mips/configs/generic/board-ocelot.config35
-rw-r--r--arch/mips/crypto/Makefile6
-rw-r--r--arch/mips/crypto/crc32-mips.c348
-rw-r--r--arch/mips/generic/Kconfig16
-rw-r--r--arch/mips/generic/Makefile1
-rw-r--r--arch/mips/generic/board-ocelot.c78
-rw-r--r--arch/mips/include/asm/cpu-features.h5
-rw-r--r--arch/mips/include/asm/isa-rev.h24
-rw-r--r--arch/mips/include/asm/mach-ath79/ar71xx_regs.h2
-rw-r--r--arch/mips/include/asm/mipsregs.h1
-rw-r--r--arch/mips/include/uapi/asm/hwcap.h1
-rw-r--r--arch/mips/kernel/cpu-probe.c3
-rw-r--r--arch/mips/kernel/pm-cps.c31
-rw-r--r--arch/mips/kernel/reset.c68
-rw-r--r--arch/mips/kernel/setup.c5
-rw-r--r--arch/mips/mm/init.c2
-rw-r--r--arch/mips/net/bpf_jit_asm.S9
-rw-r--r--arch/mips/pci/pci-mt7620.c1
-rw-r--r--arch/mips/txx9/rbtx4927/setup.c2
-rw-r--r--arch/mips/vdso/elf.S10
-rw-r--r--crypto/Kconfig9
-rw-r--r--drivers/firmware/broadcom/Kconfig1
-rw-r--r--drivers/firmware/broadcom/bcm47xx_sprom.c18
59 files changed, 1381 insertions, 84 deletions
diff --git a/Documentation/devicetree/bindings/mips/mscc.txt b/Documentation/devicetree/bindings/mips/mscc.txt
new file mode 100644
index 000000000000..ae15ec333542
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/mscc.txt
@@ -0,0 +1,43 @@
1* Microsemi MIPS CPUs
2
3Boards with a SoC of the Microsemi MIPS family shall have the following
4properties:
5
6Required properties:
7- compatible: "mscc,ocelot"
8
9
10* Other peripherals:
11
12o CPU chip regs:
13
14The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
15functionalities: chip ID, general purpose register for software use, reset
16controller, hardware status and configuration, efuses.
17
18Required properties:
19- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
20- reg : Should contain registers location and length
21
22Example:
23 syscon@71070000 {
24 compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
25 reg = <0x71070000 0x1c>;
26 };
27
28
29o CPU system control:
30
31The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
32the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
33endianness, CPU bus control, CPU status.
34
35Required properties:
36- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
37- reg : Should contain registers location and length
38
39Example:
40 syscon@70000000 {
41 compatible = "mscc,ocelot-cpu-syscon", "syscon";
42 reg = <0x70000000 0x2c>;
43 };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 12e8b3e576b0..b5f978a4cac6 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -225,6 +225,7 @@ motorola Motorola, Inc.
225moxa Moxa Inc. 225moxa Moxa Inc.
226mpl MPL AG 226mpl MPL AG
227mqmaker mqmaker Inc. 227mqmaker mqmaker Inc.
228mscc Microsemi Corporation
228msi Micro-Star International Co. Ltd. 229msi Micro-Star International Co. Ltd.
229mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.) 230mti Imagination Technologies Ltd. (formerly MIPS Technologies Inc.)
230multi-inno Multi-Inno Technology Co.,Ltd 231multi-inno Multi-Inno Technology Co.,Ltd
diff --git a/MAINTAINERS b/MAINTAINERS
index 00855ffc8de9..b7bd40b6b80d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9230,6 +9230,15 @@ S: Maintained
9230F: drivers/usb/misc/usb251xb.c 9230F: drivers/usb/misc/usb251xb.c
9231F: Documentation/devicetree/bindings/usb/usb251xb.txt 9231F: Documentation/devicetree/bindings/usb/usb251xb.txt
9232 9232
9233MICROSEMI MIPS SOCS
9234M: Alexandre Belloni <alexandre.belloni@bootlin.com>
9235L: linux-mips@linux-mips.org
9236S: Maintained
9237F: arch/mips/generic/board-ocelot.c
9238F: arch/mips/configs/generic/board-ocelot.config
9239F: arch/mips/boot/dts/mscc/
9240F: Documentation/devicetree/bindings/mips/mscc.txt
9241
9233MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi) 9242MICROSEMI SMART ARRAY SMARTPQI DRIVER (smartpqi)
9234M: Don Brace <don.brace@microsemi.com> 9243M: Don Brace <don.brace@microsemi.com>
9235L: esc.storagedev@microsemi.com 9244L: esc.storagedev@microsemi.com
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 61e9a24297b7..225c95da23ce 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -2029,6 +2029,7 @@ config CPU_MIPSR6
2029 select CPU_HAS_RIXI 2029 select CPU_HAS_RIXI
2030 select HAVE_ARCH_BITREVERSE 2030 select HAVE_ARCH_BITREVERSE
2031 select MIPS_ASID_BITS_VARIABLE 2031 select MIPS_ASID_BITS_VARIABLE
2032 select MIPS_CRC_SUPPORT
2032 select MIPS_SPRAM 2033 select MIPS_SPRAM
2033 2034
2034config EVA 2035config EVA
@@ -2502,6 +2503,9 @@ config MIPS_ASID_BITS
2502config MIPS_ASID_BITS_VARIABLE 2503config MIPS_ASID_BITS_VARIABLE
2503 bool 2504 bool
2504 2505
2506config MIPS_CRC_SUPPORT
2507 bool
2508
2505# 2509#
2506# - Highmem only makes sense for the 32-bit kernel. 2510# - Highmem only makes sense for the 32-bit kernel.
2507# - The current highmem code will only work properly on physically indexed 2511# - The current highmem code will only work properly on physically indexed
@@ -2850,8 +2854,7 @@ config CRASH_DUMP
2850 2854
2851config PHYSICAL_START 2855config PHYSICAL_START
2852 hex "Physical address where the kernel is loaded" 2856 hex "Physical address where the kernel is loaded"
2853 default "0xffffffff84000000" if 64BIT 2857 default "0xffffffff84000000"
2854 default "0x84000000" if 32BIT
2855 depends on CRASH_DUMP 2858 depends on CRASH_DUMP
2856 help 2859 help
2857 This gives the CKSEG0 or KSEG0 address where the kernel is loaded. 2860 This gives the CKSEG0 or KSEG0 address where the kernel is loaded.
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index d1ca839c3981..5e9fce076ab6 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -222,6 +222,8 @@ xpa-cflags-y := $(mips-cflags)
222xpa-cflags-$(micromips-ase) += -mmicromips -Wa$(comma)-fatal-warnings 222xpa-cflags-$(micromips-ase) += -mmicromips -Wa$(comma)-fatal-warnings
223toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa) 223toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa)
224cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA 224cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA
225toolchain-crc := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc)
226cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC
225 227
226# 228#
227# Firmware support 229# Firmware support
@@ -249,20 +251,12 @@ ifdef CONFIG_PHYSICAL_START
249load-y = $(CONFIG_PHYSICAL_START) 251load-y = $(CONFIG_PHYSICAL_START)
250endif 252endif
251 253
252entry-noisa-y = 0x$(shell $(NM) vmlinux 2>/dev/null \ 254# Sign-extend the entry point to 64 bits if retrieved as a 32-bit number.
253 | grep "\bkernel_entry\b" | cut -f1 -d \ ) 255entry-y = $(shell $(OBJDUMP) -f vmlinux 2>/dev/null \
254ifdef CONFIG_CPU_MICROMIPS 256 | sed -n '/^start address / { \
255 # 257 s/^.* //; \
256 # Set the ISA bit, since the kernel_entry symbol in the ELF will have it 258 s/0x\([0-7].......\)$$/0x00000000\1/; \
257 # clear which would lead to images containing addresses which bootloaders may 259 s/0x\(........\)$$/0xffffffff\1/; p }')
258 # jump to as MIPS32 code.
259 #
260 entry-y = $(patsubst %0,%1,$(patsubst %2,%3,$(patsubst %4,%5, \
261 $(patsubst %6,%7,$(patsubst %8,%9,$(patsubst %a,%b, \
262 $(patsubst %c,%d,$(patsubst %e,%f,$(entry-noisa-y)))))))))
263else
264 entry-y = $(entry-noisa-y)
265endif
266 260
267cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic 261cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic
268drivers-$(CONFIG_PCI) += arch/mips/pci/ 262drivers-$(CONFIG_PCI) += arch/mips/pci/
@@ -330,6 +324,7 @@ libs-y += arch/mips/math-emu/
330# See arch/mips/Kbuild for content of core part of the kernel 324# See arch/mips/Kbuild for content of core part of the kernel
331core-y += arch/mips/ 325core-y += arch/mips/
332 326
327drivers-$(CONFIG_MIPS_CRC_SUPPORT) += arch/mips/crypto/
333drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ 328drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/
334 329
335# suspend and hibernation support 330# suspend and hibernation support
@@ -473,6 +468,21 @@ define archhelp
473 echo 468 echo
474 echo ' {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">' 469 echo ' {micro32,32,64}{r1,r2,r6}{el,}_defconfig <BOARDS="list of boards">'
475 echo 470 echo
471 echo ' Where BOARDS is some subset of the following:'
472 for board in $(sort $(BOARDS)); do echo " $${board}"; done
473 echo
474 echo ' Specifically the following generic default configurations are'
475 echo ' supported:'
476 echo
477 $(foreach cfg,$(generic_defconfigs),
478 printf " %-24s - Build generic kernel for $(call describe_generic_defconfig,$(cfg))\n" $(cfg);)
479 echo
480 echo ' The following legacy default configurations have been converted to'
481 echo ' generic and can still be used:'
482 echo
483 $(foreach cfg,$(sort $(legacy_defconfigs)),
484 printf " %-24s - Build $($(cfg)-y)\n" $(cfg);)
485 echo
476 echo ' Otherwise, the following default configurations are available:' 486 echo ' Otherwise, the following default configurations are available:'
477endef 487endef
478 488
@@ -507,6 +517,10 @@ endef
507$(eval $(call gen_generic_defconfigs,32 64,r1 r2 r6,eb el)) 517$(eval $(call gen_generic_defconfigs,32 64,r1 r2 r6,eb el))
508$(eval $(call gen_generic_defconfigs,micro32,r2,eb el)) 518$(eval $(call gen_generic_defconfigs,micro32,r2,eb el))
509 519
520define describe_generic_defconfig
521$(subst 32r,MIPS32 r,$(subst 64r,MIPS64 r,$(subst el, little endian,$(patsubst %_defconfig,%,$(1)))))
522endef
523
510.PHONY: $(generic_defconfigs) 524.PHONY: $(generic_defconfigs)
511$(generic_defconfigs): 525$(generic_defconfigs):
512 $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \ 526 $(Q)$(CONFIG_SHELL) $(srctree)/scripts/kconfig/merge_config.sh \
@@ -543,14 +557,18 @@ generic_defconfig:
543# now that the boards have been converted to use the generic kernel they are 557# now that the boards have been converted to use the generic kernel they are
544# wrappers around the generic rules above. 558# wrappers around the generic rules above.
545# 559#
546.PHONY: sead3_defconfig 560legacy_defconfigs += ocelot_defconfig
547sead3_defconfig: 561ocelot_defconfig-y := 32r2el_defconfig BOARDS=ocelot
548 $(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=sead-3 562
563legacy_defconfigs += sead3_defconfig
564sead3_defconfig-y := 32r2el_defconfig BOARDS=sead-3
565
566legacy_defconfigs += sead3micro_defconfig
567sead3micro_defconfig-y := micro32r2el_defconfig BOARDS=sead-3
549 568
550.PHONY: sead3micro_defconfig 569legacy_defconfigs += xilfpga_defconfig
551sead3micro_defconfig: 570xilfpga_defconfig-y := 32r2el_defconfig BOARDS=xilfpga
552 $(Q)$(MAKE) -f $(srctree)/Makefile micro32r2el_defconfig BOARDS=sead-3
553 571
554.PHONY: xilfpga_defconfig 572.PHONY: $(legacy_defconfigs)
555xilfpga_defconfig: 573$(legacy_defconfigs):
556 $(Q)$(MAKE) -f $(srctree)/Makefile 32r2el_defconfig BOARDS=xilfpga 574 $(Q)$(MAKE) -f $(srctree)/Makefile $($@-y)
diff --git a/arch/mips/alchemy/board-gpr.c b/arch/mips/alchemy/board-gpr.c
index 328d697e72b4..4e79dbd54a33 100644
--- a/arch/mips/alchemy/board-gpr.c
+++ b/arch/mips/alchemy/board-gpr.c
@@ -190,7 +190,7 @@ static struct platform_device gpr_mtd_device = {
190/* 190/*
191 * LEDs 191 * LEDs
192 */ 192 */
193static struct gpio_led gpr_gpio_leds[] = { 193static const struct gpio_led gpr_gpio_leds[] = {
194 { /* green */ 194 { /* green */
195 .name = "gpr:green", 195 .name = "gpr:green",
196 .gpio = 4, 196 .gpio = 4,
diff --git a/arch/mips/alchemy/board-mtx1.c b/arch/mips/alchemy/board-mtx1.c
index 85bb75669b0d..aab55aaf3d62 100644
--- a/arch/mips/alchemy/board-mtx1.c
+++ b/arch/mips/alchemy/board-mtx1.c
@@ -145,7 +145,7 @@ static struct platform_device mtx1_wdt = {
145 .resource = mtx1_wdt_res, 145 .resource = mtx1_wdt_res,
146}; 146};
147 147
148static struct gpio_led default_leds[] = { 148static const struct gpio_led default_leds[] = {
149 { 149 {
150 .name = "mtx1:green", 150 .name = "mtx1:green",
151 .gpio = 211, 151 .gpio = 211,
diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c
index e1675c25d5d4..f09262e0a72f 100644
--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -346,7 +346,7 @@ static struct platform_device ar7_udc = {
346/***************************************************************************** 346/*****************************************************************************
347 * LEDs 347 * LEDs
348 ****************************************************************************/ 348 ****************************************************************************/
349static struct gpio_led default_leds[] = { 349static const struct gpio_led default_leds[] = {
350 { 350 {
351 .name = "status", 351 .name = "status",
352 .gpio = 8, 352 .gpio = 8,
@@ -354,12 +354,12 @@ static struct gpio_led default_leds[] = {
354 }, 354 },
355}; 355};
356 356
357static struct gpio_led titan_leds[] = { 357static const struct gpio_led titan_leds[] = {
358 { .name = "status", .gpio = 8, .active_low = 1, }, 358 { .name = "status", .gpio = 8, .active_low = 1, },
359 { .name = "wifi", .gpio = 13, .active_low = 1, }, 359 { .name = "wifi", .gpio = 13, .active_low = 1, },
360}; 360};
361 361
362static struct gpio_led dsl502t_leds[] = { 362static const struct gpio_led dsl502t_leds[] = {
363 { 363 {
364 .name = "status", 364 .name = "status",
365 .gpio = 9, 365 .gpio = 9,
@@ -377,7 +377,7 @@ static struct gpio_led dsl502t_leds[] = {
377 }, 377 },
378}; 378};
379 379
380static struct gpio_led dg834g_leds[] = { 380static const struct gpio_led dg834g_leds[] = {
381 { 381 {
382 .name = "ppp", 382 .name = "ppp",
383 .gpio = 6, 383 .gpio = 6,
@@ -406,7 +406,7 @@ static struct gpio_led dg834g_leds[] = {
406 }, 406 },
407}; 407};
408 408
409static struct gpio_led fb_sl_leds[] = { 409static const struct gpio_led fb_sl_leds[] = {
410 { 410 {
411 .name = "1", 411 .name = "1",
412 .gpio = 7, 412 .gpio = 7,
@@ -433,7 +433,7 @@ static struct gpio_led fb_sl_leds[] = {
433 }, 433 },
434}; 434};
435 435
436static struct gpio_led fb_fon_leds[] = { 436static const struct gpio_led fb_fon_leds[] = {
437 { 437 {
438 .name = "1", 438 .name = "1",
439 .gpio = 8, 439 .gpio = 8,
@@ -459,7 +459,7 @@ static struct gpio_led fb_fon_leds[] = {
459 }, 459 },
460}; 460};
461 461
462static struct gpio_led gt701_leds[] = { 462static const struct gpio_led gt701_leds[] = {
463 { 463 {
464 .name = "inet:green", 464 .name = "inet:green",
465 .gpio = 13, 465 .gpio = 13,
diff --git a/arch/mips/bcm47xx/buttons.c b/arch/mips/bcm47xx/buttons.c
index 88a8fb2bbc71..88d400d256c4 100644
--- a/arch/mips/bcm47xx/buttons.c
+++ b/arch/mips/bcm47xx/buttons.c
@@ -355,7 +355,7 @@ bcm47xx_buttons_luxul_xwr_600_v1[] = {
355 355
356static const struct gpio_keys_button 356static const struct gpio_keys_button
357bcm47xx_buttons_luxul_xwr_1750_v1[] = { 357bcm47xx_buttons_luxul_xwr_1750_v1[] = {
358 BCM47XX_GPIO_KEY(14, BTN_TASK), 358 BCM47XX_GPIO_KEY(14, KEY_RESTART),
359}; 359};
360 360
361/* Microsoft */ 361/* Microsoft */
diff --git a/arch/mips/bcm47xx/leds.c b/arch/mips/bcm47xx/leds.c
index 8307a8a02667..34a7b3fbdfd9 100644
--- a/arch/mips/bcm47xx/leds.c
+++ b/arch/mips/bcm47xx/leds.c
@@ -409,6 +409,12 @@ bcm47xx_leds_luxul_xap_1500_v1[] __initconst = {
409}; 409};
410 410
411static const struct gpio_led 411static const struct gpio_led
412bcm47xx_leds_luxul_xap1500_v1_extra[] __initconst = {
413 BCM47XX_GPIO_LED(44, "green", "5ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
414 BCM47XX_GPIO_LED(76, "green", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
415};
416
417static const struct gpio_led
412bcm47xx_leds_luxul_xbr_4400_v1[] __initconst = { 418bcm47xx_leds_luxul_xbr_4400_v1[] __initconst = {
413 BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF), 419 BCM47XX_GPIO_LED(12, "green", "usb", 0, LEDS_GPIO_DEFSTATE_OFF),
414 BCM47XX_GPIO_LED_TRIGGER(15, "green", "status", 0, "timer"), 420 BCM47XX_GPIO_LED_TRIGGER(15, "green", "status", 0, "timer"),
@@ -435,6 +441,11 @@ bcm47xx_leds_luxul_xwr_1750_v1[] __initconst = {
435 BCM47XX_GPIO_LED(15, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF), 441 BCM47XX_GPIO_LED(15, "green", "wps", 0, LEDS_GPIO_DEFSTATE_OFF),
436}; 442};
437 443
444static const struct gpio_led
445bcm47xx_leds_luxul_xwr1750_v1_extra[] __initconst = {
446 BCM47XX_GPIO_LED(76, "green", "2ghz", 0, LEDS_GPIO_DEFSTATE_OFF),
447};
448
438/* Microsoft */ 449/* Microsoft */
439 450
440static const struct gpio_led 451static const struct gpio_led
@@ -528,6 +539,12 @@ static struct gpio_led_platform_data bcm47xx_leds_pdata;
528 bcm47xx_leds_pdata.num_leds = ARRAY_SIZE(dev_leds); \ 539 bcm47xx_leds_pdata.num_leds = ARRAY_SIZE(dev_leds); \
529} while (0) 540} while (0)
530 541
542static struct gpio_led_platform_data bcm47xx_leds_pdata_extra __initdata = {};
543#define bcm47xx_set_pdata_extra(dev_leds) do { \
544 bcm47xx_leds_pdata_extra.leds = dev_leds; \
545 bcm47xx_leds_pdata_extra.num_leds = ARRAY_SIZE(dev_leds); \
546} while (0)
547
531void __init bcm47xx_leds_register(void) 548void __init bcm47xx_leds_register(void)
532{ 549{
533 enum bcm47xx_board board = bcm47xx_board_get(); 550 enum bcm47xx_board board = bcm47xx_board_get();
@@ -705,6 +722,7 @@ void __init bcm47xx_leds_register(void)
705 break; 722 break;
706 case BCM47XX_BOARD_LUXUL_XAP_1500_V1: 723 case BCM47XX_BOARD_LUXUL_XAP_1500_V1:
707 bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1500_v1); 724 bcm47xx_set_pdata(bcm47xx_leds_luxul_xap_1500_v1);
725 bcm47xx_set_pdata_extra(bcm47xx_leds_luxul_xap1500_v1_extra);
708 break; 726 break;
709 case BCM47XX_BOARD_LUXUL_XBR_4400_V1: 727 case BCM47XX_BOARD_LUXUL_XBR_4400_V1:
710 bcm47xx_set_pdata(bcm47xx_leds_luxul_xbr_4400_v1); 728 bcm47xx_set_pdata(bcm47xx_leds_luxul_xbr_4400_v1);
@@ -717,6 +735,7 @@ void __init bcm47xx_leds_register(void)
717 break; 735 break;
718 case BCM47XX_BOARD_LUXUL_XWR_1750_V1: 736 case BCM47XX_BOARD_LUXUL_XWR_1750_V1:
719 bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1); 737 bcm47xx_set_pdata(bcm47xx_leds_luxul_xwr_1750_v1);
738 bcm47xx_set_pdata_extra(bcm47xx_leds_luxul_xwr1750_v1_extra);
720 break; 739 break;
721 740
722 case BCM47XX_BOARD_MICROSOFT_MN700: 741 case BCM47XX_BOARD_MICROSOFT_MN700:
@@ -760,4 +779,6 @@ void __init bcm47xx_leds_register(void)
760 } 779 }
761 780
762 gpio_led_register_device(-1, &bcm47xx_leds_pdata); 781 gpio_led_register_device(-1, &bcm47xx_leds_pdata);
782 if (bcm47xx_leds_pdata_extra.num_leds)
783 gpio_led_register_device(0, &bcm47xx_leds_pdata_extra);
763} 784}
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index e2c6f131c8eb..1e79cab8e269 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
4subdir-y += img 4subdir-y += img
5subdir-y += ingenic 5subdir-y += ingenic
6subdir-y += lantiq 6subdir-y += lantiq
7subdir-y += mscc
7subdir-y += mti 8subdir-y += mti
8subdir-y += netlogic 9subdir-y += netlogic
9subdir-y += ni 10subdir-y += ni
diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
index 2f9ef565e5d0..5bf77b6fcceb 100644
--- a/arch/mips/boot/dts/brcm/bcm7125.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
@@ -198,6 +198,13 @@
198 status = "disabled"; 198 status = "disabled";
199 }; 199 };
200 200
201 watchdog: watchdog@4067e8 {
202 clocks = <&upg_clk>;
203 compatible = "brcm,bcm7038-wdt";
204 reg = <0x4067e8 0x14>;
205 status = "disabled";
206 };
207
201 upg_gio: gpio@406700 { 208 upg_gio: gpio@406700 {
202 compatible = "brcm,brcmstb-gpio"; 209 compatible = "brcm,brcmstb-gpio";
203 reg = <0x406700 0x80>; 210 reg = <0x406700 0x80>;
diff --git a/arch/mips/boot/dts/brcm/bcm7346.dtsi b/arch/mips/boot/dts/brcm/bcm7346.dtsi
index 02e426fe6013..2afa0dada575 100644
--- a/arch/mips/boot/dts/brcm/bcm7346.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7346.dtsi
@@ -233,6 +233,13 @@
233 status = "disabled"; 233 status = "disabled";
234 }; 234 };
235 235
236 watchdog: watchdog@4067e8 {
237 clocks = <&upg_clk>;
238 compatible = "brcm,bcm7038-wdt";
239 reg = <0x4067e8 0x14>;
240 status = "disabled";
241 };
242
236 aon_pm_l2_intc: interrupt-controller@408440 { 243 aon_pm_l2_intc: interrupt-controller@408440 {
237 compatible = "brcm,l2-intc"; 244 compatible = "brcm,l2-intc";
238 reg = <0x408440 0x30>; 245 reg = <0x408440 0x30>;
@@ -243,6 +250,17 @@
243 brcm,irq-can-wake; 250 brcm,irq-can-wake;
244 }; 251 };
245 252
253 aon_ctrl: syscon@408000 {
254 compatible = "brcm,brcmstb-aon-ctrl";
255 reg = <0x408000 0x100>, <0x408200 0x200>;
256 reg-names = "aon-ctrl", "aon-sram";
257 };
258
259 timers: timer@4067c0 {
260 compatible = "brcm,brcmstb-timers";
261 reg = <0x4067c0 0x40>;
262 };
263
246 upg_gio: gpio@406700 { 264 upg_gio: gpio@406700 {
247 compatible = "brcm,brcmstb-gpio"; 265 compatible = "brcm,brcmstb-gpio";
248 reg = <0x406700 0x60>; 266 reg = <0x406700 0x60>;
@@ -483,5 +501,49 @@
483 interrupt-names = "mspi_done"; 501 interrupt-names = "mspi_done";
484 status = "disabled"; 502 status = "disabled";
485 }; 503 };
504
505 waketimer: waketimer@408e80 {
506 compatible = "brcm,brcmstb-waketimer";
507 reg = <0x408e80 0x14>;
508 interrupts = <0x3>;
509 interrupt-parent = <&aon_pm_l2_intc>;
510 interrupt-names = "timer";
511 clocks = <&upg_clk>;
512 status = "disabled";
513 };
514 };
515
516 memory_controllers {
517 compatible = "simple-bus";
518 ranges = <0x0 0x103b0000 0xa000>;
519 #address-cells = <1>;
520 #size-cells = <1>;
521
522 memory-controller@0 {
523 compatible = "brcm,brcmstb-memc", "simple-bus";
524 ranges = <0x0 0x0 0xa000>;
525 #address-cells = <1>;
526 #size-cells = <1>;
527
528 memc-arb@1000 {
529 compatible = "brcm,brcmstb-memc-arb";
530 reg = <0x1000 0x248>;
531 };
532
533 memc-ddr@2000 {
534 compatible = "brcm,brcmstb-memc-ddr";
535 reg = <0x2000 0x300>;
536 };
537
538 ddr-phy@6000 {
539 compatible = "brcm,brcmstb-ddr-phy";
540 reg = <0x6000 0xc8>;
541 };
542
543 shimphy@8000 {
544 compatible = "brcm,brcmstb-ddr-shimphy";
545 reg = <0x8000 0x13c>;
546 };
547 };
486 }; 548 };
487}; 549};
diff --git a/arch/mips/boot/dts/brcm/bcm7358.dtsi b/arch/mips/boot/dts/brcm/bcm7358.dtsi
index 1089d6ebc841..6375fc77f389 100644
--- a/arch/mips/boot/dts/brcm/bcm7358.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7358.dtsi
@@ -217,6 +217,13 @@
217 status = "disabled"; 217 status = "disabled";
218 }; 218 };
219 219
220 watchdog: watchdog@4066a8 {
221 clocks = <&upg_clk>;
222 compatible = "brcm,bcm7038-wdt";
223 reg = <0x4066a8 0x14>;
224 status = "disabled";
225 };
226
220 aon_pm_l2_intc: interrupt-controller@408240 { 227 aon_pm_l2_intc: interrupt-controller@408240 {
221 compatible = "brcm,l2-intc"; 228 compatible = "brcm,l2-intc";
222 reg = <0x408240 0x30>; 229 reg = <0x408240 0x30>;
@@ -362,5 +369,15 @@
362 interrupt-names = "mspi_done"; 369 interrupt-names = "mspi_done";
363 status = "disabled"; 370 status = "disabled";
364 }; 371 };
372
373 waketimer: waketimer@408e80 {
374 compatible = "brcm,brcmstb-waketimer";
375 reg = <0x408e80 0x14>;
376 interrupts = <0x3>;
377 interrupt-parent = <&aon_pm_l2_intc>;
378 interrupt-names = "timer";
379 clocks = <&upg_clk>;
380 status = "disabled";
381 };
365 }; 382 };
366}; 383};
diff --git a/arch/mips/boot/dts/brcm/bcm7360.dtsi b/arch/mips/boot/dts/brcm/bcm7360.dtsi
index 4b87ebec407a..a57cacea91cf 100644
--- a/arch/mips/boot/dts/brcm/bcm7360.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7360.dtsi
@@ -209,6 +209,13 @@
209 status = "disabled"; 209 status = "disabled";
210 }; 210 };
211 211
212 watchdog: watchdog@4066a8 {
213 clocks = <&upg_clk>;
214 compatible = "brcm,bcm7038-wdt";
215 reg = <0x4066a8 0x14>;
216 status = "disabled";
217 };
218
212 aon_pm_l2_intc: interrupt-controller@408440 { 219 aon_pm_l2_intc: interrupt-controller@408440 {
213 compatible = "brcm,l2-intc"; 220 compatible = "brcm,l2-intc";
214 reg = <0x408440 0x30>; 221 reg = <0x408440 0x30>;
@@ -219,6 +226,17 @@
219 brcm,irq-can-wake; 226 brcm,irq-can-wake;
220 }; 227 };
221 228
229 aon_ctrl: syscon@408000 {
230 compatible = "brcm,brcmstb-aon-ctrl";
231 reg = <0x408000 0x100>, <0x408200 0x200>;
232 reg-names = "aon-ctrl", "aon-sram";
233 };
234
235 timers: timer@406680 {
236 compatible = "brcm,brcmstb-timers";
237 reg = <0x406680 0x40>;
238 };
239
222 upg_gio: gpio@406500 { 240 upg_gio: gpio@406500 {
223 compatible = "brcm,brcmstb-gpio"; 241 compatible = "brcm,brcmstb-gpio";
224 reg = <0x406500 0xa0>; 242 reg = <0x406500 0xa0>;
@@ -402,5 +420,49 @@
402 interrupt-names = "mspi_done"; 420 interrupt-names = "mspi_done";
403 status = "disabled"; 421 status = "disabled";
404 }; 422 };
423
424 waketimer: waketimer@408e80 {
425 compatible = "brcm,brcmstb-waketimer";
426 reg = <0x408e80 0x14>;
427 interrupts = <0x3>;
428 interrupt-parent = <&aon_pm_l2_intc>;
429 interrupt-names = "timer";
430 clocks = <&upg_clk>;
431 status = "disabled";
432 };
433 };
434
435 memory_controllers {
436 compatible = "simple-bus";
437 ranges = <0x0 0x103b0000 0xa000>;
438 #address-cells = <1>;
439 #size-cells = <1>;
440
441 memory-controller@0 {
442 compatible = "brcm,brcmstb-memc", "simple-bus";
443 ranges = <0x0 0x0 0xa000>;
444 #address-cells = <1>;
445 #size-cells = <1>;
446
447 memc-arb@1000 {
448 compatible = "brcm,brcmstb-memc-arb";
449 reg = <0x1000 0x248>;
450 };
451
452 memc-ddr@2000 {
453 compatible = "brcm,brcmstb-memc-ddr";
454 reg = <0x2000 0x300>;
455 };
456
457 ddr-phy@6000 {
458 compatible = "brcm,brcmstb-ddr-phy";
459 reg = <0x6000 0xc8>;
460 };
461
462 shimphy@8000 {
463 compatible = "brcm,brcmstb-ddr-shimphy";
464 reg = <0x8000 0x13c>;
465 };
466 };
405 }; 467 };
406}; 468};
diff --git a/arch/mips/boot/dts/brcm/bcm7362.dtsi b/arch/mips/boot/dts/brcm/bcm7362.dtsi
index ca657df34b6d..728b9e9f84b8 100644
--- a/arch/mips/boot/dts/brcm/bcm7362.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7362.dtsi
@@ -205,6 +205,13 @@
205 status = "disabled"; 205 status = "disabled";
206 }; 206 };
207 207
208 watchdog: watchdog@4066a8 {
209 clocks = <&upg_clk>;
210 compatible = "brcm,bcm7038-wdt";
211 reg = <0x4066a8 0x14>;
212 status = "disabled";
213 };
214
208 aon_pm_l2_intc: interrupt-controller@408440 { 215 aon_pm_l2_intc: interrupt-controller@408440 {
209 compatible = "brcm,l2-intc"; 216 compatible = "brcm,l2-intc";
210 reg = <0x408440 0x30>; 217 reg = <0x408440 0x30>;
@@ -215,6 +222,17 @@
215 brcm,irq-can-wake; 222 brcm,irq-can-wake;
216 }; 223 };
217 224
225 aon_ctrl: syscon@408000 {
226 compatible = "brcm,brcmstb-aon-ctrl";
227 reg = <0x408000 0x100>, <0x408200 0x200>;
228 reg-names = "aon-ctrl", "aon-sram";
229 };
230
231 timers: timer@406680 {
232 compatible = "brcm,brcmstb-timers";
233 reg = <0x406680 0x40>;
234 };
235
218 upg_gio: gpio@406500 { 236 upg_gio: gpio@406500 {
219 compatible = "brcm,brcmstb-gpio"; 237 compatible = "brcm,brcmstb-gpio";
220 reg = <0x406500 0xa0>; 238 reg = <0x406500 0xa0>;
@@ -398,5 +416,49 @@
398 interrupt-names = "mspi_done"; 416 interrupt-names = "mspi_done";
399 status = "disabled"; 417 status = "disabled";
400 }; 418 };
419
420 waketimer: waketimer@408e80 {
421 compatible = "brcm,brcmstb-waketimer";
422 reg = <0x408e80 0x14>;
423 interrupts = <0x3>;
424 interrupt-parent = <&aon_pm_l2_intc>;
425 interrupt-names = "timer";
426 clocks = <&upg_clk>;
427 status = "disabled";
428 };
429 };
430
431 memory_controllers {
432 compatible = "simple-bus";
433 ranges = <0x0 0x103b0000 0xa000>;
434 #address-cells = <1>;
435 #size-cells = <1>;
436
437 memory-controller@0 {
438 compatible = "brcm,brcmstb-memc", "simple-bus";
439 ranges = <0x0 0x0 0xa000>;
440 #address-cells = <1>;
441 #size-cells = <1>;
442
443 memc-arb@1000 {
444 compatible = "brcm,brcmstb-memc-arb";
445 reg = <0x1000 0x248>;
446 };
447
448 memc-ddr@2000 {
449 compatible = "brcm,brcmstb-memc-ddr";
450 reg = <0x2000 0x300>;
451 };
452
453 ddr-phy@6000 {
454 compatible = "brcm,brcmstb-ddr-phy";
455 reg = <0x6000 0xc8>;
456 };
457
458 shimphy@8000 {
459 compatible = "brcm,brcmstb-ddr-shimphy";
460 reg = <0x8000 0x13c>;
461 };
462 };
401 }; 463 };
402}; 464};
diff --git a/arch/mips/boot/dts/brcm/bcm7420.dtsi b/arch/mips/boot/dts/brcm/bcm7420.dtsi
index d262e11bc3f9..9540c27f12e7 100644
--- a/arch/mips/boot/dts/brcm/bcm7420.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7420.dtsi
@@ -214,6 +214,13 @@
214 status = "disabled"; 214 status = "disabled";
215 }; 215 };
216 216
217 watchdog: watchdog@4067e8 {
218 clocks = <&upg_clk>;
219 compatible = "brcm,bcm7038-wdt";
220 reg = <0x4067e8 0x14>;
221 status = "disabled";
222 };
223
217 upg_gio: gpio@406700 { 224 upg_gio: gpio@406700 {
218 compatible = "brcm,brcmstb-gpio"; 225 compatible = "brcm,brcmstb-gpio";
219 reg = <0x406700 0x80>; 226 reg = <0x406700 0x80>;
diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi b/arch/mips/boot/dts/brcm/bcm7425.dtsi
index e4fb9b6e6dce..410e61ebaf9e 100644
--- a/arch/mips/boot/dts/brcm/bcm7425.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi
@@ -232,6 +232,13 @@
232 status = "disabled"; 232 status = "disabled";
233 }; 233 };
234 234
235 watchdog: watchdog@4067e8 {
236 clocks = <&upg_clk>;
237 compatible = "brcm,bcm7038-wdt";
238 reg = <0x4067e8 0x14>;
239 status = "disabled";
240 };
241
235 aon_pm_l2_intc: interrupt-controller@408440 { 242 aon_pm_l2_intc: interrupt-controller@408440 {
236 compatible = "brcm,l2-intc"; 243 compatible = "brcm,l2-intc";
237 reg = <0x408440 0x30>; 244 reg = <0x408440 0x30>;
@@ -242,6 +249,17 @@
242 brcm,irq-can-wake; 249 brcm,irq-can-wake;
243 }; 250 };
244 251
252 aon_ctrl: syscon@408000 {
253 compatible = "brcm,brcmstb-aon-ctrl";
254 reg = <0x408000 0x100>, <0x408200 0x200>;
255 reg-names = "aon-ctrl", "aon-sram";
256 };
257
258 timers: timer@4067c0 {
259 compatible = "brcm,brcmstb-timers";
260 reg = <0x4067c0 0x40>;
261 };
262
245 upg_gio: gpio@406700 { 263 upg_gio: gpio@406700 {
246 compatible = "brcm,brcmstb-gpio"; 264 compatible = "brcm,brcmstb-gpio";
247 reg = <0x406700 0x80>; 265 reg = <0x406700 0x80>;
@@ -494,5 +512,76 @@
494 interrupt-names = "mspi_done"; 512 interrupt-names = "mspi_done";
495 status = "disabled"; 513 status = "disabled";
496 }; 514 };
515
516 waketimer: waketimer@409580 {
517 compatible = "brcm,brcmstb-waketimer";
518 reg = <0x409580 0x14>;
519 interrupts = <0x3>;
520 interrupt-parent = <&aon_pm_l2_intc>;
521 interrupt-names = "timer";
522 clocks = <&upg_clk>;
523 status = "disabled";
524 };
525 };
526
527 memory_controllers {
528 compatible = "simple-bus";
529 ranges = <0x0 0x103b0000 0x1a000>;
530 #address-cells = <1>;
531 #size-cells = <1>;
532
533 memory-controller@0 {
534 compatible = "brcm,brcmstb-memc", "simple-bus";
535 ranges = <0x0 0x0 0xa000>;
536 #address-cells = <1>;
537 #size-cells = <1>;
538
539 memc-arb@1000 {
540 compatible = "brcm,brcmstb-memc-arb";
541 reg = <0x1000 0x248>;
542 };
543
544 memc-ddr@2000 {
545 compatible = "brcm,brcmstb-memc-ddr";
546 reg = <0x2000 0x300>;
547 };
548
549 ddr-phy@6000 {
550 compatible = "brcm,brcmstb-ddr-phy";
551 reg = <0x6000 0xc8>;
552 };
553
554 shimphy@8000 {
555 compatible = "brcm,brcmstb-ddr-shimphy";
556 reg = <0x8000 0x13c>;
557 };
558 };
559
560 memory-controller@1 {
561 compatible = "brcm,brcmstb-memc", "simple-bus";
562 ranges = <0x0 0x10000 0xa000>;
563 #address-cells = <1>;
564 #size-cells = <1>;
565
566 memc-arb@1000 {
567 compatible = "brcm,brcmstb-memc-arb";
568 reg = <0x1000 0x248>;
569 };
570
571 memc-ddr@2000 {
572 compatible = "brcm,brcmstb-memc-ddr";
573 reg = <0x2000 0x300>;
574 };
575
576 ddr-phy@6000 {
577 compatible = "brcm,brcmstb-ddr-phy";
578 reg = <0x6000 0xc8>;
579 };
580
581 shimphy@8000 {
582 compatible = "brcm,brcmstb-ddr-shimphy";
583 reg = <0x8000 0x13c>;
584 };
585 };
497 }; 586 };
498}; 587};
diff --git a/arch/mips/boot/dts/brcm/bcm7435.dtsi b/arch/mips/boot/dts/brcm/bcm7435.dtsi
index 1484e8990e52..8398b7f68bf4 100644
--- a/arch/mips/boot/dts/brcm/bcm7435.dtsi
+++ b/arch/mips/boot/dts/brcm/bcm7435.dtsi
@@ -247,6 +247,13 @@
247 status = "disabled"; 247 status = "disabled";
248 }; 248 };
249 249
250 watchdog: watchdog@4067e8 {
251 clocks = <&upg_clk>;
252 compatible = "brcm,bcm7038-wdt";
253 reg = <0x4067e8 0x14>;
254 status = "disabled";
255 };
256
250 aon_pm_l2_intc: interrupt-controller@408440 { 257 aon_pm_l2_intc: interrupt-controller@408440 {
251 compatible = "brcm,l2-intc"; 258 compatible = "brcm,l2-intc";
252 reg = <0x408440 0x30>; 259 reg = <0x408440 0x30>;
@@ -257,6 +264,17 @@
257 brcm,irq-can-wake; 264 brcm,irq-can-wake;
258 }; 265 };
259 266
267 aon_ctrl: syscon@408000 {
268 compatible = "brcm,brcmstb-aon-ctrl";
269 reg = <0x408000 0x100>, <0x408200 0x200>;
270 reg-names = "aon-ctrl", "aon-sram";
271 };
272
273 timers: timer@4067c0 {
274 compatible = "brcm,brcmstb-timers";
275 reg = <0x4067c0 0x40>;
276 };
277
260 upg_gio: gpio@406700 { 278 upg_gio: gpio@406700 {
261 compatible = "brcm,brcmstb-gpio"; 279 compatible = "brcm,brcmstb-gpio";
262 reg = <0x406700 0x80>; 280 reg = <0x406700 0x80>;
@@ -509,5 +527,76 @@
509 interrupt-names = "mspi_done"; 527 interrupt-names = "mspi_done";
510 status = "disabled"; 528 status = "disabled";
511 }; 529 };
530
531 waketimer: waketimer@409580 {
532 compatible = "brcm,brcmstb-waketimer";
533 reg = <0x409580 0x14>;
534 interrupts = <0x3>;
535 interrupt-parent = <&aon_pm_l2_intc>;
536 interrupt-names = "timer";
537 clocks = <&upg_clk>;
538 status = "disabled";
539 };
540 };
541
542 memory_controllers {
543 compatible = "simple-bus";
544 ranges = <0x0 0x103b0000 0x1a000>;
545 #address-cells = <1>;
546 #size-cells = <1>;
547
548 memory-controller@0 {
549 compatible = "brcm,brcmstb-memc", "simple-bus";
550 ranges = <0x0 0x0 0xa000>;
551 #address-cells = <1>;
552 #size-cells = <1>;
553
554 memc-arb@1000 {
555 compatible = "brcm,brcmstb-memc-arb";
556 reg = <0x1000 0x248>;
557 };
558
559 memc-ddr@2000 {
560 compatible = "brcm,brcmstb-memc-ddr";
561 reg = <0x2000 0x300>;
562 };
563
564 ddr-phy@6000 {
565 compatible = "brcm,brcmstb-ddr-phy";
566 reg = <0x6000 0xc8>;
567 };
568
569 shimphy@8000 {
570 compatible = "brcm,brcmstb-ddr-shimphy";
571 reg = <0x8000 0x13c>;
572 };
573 };
574
575 memory-controller@1 {
576 compatible = "brcm,brcmstb-memc", "simple-bus";
577 ranges = <0x0 0x10000 0xa000>;
578 #address-cells = <1>;
579 #size-cells = <1>;
580
581 memc-arb@1000 {
582 compatible = "brcm,brcmstb-memc-arb";
583 reg = <0x1000 0x248>;
584 };
585
586 memc-ddr@2000 {
587 compatible = "brcm,brcmstb-memc-ddr";
588 reg = <0x2000 0x300>;
589 };
590
591 ddr-phy@6000 {
592 compatible = "brcm,brcmstb-ddr-phy";
593 reg = <0x6000 0xc8>;
594 };
595
596 shimphy@8000 {
597 compatible = "brcm,brcmstb-ddr-shimphy";
598 reg = <0x8000 0x13c>;
599 };
600 };
512 }; 601 };
513}; 602};
diff --git a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
index 7f59ea2ded6c..79e9769f7e00 100644
--- a/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97125cbmb.dts
@@ -50,6 +50,10 @@
50 status = "okay"; 50 status = "okay";
51}; 51};
52 52
53&watchdog {
54 status = "okay";
55};
56
53/* FIXME: USB is wonky; disable it for now */ 57/* FIXME: USB is wonky; disable it for now */
54&ehci0 { 58&ehci0 {
55 status = "disabled"; 59 status = "disabled";
diff --git a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
index 9e7d5228f2b7..28370ff77eeb 100644
--- a/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97346dbsmb.dts
@@ -59,6 +59,10 @@
59 status = "okay"; 59 status = "okay";
60}; 60};
61 61
62&watchdog {
63 status = "okay";
64};
65
62&enet0 { 66&enet0 {
63 status = "okay"; 67 status = "okay";
64}; 68};
@@ -114,3 +118,7 @@
114&mspi { 118&mspi {
115 status = "okay"; 119 status = "okay";
116}; 120};
121
122&waketimer {
123 status = "okay";
124};
diff --git a/arch/mips/boot/dts/brcm/bcm97358svmb.dts b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
index 708207a0002d..41c1b510c230 100644
--- a/arch/mips/boot/dts/brcm/bcm97358svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97358svmb.dts
@@ -55,6 +55,10 @@
55 status = "okay"; 55 status = "okay";
56}; 56};
57 57
58&watchdog {
59 status = "okay";
60};
61
58&enet0 { 62&enet0 {
59 status = "okay"; 63 status = "okay";
60}; 64};
@@ -106,3 +110,7 @@
106&mspi { 110&mspi {
107 status = "okay"; 111 status = "okay";
108}; 112};
113
114&waketimer {
115 status = "okay";
116};
diff --git a/arch/mips/boot/dts/brcm/bcm97360svmb.dts b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
index 73c6dc9c8c6d..9f6c6c9b7ea7 100644
--- a/arch/mips/boot/dts/brcm/bcm97360svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97360svmb.dts
@@ -50,6 +50,10 @@
50 status = "okay"; 50 status = "okay";
51}; 51};
52 52
53&watchdog {
54 status = "okay";
55};
56
53&enet0 { 57&enet0 {
54 status = "okay"; 58 status = "okay";
55}; 59};
@@ -109,3 +113,7 @@
109&mspi { 113&mspi {
110 status = "okay"; 114 status = "okay";
111}; 115};
116
117&waketimer {
118 status = "okay";
119};
diff --git a/arch/mips/boot/dts/brcm/bcm97362svmb.dts b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
index 37bacfdcf9d9..df8b755c390f 100644
--- a/arch/mips/boot/dts/brcm/bcm97362svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97362svmb.dts
@@ -47,6 +47,10 @@
47 status = "okay"; 47 status = "okay";
48}; 48};
49 49
50&watchdog {
51 status = "okay";
52};
53
50&enet0 { 54&enet0 {
51 status = "okay"; 55 status = "okay";
52}; 56};
@@ -78,3 +82,7 @@
78&mspi { 82&mspi {
79 status = "okay"; 83 status = "okay";
80}; 84};
85
86&waketimer {
87 status = "okay";
88};
diff --git a/arch/mips/boot/dts/brcm/bcm97420c.dts b/arch/mips/boot/dts/brcm/bcm97420c.dts
index f96241e94874..086faeaa384a 100644
--- a/arch/mips/boot/dts/brcm/bcm97420c.dts
+++ b/arch/mips/boot/dts/brcm/bcm97420c.dts
@@ -60,6 +60,10 @@
60 status = "okay"; 60 status = "okay";
61}; 61};
62 62
63&watchdog {
64 status = "okay";
65};
66
63/* FIXME: MAC driver comes up but cannot attach to PHY */ 67/* FIXME: MAC driver comes up but cannot attach to PHY */
64&enet0 { 68&enet0 {
65 status = "disabled"; 69 status = "disabled";
diff --git a/arch/mips/boot/dts/brcm/bcm97425svmb.dts b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
index ce762c7b2e54..0ed22217bf3a 100644
--- a/arch/mips/boot/dts/brcm/bcm97425svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97425svmb.dts
@@ -61,6 +61,10 @@
61 status = "okay"; 61 status = "okay";
62}; 62};
63 63
64&watchdog {
65 status = "okay";
66};
67
64&enet0 { 68&enet0 {
65 status = "okay"; 69 status = "okay";
66}; 70};
@@ -144,3 +148,7 @@
144&mspi { 148&mspi {
145 status = "okay"; 149 status = "okay";
146}; 150};
151
152&waketimer {
153 status = "okay";
154};
diff --git a/arch/mips/boot/dts/brcm/bcm97435svmb.dts b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
index d4dd31a543fd..2c145a883aef 100644
--- a/arch/mips/boot/dts/brcm/bcm97435svmb.dts
+++ b/arch/mips/boot/dts/brcm/bcm97435svmb.dts
@@ -61,6 +61,10 @@
61 status = "okay"; 61 status = "okay";
62}; 62};
63 63
64&watchdog {
65 status = "okay";
66};
67
64&enet0 { 68&enet0 {
65 status = "okay"; 69 status = "okay";
66}; 70};
@@ -120,3 +124,7 @@
120&mspi { 124&mspi {
121 status = "okay"; 125 status = "okay";
122}; 126};
127
128&waketimer {
129 status = "okay";
130};
diff --git a/arch/mips/boot/dts/img/boston.dts b/arch/mips/boot/dts/img/boston.dts
index 2cd49b60e030..1bd105428f61 100644
--- a/arch/mips/boot/dts/img/boston.dts
+++ b/arch/mips/boot/dts/img/boston.dts
@@ -157,7 +157,7 @@
157 #address-cells = <1>; 157 #address-cells = <1>;
158 #size-cells = <0>; 158 #size-cells = <0>;
159 159
160 rtc@0x68 { 160 rtc@68 {
161 compatible = "st,m41t81s"; 161 compatible = "st,m41t81s";
162 reg = <0x68>; 162 reg = <0x68>;
163 }; 163 };
diff --git a/arch/mips/boot/dts/ingenic/ci20.dts b/arch/mips/boot/dts/ingenic/ci20.dts
index a4cc52214dbd..38078594cf97 100644
--- a/arch/mips/boot/dts/ingenic/ci20.dts
+++ b/arch/mips/boot/dts/ingenic/ci20.dts
@@ -110,22 +110,22 @@
110 reg = <0x0 0x0 0x0 0x800000>; 110 reg = <0x0 0x0 0x0 0x800000>;
111 }; 111 };
112 112
113 partition@0x800000 { 113 partition@800000 {
114 label = "u-boot"; 114 label = "u-boot";
115 reg = <0x0 0x800000 0x0 0x200000>; 115 reg = <0x0 0x800000 0x0 0x200000>;
116 }; 116 };
117 117
118 partition@0xa00000 { 118 partition@a00000 {
119 label = "u-boot-env"; 119 label = "u-boot-env";
120 reg = <0x0 0xa00000 0x0 0x200000>; 120 reg = <0x0 0xa00000 0x0 0x200000>;
121 }; 121 };
122 122
123 partition@0xc00000 { 123 partition@c00000 {
124 label = "boot"; 124 label = "boot";
125 reg = <0x0 0xc00000 0x0 0x4000000>; 125 reg = <0x0 0xc00000 0x0 0x4000000>;
126 }; 126 };
127 127
128 partition@0x8c00000 { 128 partition@4c00000 {
129 label = "system"; 129 label = "system";
130 reg = <0x0 0x4c00000 0x1 0xfb400000>; 130 reg = <0x0 0x4c00000 0x1 0xfb400000>;
131 }; 131 };
diff --git a/arch/mips/boot/dts/mscc/Makefile b/arch/mips/boot/dts/mscc/Makefile
new file mode 100644
index 000000000000..c51164537c02
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/Makefile
@@ -0,0 +1,3 @@
1dtb-$(CONFIG_LEGACY_BOARD_OCELOT) += ocelot_pcb123.dtb
2
3obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
new file mode 100644
index 000000000000..dd239cab2f9d
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -0,0 +1,117 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/ {
5 #address-cells = <1>;
6 #size-cells = <1>;
7 compatible = "mscc,ocelot";
8
9 cpus {
10 #address-cells = <1>;
11 #size-cells = <0>;
12
13 cpu@0 {
14 compatible = "mips,mips24KEc";
15 device_type = "cpu";
16 clocks = <&cpu_clk>;
17 reg = <0>;
18 };
19 };
20
21 aliases {
22 serial0 = &uart0;
23 };
24
25 cpuintc: interrupt-controller {
26 #address-cells = <0>;
27 #interrupt-cells = <1>;
28 interrupt-controller;
29 compatible = "mti,cpu-interrupt-controller";
30 };
31
32 cpu_clk: cpu-clock {
33 compatible = "fixed-clock";
34 #clock-cells = <0>;
35 clock-frequency = <500000000>;
36 };
37
38 ahb_clk: ahb-clk {
39 compatible = "fixed-factor-clock";
40 #clock-cells = <0>;
41 clocks = <&cpu_clk>;
42 clock-div = <2>;
43 clock-mult = <1>;
44 };
45
46 ahb@70000000 {
47 compatible = "simple-bus";
48 #address-cells = <1>;
49 #size-cells = <1>;
50 ranges = <0 0x70000000 0x2000000>;
51
52 interrupt-parent = <&intc>;
53
54 cpu_ctrl: syscon@0 {
55 compatible = "mscc,ocelot-cpu-syscon", "syscon";
56 reg = <0x0 0x2c>;
57 };
58
59 intc: interrupt-controller@70 {
60 compatible = "mscc,ocelot-icpu-intr";
61 reg = <0x70 0x70>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 interrupt-parent = <&cpuintc>;
65 interrupts = <2>;
66 };
67
68 uart0: serial@100000 {
69 pinctrl-0 = <&uart_pins>;
70 pinctrl-names = "default";
71 compatible = "ns16550a";
72 reg = <0x100000 0x20>;
73 interrupts = <6>;
74 clocks = <&ahb_clk>;
75 reg-io-width = <4>;
76 reg-shift = <2>;
77
78 status = "disabled";
79 };
80
81 uart2: serial@100800 {
82 pinctrl-0 = <&uart2_pins>;
83 pinctrl-names = "default";
84 compatible = "ns16550a";
85 reg = <0x100800 0x20>;
86 interrupts = <7>;
87 clocks = <&ahb_clk>;
88 reg-io-width = <4>;
89 reg-shift = <2>;
90
91 status = "disabled";
92 };
93
94 reset@1070008 {
95 compatible = "mscc,ocelot-chip-reset";
96 reg = <0x1070008 0x4>;
97 };
98
99 gpio: pinctrl@1070034 {
100 compatible = "mscc,ocelot-pinctrl";
101 reg = <0x1070034 0x68>;
102 gpio-controller;
103 #gpio-cells = <2>;
104 gpio-ranges = <&gpio 0 0 22>;
105
106 uart_pins: uart-pins {
107 pins = "GPIO_6", "GPIO_7";
108 function = "uart";
109 };
110
111 uart2_pins: uart2-pins {
112 pins = "GPIO_12", "GPIO_13";
113 function = "uart2";
114 };
115 };
116 };
117};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
new file mode 100644
index 000000000000..29d6414f8886
--- /dev/null
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -0,0 +1,27 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2017 Microsemi Corporation */
3
4/dts-v1/;
5
6#include "ocelot.dtsi"
7
8/ {
9 compatible = "mscc,ocelot-pcb123", "mscc,ocelot";
10
11 chosen {
12 stdout-path = "serial0:115200n8";
13 };
14
15 memory@0 {
16 device_type = "memory";
17 reg = <0x0 0x0e000000>;
18 };
19};
20
21&uart0 {
22 status = "okay";
23};
24
25&uart2 {
26 status = "okay";
27};
diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
index d99f5242169e..b3aec101a65d 100644
--- a/arch/mips/cavium-octeon/octeon-irq.c
+++ b/arch/mips/cavium-octeon/octeon-irq.c
@@ -2271,7 +2271,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2271 2271
2272 parent_irq = irq_of_parse_and_map(ciu_node, 0); 2272 parent_irq = irq_of_parse_and_map(ciu_node, 0);
2273 if (!parent_irq) { 2273 if (!parent_irq) {
2274 pr_err("ERROR: Couldn't acquire parent_irq for %s\n.", 2274 pr_err("ERROR: Couldn't acquire parent_irq for %s\n",
2275 ciu_node->name); 2275 ciu_node->name);
2276 return -EINVAL; 2276 return -EINVAL;
2277 } 2277 }
@@ -2283,7 +2283,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2283 2283
2284 addr = of_get_address(ciu_node, 0, NULL, NULL); 2284 addr = of_get_address(ciu_node, 0, NULL, NULL);
2285 if (!addr) { 2285 if (!addr) {
2286 pr_err("ERROR: Couldn't acquire reg(0) %s\n.", ciu_node->name); 2286 pr_err("ERROR: Couldn't acquire reg(0) %s\n", ciu_node->name);
2287 return -EINVAL; 2287 return -EINVAL;
2288 } 2288 }
2289 host_data->raw_reg = (u64)phys_to_virt( 2289 host_data->raw_reg = (u64)phys_to_virt(
@@ -2291,7 +2291,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2291 2291
2292 addr = of_get_address(ciu_node, 1, NULL, NULL); 2292 addr = of_get_address(ciu_node, 1, NULL, NULL);
2293 if (!addr) { 2293 if (!addr) {
2294 pr_err("ERROR: Couldn't acquire reg(1) %s\n.", ciu_node->name); 2294 pr_err("ERROR: Couldn't acquire reg(1) %s\n", ciu_node->name);
2295 return -EINVAL; 2295 return -EINVAL;
2296 } 2296 }
2297 host_data->en_reg = (u64)phys_to_virt( 2297 host_data->en_reg = (u64)phys_to_virt(
@@ -2299,7 +2299,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2299 2299
2300 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val); 2300 r = of_property_read_u32(ciu_node, "cavium,max-bits", &val);
2301 if (r) { 2301 if (r) {
2302 pr_err("ERROR: Couldn't read cavium,max-bits from %s\n.", 2302 pr_err("ERROR: Couldn't read cavium,max-bits from %s\n",
2303 ciu_node->name); 2303 ciu_node->name);
2304 return r; 2304 return r;
2305 } 2305 }
@@ -2309,7 +2309,7 @@ static int __init octeon_irq_init_cib(struct device_node *ciu_node,
2309 &octeon_irq_domain_cib_ops, 2309 &octeon_irq_domain_cib_ops,
2310 host_data); 2310 host_data);
2311 if (!cib_domain) { 2311 if (!cib_domain) {
2312 pr_err("ERROR: Couldn't irq_domain_add_linear()\n."); 2312 pr_err("ERROR: Couldn't irq_domain_add_linear()\n");
2313 return -ENOMEM; 2313 return -ENOMEM;
2314 } 2314 }
2315 2315
diff --git a/arch/mips/configs/bmips_stb_defconfig b/arch/mips/configs/bmips_stb_defconfig
index 3cefa6bc01dd..47aecb8750e6 100644
--- a/arch/mips/configs/bmips_stb_defconfig
+++ b/arch/mips/configs/bmips_stb_defconfig
@@ -72,6 +72,7 @@ CONFIG_USB_EHCI_HCD_PLATFORM=y
72CONFIG_USB_OHCI_HCD=y 72CONFIG_USB_OHCI_HCD=y
73CONFIG_USB_OHCI_HCD_PLATFORM=y 73CONFIG_USB_OHCI_HCD_PLATFORM=y
74CONFIG_USB_STORAGE=y 74CONFIG_USB_STORAGE=y
75CONFIG_SOC_BRCMSTB=y
75CONFIG_EXT4_FS=y 76CONFIG_EXT4_FS=y
76CONFIG_EXT4_FS_POSIX_ACL=y 77CONFIG_EXT4_FS_POSIX_ACL=y
77CONFIG_EXT4_FS_SECURITY=y 78CONFIG_EXT4_FS_SECURITY=y
diff --git a/arch/mips/configs/generic/32r6.config b/arch/mips/configs/generic/32r6.config
index ca606e71f4d0..1a5d5ea4ab2b 100644
--- a/arch/mips/configs/generic/32r6.config
+++ b/arch/mips/configs/generic/32r6.config
@@ -1,2 +1,4 @@
1CONFIG_CPU_MIPS32_R6=y 1CONFIG_CPU_MIPS32_R6=y
2CONFIG_HIGHMEM=y 2CONFIG_HIGHMEM=y
3
4CONFIG_CRYPTO_CRC32_MIPS=y
diff --git a/arch/mips/configs/generic/64r6.config b/arch/mips/configs/generic/64r6.config
index 7cac0339c4d5..5dd8e8503e34 100644
--- a/arch/mips/configs/generic/64r6.config
+++ b/arch/mips/configs/generic/64r6.config
@@ -2,3 +2,5 @@ CONFIG_CPU_MIPS64_R6=y
2CONFIG_64BIT=y 2CONFIG_64BIT=y
3CONFIG_MIPS32_O32=y 3CONFIG_MIPS32_O32=y
4CONFIG_MIPS32_N32=y 4CONFIG_MIPS32_N32=y
5
6CONFIG_CRYPTO_CRC32_MIPS=y
diff --git a/arch/mips/configs/generic/board-ocelot.config b/arch/mips/configs/generic/board-ocelot.config
new file mode 100644
index 000000000000..aa815761d85e
--- /dev/null
+++ b/arch/mips/configs/generic/board-ocelot.config
@@ -0,0 +1,35 @@
1# require CONFIG_CPU_MIPS32_R2=y
2
3CONFIG_LEGACY_BOARD_OCELOT=y
4
5CONFIG_MTD=y
6CONFIG_MTD_CMDLINE_PARTS=y
7CONFIG_MTD_BLOCK=y
8CONFIG_MTD_M25P80=y
9CONFIG_MTD_NAND=y
10CONFIG_MTD_NAND_PLATFORM=y
11CONFIG_MTD_SPI_NOR=y
12CONFIG_MTD_UBI=y
13
14CONFIG_BLK_DEV_LOOP=y
15CONFIG_BLK_DEV_RAM=y
16
17CONFIG_SERIAL_8250=y
18CONFIG_SERIAL_8250_CONSOLE=y
19CONFIG_SERIAL_OF_PLATFORM=y
20
21CONFIG_GPIO_SYSFS=y
22
23CONFIG_I2C=y
24CONFIG_I2C_CHARDEV=y
25CONFIG_I2C_MUX=y
26
27CONFIG_SPI=y
28CONFIG_SPI_BITBANG=y
29CONFIG_SPI_DESIGNWARE=y
30CONFIG_SPI_SPIDEV=y
31
32CONFIG_POWER_RESET=y
33CONFIG_POWER_RESET_OCELOT_RESET=y
34
35CONFIG_MAGIC_SYSRQ=y
diff --git a/arch/mips/crypto/Makefile b/arch/mips/crypto/Makefile
new file mode 100644
index 000000000000..e07aca572c2e
--- /dev/null
+++ b/arch/mips/crypto/Makefile
@@ -0,0 +1,6 @@
1# SPDX-License-Identifier: GPL-2.0
2#
3# Makefile for MIPS crypto files..
4#
5
6obj-$(CONFIG_CRYPTO_CRC32_MIPS) += crc32-mips.o
diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c
new file mode 100644
index 000000000000..7d1d2425746f
--- /dev/null
+++ b/arch/mips/crypto/crc32-mips.c
@@ -0,0 +1,348 @@
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * crc32-mips.c - CRC32 and CRC32C using optional MIPSr6 instructions
4 *
5 * Module based on arm64/crypto/crc32-arm.c
6 *
7 * Copyright (C) 2014 Linaro Ltd <yazen.ghannam@linaro.org>
8 * Copyright (C) 2018 MIPS Tech, LLC
9 */
10
11#include <linux/unaligned/access_ok.h>
12#include <linux/cpufeature.h>
13#include <linux/init.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/string.h>
17#include <asm/mipsregs.h>
18
19#include <crypto/internal/hash.h>
20
21enum crc_op_size {
22 b, h, w, d,
23};
24
25enum crc_type {
26 crc32,
27 crc32c,
28};
29
30#ifndef TOOLCHAIN_SUPPORTS_CRC
31#define _ASM_MACRO_CRC32(OP, SZ, TYPE) \
32_ASM_MACRO_3R(OP, rt, rs, rt2, \
33 ".ifnc \\rt, \\rt2\n\t" \
34 ".error \"invalid operands \\\"" #OP " \\rt,\\rs,\\rt2\\\"\"\n\t" \
35 ".endif\n\t" \
36 _ASM_INSN_IF_MIPS(0x7c00000f | (__rt << 16) | (__rs << 21) | \
37 ((SZ) << 6) | ((TYPE) << 8)) \
38 _ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) | \
39 ((SZ) << 14) | ((TYPE) << 3)))
40_ASM_MACRO_CRC32(crc32b, 0, 0);
41_ASM_MACRO_CRC32(crc32h, 1, 0);
42_ASM_MACRO_CRC32(crc32w, 2, 0);
43_ASM_MACRO_CRC32(crc32d, 3, 0);
44_ASM_MACRO_CRC32(crc32cb, 0, 1);
45_ASM_MACRO_CRC32(crc32ch, 1, 1);
46_ASM_MACRO_CRC32(crc32cw, 2, 1);
47_ASM_MACRO_CRC32(crc32cd, 3, 1);
48#define _ASM_SET_CRC ""
49#else /* !TOOLCHAIN_SUPPORTS_CRC */
50#define _ASM_SET_CRC ".set\tcrc\n\t"
51#endif
52
53#define _CRC32(crc, value, size, type) \
54do { \
55 __asm__ __volatile__( \
56 ".set push\n\t" \
57 _ASM_SET_CRC \
58 #type #size " %0, %1, %0\n\t" \
59 ".set pop" \
60 : "+r" (crc) \
61 : "r" (value)); \
62} while (0)
63
64#define CRC32(crc, value, size) \
65 _CRC32(crc, value, size, crc32)
66
67#define CRC32C(crc, value, size) \
68 _CRC32(crc, value, size, crc32c)
69
70static u32 crc32_mips_le_hw(u32 crc_, const u8 *p, unsigned int len)
71{
72 u32 crc = crc_;
73
74#ifdef CONFIG_64BIT
75 while (len >= sizeof(u64)) {
76 u64 value = get_unaligned_le64(p);
77
78 CRC32(crc, value, d);
79 p += sizeof(u64);
80 len -= sizeof(u64);
81 }
82
83 if (len & sizeof(u32)) {
84#else /* !CONFIG_64BIT */
85 while (len >= sizeof(u32)) {
86#endif
87 u32 value = get_unaligned_le32(p);
88
89 CRC32(crc, value, w);
90 p += sizeof(u32);
91 len -= sizeof(u32);
92 }
93
94 if (len & sizeof(u16)) {
95 u16 value = get_unaligned_le16(p);
96
97 CRC32(crc, value, h);
98 p += sizeof(u16);
99 }
100
101 if (len & sizeof(u8)) {
102 u8 value = *p++;
103
104 CRC32(crc, value, b);
105 }
106
107 return crc;
108}
109
110static u32 crc32c_mips_le_hw(u32 crc_, const u8 *p, unsigned int len)
111{
112 u32 crc = crc_;
113
114#ifdef CONFIG_64BIT
115 while (len >= sizeof(u64)) {
116 u64 value = get_unaligned_le64(p);
117
118 CRC32C(crc, value, d);
119 p += sizeof(u64);
120 len -= sizeof(u64);
121 }
122
123 if (len & sizeof(u32)) {
124#else /* !CONFIG_64BIT */
125 while (len >= sizeof(u32)) {
126#endif
127 u32 value = get_unaligned_le32(p);
128
129 CRC32C(crc, value, w);
130 p += sizeof(u32);
131 len -= sizeof(u32);
132 }
133
134 if (len & sizeof(u16)) {
135 u16 value = get_unaligned_le16(p);
136
137 CRC32C(crc, value, h);
138 p += sizeof(u16);
139 }
140
141 if (len & sizeof(u8)) {
142 u8 value = *p++;
143
144 CRC32C(crc, value, b);
145 }
146 return crc;
147}
148
149#define CHKSUM_BLOCK_SIZE 1
150#define CHKSUM_DIGEST_SIZE 4
151
152struct chksum_ctx {
153 u32 key;
154};
155
156struct chksum_desc_ctx {
157 u32 crc;
158};
159
160static int chksum_init(struct shash_desc *desc)
161{
162 struct chksum_ctx *mctx = crypto_shash_ctx(desc->tfm);
163 struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
164
165 ctx->crc = mctx->key;
166
167 return 0;
168}
169
170/*
171 * Setting the seed allows arbitrary accumulators and flexible XOR policy
172 * If your algorithm starts with ~0, then XOR with ~0 before you set
173 * the seed.
174 */
175static int chksum_setkey(struct crypto_shash *tfm, const u8 *key,
176 unsigned int keylen)
177{
178 struct chksum_ctx *mctx = crypto_shash_ctx(tfm);
179
180 if (keylen != sizeof(mctx->key)) {
181 crypto_shash_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
182 return -EINVAL;
183 }
184 mctx->key = get_unaligned_le32(key);
185 return 0;
186}
187
188static int chksum_update(struct shash_desc *desc, const u8 *data,
189 unsigned int length)
190{
191 struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
192
193 ctx->crc = crc32_mips_le_hw(ctx->crc, data, length);
194 return 0;
195}
196
197static int chksumc_update(struct shash_desc *desc, const u8 *data,
198 unsigned int length)
199{
200 struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
201
202 ctx->crc = crc32c_mips_le_hw(ctx->crc, data, length);
203 return 0;
204}
205
206static int chksum_final(struct shash_desc *desc, u8 *out)
207{
208 struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
209
210 put_unaligned_le32(ctx->crc, out);
211 return 0;
212}
213
214static int chksumc_final(struct shash_desc *desc, u8 *out)
215{
216 struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
217
218 put_unaligned_le32(~ctx->crc, out);
219 return 0;
220}
221
222static int __chksum_finup(u32 crc, const u8 *data, unsigned int len, u8 *out)
223{
224 put_unaligned_le32(crc32_mips_le_hw(crc, data, len), out);
225 return 0;
226}
227
228static int __chksumc_finup(u32 crc, const u8 *data, unsigned int len, u8 *out)
229{
230 put_unaligned_le32(~crc32c_mips_le_hw(crc, data, len), out);
231 return 0;
232}
233
234static int chksum_finup(struct shash_desc *desc, const u8 *data,
235 unsigned int len, u8 *out)
236{
237 struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
238
239 return __chksum_finup(ctx->crc, data, len, out);
240}
241
242static int chksumc_finup(struct shash_desc *desc, const u8 *data,
243 unsigned int len, u8 *out)
244{
245 struct chksum_desc_ctx *ctx = shash_desc_ctx(desc);
246
247 return __chksumc_finup(ctx->crc, data, len, out);
248}
249
250static int chksum_digest(struct shash_desc *desc, const u8 *data,
251 unsigned int length, u8 *out)
252{
253 struct chksum_ctx *mctx = crypto_shash_ctx(desc->tfm);
254
255 return __chksum_finup(mctx->key, data, length, out);
256}
257
258static int chksumc_digest(struct shash_desc *desc, const u8 *data,
259 unsigned int length, u8 *out)
260{
261 struct chksum_ctx *mctx = crypto_shash_ctx(desc->tfm);
262
263 return __chksumc_finup(mctx->key, data, length, out);
264}
265
266static int chksum_cra_init(struct crypto_tfm *tfm)
267{
268 struct chksum_ctx *mctx = crypto_tfm_ctx(tfm);
269
270 mctx->key = ~0;
271 return 0;
272}
273
274static struct shash_alg crc32_alg = {
275 .digestsize = CHKSUM_DIGEST_SIZE,
276 .setkey = chksum_setkey,
277 .init = chksum_init,
278 .update = chksum_update,
279 .final = chksum_final,
280 .finup = chksum_finup,
281 .digest = chksum_digest,
282 .descsize = sizeof(struct chksum_desc_ctx),
283 .base = {
284 .cra_name = "crc32",
285 .cra_driver_name = "crc32-mips-hw",
286 .cra_priority = 300,
287 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
288 .cra_blocksize = CHKSUM_BLOCK_SIZE,
289 .cra_alignmask = 0,
290 .cra_ctxsize = sizeof(struct chksum_ctx),
291 .cra_module = THIS_MODULE,
292 .cra_init = chksum_cra_init,
293 }
294};
295
296static struct shash_alg crc32c_alg = {
297 .digestsize = CHKSUM_DIGEST_SIZE,
298 .setkey = chksum_setkey,
299 .init = chksum_init,
300 .update = chksumc_update,
301 .final = chksumc_final,
302 .finup = chksumc_finup,
303 .digest = chksumc_digest,
304 .descsize = sizeof(struct chksum_desc_ctx),
305 .base = {
306 .cra_name = "crc32c",
307 .cra_driver_name = "crc32c-mips-hw",
308 .cra_priority = 300,
309 .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
310 .cra_blocksize = CHKSUM_BLOCK_SIZE,
311 .cra_alignmask = 0,
312 .cra_ctxsize = sizeof(struct chksum_ctx),
313 .cra_module = THIS_MODULE,
314 .cra_init = chksum_cra_init,
315 }
316};
317
318static int __init crc32_mod_init(void)
319{
320 int err;
321
322 err = crypto_register_shash(&crc32_alg);
323
324 if (err)
325 return err;
326
327 err = crypto_register_shash(&crc32c_alg);
328
329 if (err) {
330 crypto_unregister_shash(&crc32_alg);
331 return err;
332 }
333
334 return 0;
335}
336
337static void __exit crc32_mod_exit(void)
338{
339 crypto_unregister_shash(&crc32_alg);
340 crypto_unregister_shash(&crc32c_alg);
341}
342
343MODULE_AUTHOR("Marcin Nowakowski <marcin.nowakowski@mips.com");
344MODULE_DESCRIPTION("CRC32 and CRC32C using optional MIPS instructions");
345MODULE_LICENSE("GPL v2");
346
347module_cpu_feature_match(MIPS_CRC32, crc32_mod_init);
348module_exit(crc32_mod_exit);
diff --git a/arch/mips/generic/Kconfig b/arch/mips/generic/Kconfig
index 2ff3b17bfab1..ba9b2c8cce68 100644
--- a/arch/mips/generic/Kconfig
+++ b/arch/mips/generic/Kconfig
@@ -27,6 +27,22 @@ config LEGACY_BOARD_SEAD3
27 Enable this to include support for booting on MIPS SEAD-3 FPGA-based 27 Enable this to include support for booting on MIPS SEAD-3 FPGA-based
28 development boards, which boot using a legacy boot protocol. 28 development boards, which boot using a legacy boot protocol.
29 29
30comment "MSCC Ocelot doesn't work with SEAD3 enabled"
31 depends on LEGACY_BOARD_SEAD3
32
33config LEGACY_BOARD_OCELOT
34 bool "Support MSCC Ocelot boards"
35 depends on LEGACY_BOARD_SEAD3=n
36 select LEGACY_BOARDS
37 select MSCC_OCELOT
38
39config MSCC_OCELOT
40 bool
41 select GPIOLIB
42 select MSCC_OCELOT_IRQ
43 select SYS_HAS_EARLY_PRINTK
44 select USE_GENERIC_EARLY_PRINTK_8250
45
30comment "FIT/UHI Boards" 46comment "FIT/UHI Boards"
31 47
32config FIT_IMAGE_FDT_BOSTON 48config FIT_IMAGE_FDT_BOSTON
diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile
index 5c31e0c4697d..d03a36f869a4 100644
--- a/arch/mips/generic/Makefile
+++ b/arch/mips/generic/Makefile
@@ -14,5 +14,6 @@ obj-y += proc.o
14 14
15obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o 15obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o
16obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o 16obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o
17obj-$(CONFIG_LEGACY_BOARD_OCELOT) += board-ocelot.o
17obj-$(CONFIG_KEXEC) += kexec.o 18obj-$(CONFIG_KEXEC) += kexec.o
18obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o 19obj-$(CONFIG_VIRT_BOARD_RANCHU) += board-ranchu.o
diff --git a/arch/mips/generic/board-ocelot.c b/arch/mips/generic/board-ocelot.c
new file mode 100644
index 000000000000..06d92fb37769
--- /dev/null
+++ b/arch/mips/generic/board-ocelot.c
@@ -0,0 +1,78 @@
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Microsemi MIPS SoC support
4 *
5 * Copyright (c) 2017 Microsemi Corporation
6 */
7#include <asm/machine.h>
8#include <asm/prom.h>
9
10#define DEVCPU_GCB_CHIP_REGS_CHIP_ID 0x71070000
11#define CHIP_ID_PART_ID GENMASK(27, 12)
12
13#define OCELOT_PART_ID (0x7514 << 12)
14
15#define UART_UART 0x70100000
16
17static __init bool ocelot_detect(void)
18{
19 u32 rev;
20 int idx;
21
22 /* Look for the TLB entry set up by redboot before trying to use it */
23 write_c0_entryhi(DEVCPU_GCB_CHIP_REGS_CHIP_ID);
24 mtc0_tlbw_hazard();
25 tlb_probe();
26 tlb_probe_hazard();
27 idx = read_c0_index();
28 if (idx < 0)
29 return 0;
30
31 /* A TLB entry exists, lets assume its usable and check the CHIP ID */
32 rev = __raw_readl((void __iomem *)DEVCPU_GCB_CHIP_REGS_CHIP_ID);
33
34 if ((rev & CHIP_ID_PART_ID) != OCELOT_PART_ID)
35 return 0;
36
37 /* Copy command line from bootloader early for Initrd detection */
38 if (fw_arg0 < 10 && (fw_arg1 & 0xFFF00000) == 0x80000000) {
39 unsigned int prom_argc = fw_arg0;
40 const char **prom_argv = (const char **)fw_arg1;
41
42 if (prom_argc > 1 && strlen(prom_argv[1]) > 0)
43 /* ignore all built-in args if any f/w args given */
44 strcpy(arcs_cmdline, prom_argv[1]);
45 }
46
47 return 1;
48}
49
50static void __init ocelot_earlyprintk_init(void)
51{
52 void __iomem *uart_base;
53
54 uart_base = ioremap_nocache(UART_UART, 0x20);
55 setup_8250_early_printk_port((unsigned long)uart_base, 2, 50000);
56}
57
58static void __init ocelot_late_init(void)
59{
60 ocelot_earlyprintk_init();
61}
62
63static __init const void *ocelot_fixup_fdt(const void *fdt,
64 const void *match_data)
65{
66 /* This has to be done so late because ioremap needs to work */
67 late_time_init = ocelot_late_init;
68
69 return fdt;
70}
71
72extern char __dtb_ocelot_pcb123_begin[];
73
74MIPS_MACHINE(ocelot) = {
75 .fdt = __dtb_ocelot_pcb123_begin,
76 .fixup_fdt = ocelot_fixup_fdt,
77 .detect = ocelot_detect,
78};
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index 721b698bfe3c..5f74590e0bea 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -11,6 +11,7 @@
11 11
12#include <asm/cpu.h> 12#include <asm/cpu.h>
13#include <asm/cpu-info.h> 13#include <asm/cpu-info.h>
14#include <asm/isa-rev.h>
14#include <cpu-feature-overrides.h> 15#include <cpu-feature-overrides.h>
15 16
16/* 17/*
@@ -493,7 +494,7 @@
493# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF) 494# define cpu_has_perf (cpu_data[0].options & MIPS_CPU_PERF)
494#endif 495#endif
495 496
496#if defined(CONFIG_SMP) && defined(__mips_isa_rev) && (__mips_isa_rev >= 6) 497#if defined(CONFIG_SMP) && (MIPS_ISA_REV >= 6)
497/* 498/*
498 * Some systems share FTLB RAMs between threads within a core (siblings in 499 * Some systems share FTLB RAMs between threads within a core (siblings in
499 * kernel parlance). This means that FTLB entries may become invalid at almost 500 * kernel parlance). This means that FTLB entries may become invalid at almost
@@ -525,7 +526,7 @@
525# define cpu_has_shared_ftlb_entries \ 526# define cpu_has_shared_ftlb_entries \
526 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES) 527 (current_cpu_data.options & MIPS_CPU_SHARED_FTLB_ENTRIES)
527# endif 528# endif
528#endif /* SMP && __mips_isa_rev >= 6 */ 529#endif /* SMP && MIPS_ISA_REV >= 6 */
529 530
530#ifndef cpu_has_shared_ftlb_ram 531#ifndef cpu_has_shared_ftlb_ram
531# define cpu_has_shared_ftlb_ram 0 532# define cpu_has_shared_ftlb_ram 0
diff --git a/arch/mips/include/asm/isa-rev.h b/arch/mips/include/asm/isa-rev.h
new file mode 100644
index 000000000000..683ea3454dcb
--- /dev/null
+++ b/arch/mips/include/asm/isa-rev.h
@@ -0,0 +1,24 @@
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 MIPS Tech, LLC
4 * Author: Matt Redfearn <matt.redfearn@mips.com>
5 */
6
7#ifndef __MIPS_ASM_ISA_REV_H__
8#define __MIPS_ASM_ISA_REV_H__
9
10/*
11 * The ISA revision level. This is 0 for MIPS I to V and N for
12 * MIPS{32,64}rN.
13 */
14
15/* If the compiler has defined __mips_isa_rev, believe it. */
16#ifdef __mips_isa_rev
17#define MIPS_ISA_REV __mips_isa_rev
18#else
19/* The compiler hasn't defined the isa rev so assume it's MIPS I - V (0) */
20#define MIPS_ISA_REV 0
21#endif
22
23
24#endif /* __MIPS_ASM_ISA_REV_H__ */
diff --git a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
index aa3800c82332..d99ca862dae3 100644
--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
@@ -167,7 +167,7 @@
167#define AR71XX_AHB_DIV_MASK 0x7 167#define AR71XX_AHB_DIV_MASK 0x7
168 168
169#define AR724X_PLL_REG_CPU_CONFIG 0x00 169#define AR724X_PLL_REG_CPU_CONFIG 0x00
170#define AR724X_PLL_REG_PCIE_CONFIG 0x18 170#define AR724X_PLL_REG_PCIE_CONFIG 0x10
171 171
172#define AR724X_PLL_FB_SHIFT 0 172#define AR724X_PLL_FB_SHIFT 0
173#define AR724X_PLL_FB_MASK 0x3ff 173#define AR724X_PLL_FB_MASK 0x3ff
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 858752dac337..f65859784a4c 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -664,6 +664,7 @@
664#define MIPS_CONF5_FRE (_ULCAST_(1) << 8) 664#define MIPS_CONF5_FRE (_ULCAST_(1) << 8)
665#define MIPS_CONF5_UFE (_ULCAST_(1) << 9) 665#define MIPS_CONF5_UFE (_ULCAST_(1) << 9)
666#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14) 666#define MIPS_CONF5_CA2 (_ULCAST_(1) << 14)
667#define MIPS_CONF5_CRCP (_ULCAST_(1) << 18)
667#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27) 668#define MIPS_CONF5_MSAEN (_ULCAST_(1) << 27)
668#define MIPS_CONF5_EVA (_ULCAST_(1) << 28) 669#define MIPS_CONF5_EVA (_ULCAST_(1) << 28)
669#define MIPS_CONF5_CV (_ULCAST_(1) << 29) 670#define MIPS_CONF5_CV (_ULCAST_(1) << 29)
diff --git a/arch/mips/include/uapi/asm/hwcap.h b/arch/mips/include/uapi/asm/hwcap.h
index 600ad8fd6835..a2aba4b059e6 100644
--- a/arch/mips/include/uapi/asm/hwcap.h
+++ b/arch/mips/include/uapi/asm/hwcap.h
@@ -5,5 +5,6 @@
5/* HWCAP flags */ 5/* HWCAP flags */
6#define HWCAP_MIPS_R6 (1 << 0) 6#define HWCAP_MIPS_R6 (1 << 0)
7#define HWCAP_MIPS_MSA (1 << 1) 7#define HWCAP_MIPS_MSA (1 << 1)
8#define HWCAP_MIPS_CRC32 (1 << 2)
8 9
9#endif /* _UAPI_ASM_HWCAP_H */ 10#endif /* _UAPI_ASM_HWCAP_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index cf3fd549e16d..6b07b739f914 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -848,6 +848,9 @@ static inline unsigned int decode_config5(struct cpuinfo_mips *c)
848 if (config5 & MIPS_CONF5_CA2) 848 if (config5 & MIPS_CONF5_CA2)
849 c->ases |= MIPS_ASE_MIPS16E2; 849 c->ases |= MIPS_ASE_MIPS16E2;
850 850
851 if (config5 & MIPS_CONF5_CRCP)
852 elf_hwcap |= HWCAP_MIPS_CRC32;
853
851 return config5 & MIPS_CONF_M; 854 return config5 & MIPS_CONF_M;
852} 855}
853 856
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 421e06dfee72..55c3fbeb2df6 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -12,6 +12,7 @@
12#include <linux/init.h> 12#include <linux/init.h>
13#include <linux/percpu.h> 13#include <linux/percpu.h>
14#include <linux/slab.h> 14#include <linux/slab.h>
15#include <linux/suspend.h>
15 16
16#include <asm/asm-offsets.h> 17#include <asm/asm-offsets.h>
17#include <asm/cacheflush.h> 18#include <asm/cacheflush.h>
@@ -670,6 +671,34 @@ static int cps_pm_online_cpu(unsigned int cpu)
670 return 0; 671 return 0;
671} 672}
672 673
674static int cps_pm_power_notifier(struct notifier_block *this,
675 unsigned long event, void *ptr)
676{
677 unsigned int stat;
678
679 switch (event) {
680 case PM_SUSPEND_PREPARE:
681 stat = read_cpc_cl_stat_conf();
682 /*
683 * If we're attempting to suspend the system and power down all
684 * of the cores, the JTAG detect bit indicates that the CPC will
685 * instead put the cores into clock-off state. In this state
686 * a connected debugger can cause the CPU to attempt
687 * interactions with the powered down system. At best this will
688 * fail. At worst, it can hang the NoC, requiring a hard reset.
689 * To avoid this, just block system suspend if a JTAG probe
690 * is detected.
691 */
692 if (stat & CPC_Cx_STAT_CONF_EJTAG_PROBE) {
693 pr_warn("JTAG probe is connected - abort suspend\n");
694 return NOTIFY_BAD;
695 }
696 return NOTIFY_DONE;
697 default:
698 return NOTIFY_DONE;
699 }
700}
701
673static int __init cps_pm_init(void) 702static int __init cps_pm_init(void)
674{ 703{
675 /* A CM is required for all non-coherent states */ 704 /* A CM is required for all non-coherent states */
@@ -705,6 +734,8 @@ static int __init cps_pm_init(void)
705 pr_warn("pm-cps: no CPC, clock & power gating unavailable\n"); 734 pr_warn("pm-cps: no CPC, clock & power gating unavailable\n");
706 } 735 }
707 736
737 pm_notifier(cps_pm_power_notifier, 0);
738
708 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online", 739 return cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "mips/cps_pm:online",
709 cps_pm_online_cpu, NULL); 740 cps_pm_online_cpu, NULL);
710} 741}
diff --git a/arch/mips/kernel/reset.c b/arch/mips/kernel/reset.c
index 7c746d3458e7..6288780b779e 100644
--- a/arch/mips/kernel/reset.c
+++ b/arch/mips/kernel/reset.c
@@ -13,6 +13,9 @@
13#include <linux/reboot.h> 13#include <linux/reboot.h>
14#include <linux/delay.h> 14#include <linux/delay.h>
15 15
16#include <asm/compiler.h>
17#include <asm/idle.h>
18#include <asm/mipsregs.h>
16#include <asm/reboot.h> 19#include <asm/reboot.h>
17 20
18/* 21/*
@@ -26,6 +29,62 @@ void (*pm_power_off)(void);
26 29
27EXPORT_SYMBOL(pm_power_off); 30EXPORT_SYMBOL(pm_power_off);
28 31
32static void machine_hang(void)
33{
34 /*
35 * We're hanging the system so we don't want to be interrupted anymore.
36 * Any interrupt handlers that ran would at best be useless & at worst
37 * go awry because the system isn't in a functional state.
38 */
39 local_irq_disable();
40
41 /*
42 * Mask all interrupts, giving us a better chance of remaining in the
43 * low power wait state.
44 */
45 clear_c0_status(ST0_IM);
46
47 while (true) {
48 if (cpu_has_mips_r) {
49 /*
50 * We know that the wait instruction is supported so
51 * make use of it directly, leaving interrupts
52 * disabled.
53 */
54 asm volatile(
55 ".set push\n\t"
56 ".set " MIPS_ISA_ARCH_LEVEL "\n\t"
57 "wait\n\t"
58 ".set pop");
59 } else if (cpu_wait) {
60 /*
61 * Try the cpu_wait() callback. This isn't ideal since
62 * it'll re-enable interrupts, but that ought to be
63 * harmless given that they're all masked.
64 */
65 cpu_wait();
66 local_irq_disable();
67 } else {
68 /*
69 * We're going to burn some power running round the
70 * loop, but we don't really have a choice. This isn't
71 * a path we should expect to run for long during
72 * typical use anyway.
73 */
74 }
75
76 /*
77 * In most modern MIPS CPUs interrupts will cause the wait
78 * instruction to graduate even when disabled, and in some
79 * cases even when masked. In order to prevent a timer
80 * interrupt from continuously taking us out of the low power
81 * wait state, we clear any pending timer interrupt here.
82 */
83 if (cpu_has_counter)
84 write_c0_compare(0);
85 }
86}
87
29void machine_restart(char *command) 88void machine_restart(char *command)
30{ 89{
31 if (_machine_restart) 90 if (_machine_restart)
@@ -38,8 +97,7 @@ void machine_restart(char *command)
38 do_kernel_restart(command); 97 do_kernel_restart(command);
39 mdelay(1000); 98 mdelay(1000);
40 pr_emerg("Reboot failed -- System halted\n"); 99 pr_emerg("Reboot failed -- System halted\n");
41 local_irq_disable(); 100 machine_hang();
42 while (1);
43} 101}
44 102
45void machine_halt(void) 103void machine_halt(void)
@@ -51,8 +109,7 @@ void machine_halt(void)
51 preempt_disable(); 109 preempt_disable();
52 smp_send_stop(); 110 smp_send_stop();
53#endif 111#endif
54 local_irq_disable(); 112 machine_hang();
55 while (1);
56} 113}
57 114
58void machine_power_off(void) 115void machine_power_off(void)
@@ -64,6 +121,5 @@ void machine_power_off(void)
64 preempt_disable(); 121 preempt_disable();
65 smp_send_stop(); 122 smp_send_stop();
66#endif 123#endif
67 local_irq_disable(); 124 machine_hang();
68 while (1);
69} 125}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 5f8b0a9e30b3..563188ac6fa2 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -155,7 +155,8 @@ void __init detect_memory_region(phys_addr_t start, phys_addr_t sz_min, phys_add
155 add_memory_region(start, size, BOOT_MEM_RAM); 155 add_memory_region(start, size, BOOT_MEM_RAM);
156} 156}
157 157
158bool __init memory_region_available(phys_addr_t start, phys_addr_t size) 158static bool __init __maybe_unused memory_region_available(phys_addr_t start,
159 phys_addr_t size)
159{ 160{
160 int i; 161 int i;
161 bool in_ram = false, free = true; 162 bool in_ram = false, free = true;
@@ -453,7 +454,7 @@ static void __init bootmem_init(void)
453 pr_info("Wasting %lu bytes for tracking %lu unused pages\n", 454 pr_info("Wasting %lu bytes for tracking %lu unused pages\n",
454 (min_low_pfn - ARCH_PFN_OFFSET) * sizeof(struct page), 455 (min_low_pfn - ARCH_PFN_OFFSET) * sizeof(struct page),
455 min_low_pfn - ARCH_PFN_OFFSET); 456 min_low_pfn - ARCH_PFN_OFFSET);
456 } else if (min_low_pfn < ARCH_PFN_OFFSET) { 457 } else if (ARCH_PFN_OFFSET - min_low_pfn > 0UL) {
457 pr_info("%lu free pages won't be used\n", 458 pr_info("%lu free pages won't be used\n",
458 ARCH_PFN_OFFSET - min_low_pfn); 459 ARCH_PFN_OFFSET - min_low_pfn);
459 } 460 }
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 84b7b592b834..400676ce03f4 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -30,7 +30,6 @@
30#include <linux/hardirq.h> 30#include <linux/hardirq.h>
31#include <linux/gfp.h> 31#include <linux/gfp.h>
32#include <linux/kcore.h> 32#include <linux/kcore.h>
33#include <linux/export.h>
34#include <linux/initrd.h> 33#include <linux/initrd.h>
35 34
36#include <asm/asm-offsets.h> 35#include <asm/asm-offsets.h>
@@ -46,7 +45,6 @@
46#include <asm/pgalloc.h> 45#include <asm/pgalloc.h>
47#include <asm/tlb.h> 46#include <asm/tlb.h>
48#include <asm/fixmap.h> 47#include <asm/fixmap.h>
49#include <asm/maar.h>
50 48
51/* 49/*
52 * We have up to 8 empty zeroed pages so we can map one of the right colour 50 * We have up to 8 empty zeroed pages so we can map one of the right colour
diff --git a/arch/mips/net/bpf_jit_asm.S b/arch/mips/net/bpf_jit_asm.S
index 88a2075305d1..57154c5883b6 100644
--- a/arch/mips/net/bpf_jit_asm.S
+++ b/arch/mips/net/bpf_jit_asm.S
@@ -11,6 +11,7 @@
11 */ 11 */
12 12
13#include <asm/asm.h> 13#include <asm/asm.h>
14#include <asm/isa-rev.h>
14#include <asm/regdef.h> 15#include <asm/regdef.h>
15#include "bpf_jit.h" 16#include "bpf_jit.h"
16 17
@@ -65,7 +66,7 @@ FEXPORT(sk_load_word_positive)
65 lw $r_A, 0(t1) 66 lw $r_A, 0(t1)
66 .set noreorder 67 .set noreorder
67#ifdef CONFIG_CPU_LITTLE_ENDIAN 68#ifdef CONFIG_CPU_LITTLE_ENDIAN
68# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 69# if MIPS_ISA_REV >= 2
69 wsbh t0, $r_A 70 wsbh t0, $r_A
70 rotr $r_A, t0, 16 71 rotr $r_A, t0, 16
71# else 72# else
@@ -92,7 +93,7 @@ FEXPORT(sk_load_half_positive)
92 PTR_ADDU t1, $r_skb_data, offset 93 PTR_ADDU t1, $r_skb_data, offset
93 lhu $r_A, 0(t1) 94 lhu $r_A, 0(t1)
94#ifdef CONFIG_CPU_LITTLE_ENDIAN 95#ifdef CONFIG_CPU_LITTLE_ENDIAN
95# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 96# if MIPS_ISA_REV >= 2
96 wsbh $r_A, $r_A 97 wsbh $r_A, $r_A
97# else 98# else
98 sll t0, $r_A, 8 99 sll t0, $r_A, 8
@@ -170,7 +171,7 @@ FEXPORT(sk_load_byte_positive)
170NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp) 171NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
171 bpf_slow_path_common(4) 172 bpf_slow_path_common(4)
172#ifdef CONFIG_CPU_LITTLE_ENDIAN 173#ifdef CONFIG_CPU_LITTLE_ENDIAN
173# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 174# if MIPS_ISA_REV >= 2
174 wsbh t0, $r_s0 175 wsbh t0, $r_s0
175 jr $r_ra 176 jr $r_ra
176 rotr $r_A, t0, 16 177 rotr $r_A, t0, 16
@@ -196,7 +197,7 @@ NESTED(bpf_slow_path_word, (6 * SZREG), $r_sp)
196NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp) 197NESTED(bpf_slow_path_half, (6 * SZREG), $r_sp)
197 bpf_slow_path_common(2) 198 bpf_slow_path_common(2)
198#ifdef CONFIG_CPU_LITTLE_ENDIAN 199#ifdef CONFIG_CPU_LITTLE_ENDIAN
199# if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 200# if MIPS_ISA_REV >= 2
200 jr $r_ra 201 jr $r_ra
201 wsbh $r_A, $r_s0 202 wsbh $r_A, $r_s0
202# else 203# else
diff --git a/arch/mips/pci/pci-mt7620.c b/arch/mips/pci/pci-mt7620.c
index 407f155f0bb6..f6b77788124a 100644
--- a/arch/mips/pci/pci-mt7620.c
+++ b/arch/mips/pci/pci-mt7620.c
@@ -315,6 +315,7 @@ static int mt7620_pci_probe(struct platform_device *pdev)
315 break; 315 break;
316 316
317 case MT762X_SOC_MT7628AN: 317 case MT762X_SOC_MT7628AN:
318 case MT762X_SOC_MT7688:
318 if (mt7628_pci_hw_init(pdev)) 319 if (mt7628_pci_hw_init(pdev))
319 return -1; 320 return -1;
320 break; 321 break;
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index f5b367e20dff..31955c1d5555 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -319,7 +319,7 @@ static void __init rbtx4927_mtd_init(void)
319 319
320static void __init rbtx4927_gpioled_init(void) 320static void __init rbtx4927_gpioled_init(void)
321{ 321{
322 static struct gpio_led leds[] = { 322 static const struct gpio_led leds[] = {
323 { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, }, 323 { .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
324 { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, }, 324 { .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
325 }; 325 };
diff --git a/arch/mips/vdso/elf.S b/arch/mips/vdso/elf.S
index be37bbb1f061..428a1917afc6 100644
--- a/arch/mips/vdso/elf.S
+++ b/arch/mips/vdso/elf.S
@@ -10,6 +10,8 @@
10 10
11#include "vdso.h" 11#include "vdso.h"
12 12
13#include <asm/isa-rev.h>
14
13#include <linux/elfnote.h> 15#include <linux/elfnote.h>
14#include <linux/version.h> 16#include <linux/version.h>
15 17
@@ -40,11 +42,7 @@ __mips_abiflags:
40 .byte __mips /* isa_level */ 42 .byte __mips /* isa_level */
41 43
42 /* isa_rev */ 44 /* isa_rev */
43#ifdef __mips_isa_rev 45 .byte MIPS_ISA_REV
44 .byte __mips_isa_rev
45#else
46 .byte 0
47#endif
48 46
49 /* gpr_size */ 47 /* gpr_size */
50#ifdef __mips64 48#ifdef __mips64
@@ -54,7 +52,7 @@ __mips_abiflags:
54#endif 52#endif
55 53
56 /* cpr1_size */ 54 /* cpr1_size */
57#if (defined(__mips_isa_rev) && __mips_isa_rev >= 6) || defined(__mips64) 55#if (MIPS_ISA_REV >= 6) || defined(__mips64)
58 .byte 2 /* AFL_REG_64 */ 56 .byte 2 /* AFL_REG_64 */
59#else 57#else
60 .byte 1 /* AFL_REG_32 */ 58 .byte 1 /* AFL_REG_32 */
diff --git a/crypto/Kconfig b/crypto/Kconfig
index c0dabed5122e..76e8c88c97b4 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -500,6 +500,15 @@ config CRYPTO_CRC32_PCLMUL
500 which will enable any routine to use the CRC-32-IEEE 802.3 checksum 500 which will enable any routine to use the CRC-32-IEEE 802.3 checksum
501 and gain better performance as compared with the table implementation. 501 and gain better performance as compared with the table implementation.
502 502
503config CRYPTO_CRC32_MIPS
504 tristate "CRC32c and CRC32 CRC algorithm (MIPS)"
505 depends on MIPS_CRC_SUPPORT
506 select CRYPTO_HASH
507 help
508 CRC32c and CRC32 CRC algorithms implemented using mips crypto
509 instructions, when available.
510
511
503config CRYPTO_CRCT10DIF 512config CRYPTO_CRCT10DIF
504 tristate "CRCT10DIF algorithm" 513 tristate "CRCT10DIF algorithm"
505 select CRYPTO_HASH 514 select CRYPTO_HASH
diff --git a/drivers/firmware/broadcom/Kconfig b/drivers/firmware/broadcom/Kconfig
index 3c7e5b741e37..f77cdb3a041f 100644
--- a/drivers/firmware/broadcom/Kconfig
+++ b/drivers/firmware/broadcom/Kconfig
@@ -13,6 +13,7 @@ config BCM47XX_NVRAM
13config BCM47XX_SPROM 13config BCM47XX_SPROM
14 bool "Broadcom SPROM driver" 14 bool "Broadcom SPROM driver"
15 depends on BCM47XX_NVRAM 15 depends on BCM47XX_NVRAM
16 select GENERIC_NET_UTILS
16 help 17 help
17 Broadcom devices store configuration data in SPROM. Accessing it is 18 Broadcom devices store configuration data in SPROM. Accessing it is
18 specific to the bus host type, e.g. PCI(e) devices have it mapped in 19 specific to the bus host type, e.g. PCI(e) devices have it mapped in
diff --git a/drivers/firmware/broadcom/bcm47xx_sprom.c b/drivers/firmware/broadcom/bcm47xx_sprom.c
index 62aa3cf09b4d..4787f86c8ac1 100644
--- a/drivers/firmware/broadcom/bcm47xx_sprom.c
+++ b/drivers/firmware/broadcom/bcm47xx_sprom.c
@@ -137,20 +137,6 @@ static void nvram_read_leddc(const char *prefix, const char *name,
137 *leddc_off_time = (val >> 16) & 0xff; 137 *leddc_off_time = (val >> 16) & 0xff;
138} 138}
139 139
140static void bcm47xx_nvram_parse_macaddr(char *buf, u8 macaddr[6])
141{
142 if (strchr(buf, ':'))
143 sscanf(buf, "%hhx:%hhx:%hhx:%hhx:%hhx:%hhx", &macaddr[0],
144 &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
145 &macaddr[5]);
146 else if (strchr(buf, '-'))
147 sscanf(buf, "%hhx-%hhx-%hhx-%hhx-%hhx-%hhx", &macaddr[0],
148 &macaddr[1], &macaddr[2], &macaddr[3], &macaddr[4],
149 &macaddr[5]);
150 else
151 pr_warn("Can not parse mac address: %s\n", buf);
152}
153
154static void nvram_read_macaddr(const char *prefix, const char *name, 140static void nvram_read_macaddr(const char *prefix, const char *name,
155 u8 val[6], bool fallback) 141 u8 val[6], bool fallback)
156{ 142{
@@ -161,7 +147,9 @@ static void nvram_read_macaddr(const char *prefix, const char *name,
161 if (err < 0) 147 if (err < 0)
162 return; 148 return;
163 149
164 bcm47xx_nvram_parse_macaddr(buf, val); 150 strreplace(buf, '-', ':');
151 if (!mac_pton(buf, val))
152 pr_warn("Can not parse mac address: %s\n", buf);
165} 153}
166 154
167static void nvram_read_alpha2(const char *prefix, const char *name, 155static void nvram_read_alpha2(const char *prefix, const char *name,
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-25 02:31:23 -0400