litmus-rt-ext-res.git/net/dsa/Makefile, branch EXT-RES

net-next: dsa: add Qualcomm tag RX/TX handler

2016-09-16T08:31:51+00:00

Add support for the 2-bytes Qualcomm tag that gigabit switches such as
the QCA8337/N might insert when receiving packets, or that we need
to insert while targeting specific switch ports. The tag is inserted
directly behind the ethernet header.

Reviewed-by: Andrew Lunn 
Reviewed-by: Florian Fainelli 
Signed-off-by: John Crispin 
Signed-off-by: David S. Miller

net: dsa: Add new binding implementation

2016-06-04T21:29:55+00:00

The existing DSA binding has a number of limitations and problems. The
main problem is that it cannot represent a switch as a linux device,
hanging off some bus. It is limited to one CPU port. The DSA platform
device is artificial, and does not really represent hardware.

Implement a new binding which can be embedded into any type of node on
a bus to represent one switch device, and its links to other switches.

Signed-off-by: Andrew Lunn 
Signed-off-by: Florian Fainelli 
Signed-off-by: David S. Miller

net: dsa: add Broadcom tag RX/TX handler

2014-08-28T05:59:40+00:00

Add support for the 4-bytes Broadcom tag that built-in switches such as
the Starfighter 2 might insert when receiving packets, or that we need
to insert while targetting specific switch ports. We use a fake local
EtherType value for this 4-bytes switch tag: ETH_P_BRCMTAG to make sure
we can assign DSA-specific network operations within the DSA drivers.

Signed-off-by: Florian Fainelli 
Signed-off-by: David S. Miller

dsa: Move switch drivers to new directory drivers/net/dsa

2011-11-29T05:21:36+00:00

Support for specific hardware belongs under drivers/net/ not net/.

Signed-off-by: Ben Hutchings 
Acked-by: Lennert Buytenhek 
Signed-off-by: David S. Miller

dsa: Allow core and drivers to be built as modules

2011-11-26T19:48:16+00:00

Change the kconfig types to tristate and adjust the condition for
declaring net_device::dsa_ptr to allow for this.

Adjust the makefile so that if NET_DSA_MV88E6123_61_65=y and
NET_DSA_MV88E6131=m or vice versa then both drivers are built-in.  We
could leave these options as bool and make NET_DSA_MV88E6XXX a
user-selected option, but that would break existing configurations.

Signed-off-by: Ben Hutchings 
Signed-off-by: David S. Miller

mv88e6xxx: Combine mv88e6131 and mv88e612_61_65 drivers

2011-11-26T19:48:15+00:00

These drivers share a lot of code, so if we make them modular they
should be built into the same module.  Therefore, link them together
and merge their respective module init and exit functions.

Signed-off-by: Ben Hutchings 
Signed-off-by: David S. Miller

dsa: Combine core and tagging code

2011-11-26T19:48:15+00:00

These files have circular dependencies, so if we make DSA modular then
they must be built into the same module.  Therefore, link them
together and merge their respective module init and exit functions.

Signed-off-by: Ben Hutchings 
Signed-off-by: David S. Miller

dsa: add support for the Marvell 88E6060 switch chip

2008-10-09T00:24:22+00:00

Add support for the Marvell 88E6060 switch chip.  This chip only
supports the Header and Trailer tagging formats, and we use it in
Trailer mode since that mode is slightly easier to handle than
Header mode.

Signed-off-by: Lennert Buytenhek 
Tested-by: Byron Bradley 
Tested-by: Tim Ellis 
Signed-off-by: David S. Miller

dsa: add support for Trailer tagging format

2008-10-09T00:24:16+00:00

This adds support for the Trailer switch tagging format.  This is
another tagging that doesn't explicitly mark tagged packets with a
distinct ethertype, so that we need to add a similar hack in the
receive path as for the Original DSA tagging format.

Signed-off-by: Lennert Buytenhek 
Tested-by: Byron Bradley 
Tested-by: Tim Ellis 
Signed-off-by: David S. Miller

dsa: add support for the Marvell 88E6131 switch chip

2008-10-09T00:24:09+00:00

Add support for the Marvell 88E6131 switch chip.  This chip only
supports the original (ethertype-less) DSA tagging format.

On the 88E6131, there is a PHY Polling Unit (PPU) which has exclusive
access to each of the PHYs's MII management registers.  If we want to
talk to the PHYs from software, we have to disable the PPU and wait
for it to complete its current transaction before we can do so, and we
need to re-enable the PPU afterwards to make sure that the switch will
notice changes in link state and speed on the individual ports as they
occur.

Since disabling the PPU is rather slow, and since MII management
accesses are typically done in bursts, this patch keeps the PPU disabled
for 10ms after a software access completes.  This makes handling the
PPU slightly more complex, but speeds up something like running ethtool
on one of the switch slave interfaces from ~300ms to ~30ms on typical
hardware.

Signed-off-by: Lennert Buytenhek 
Tested-by: Nicolas Pitre 
Tested-by: Peter van Valderen 
Tested-by: Dirk Teurlings 
Signed-off-by: David S. Miller