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<title>litmus-rt-ext-res.git/drivers/dma/xilinx/Makefile, branch EXT-RES</title>
<subtitle>LITMUS^RT with extended reservations for Forbidden Zones paper @ RTAS'20</subtitle>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-ext-res.git/'/>
<entry>
<title>dmaengine: Add Xilinx zynqmp dma engine driver support</title>
<updated>2016-07-08T05:55:34+00:00</updated>
<author>
<name>Kedareswara rao Appana</name>
<email>appana.durga.rao@xilinx.com</email>
</author>
<published>2016-07-01T11:37:06+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-ext-res.git/commit/?id=b0cc417c1637192be658e68a74c8d1568e3d35f6'/>
<id>b0cc417c1637192be658e68a74c8d1568e3d35f6</id>
<content type='text'>
Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and I/O to I/O buffer transfers.

Signed-off-by: Kedareswara rao Appana &lt;appanad@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
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<pre>
Added the driver for zynqmp dma engine used in Zynq
UltraScale+ MPSoC. This dma controller supports memory to memory
and I/O to I/O buffer transfers.

Signed-off-by: Kedareswara rao Appana &lt;appanad@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dmaengine: xilinx: Rename driver and config</title>
<updated>2016-07-08T05:21:35+00:00</updated>
<author>
<name>Kedareswara rao Appana</name>
<email>appana.durga.rao@xilinx.com</email>
</author>
<published>2016-06-24T05:21:25+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-ext-res.git/commit/?id=fde57a7c4474b2d00b7b82b94aa2dd0160b1bbee'/>
<id>fde57a7c4474b2d00b7b82b94aa2dd0160b1bbee</id>
<content type='text'>
In the existing vdma driver support for
AXI DMA and CDMA got added so the driver is no
longer VDMA specific.

This patch renames the driver and DT binding doc to xilinx_dma
and updates the Kconfig description for all the DMAS.

Signed-off-by: Kedareswara rao Appana &lt;appanad@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
In the existing vdma driver support for
AXI DMA and CDMA got added so the driver is no
longer VDMA specific.

This patch renames the driver and DT binding doc to xilinx_dma
and updates the Kconfig description for all the DMAS.

Signed-off-by: Kedareswara rao Appana &lt;appanad@xilinx.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dma: Add Xilinx AXI Video Direct Memory Access Engine driver support</title>
<updated>2014-04-30T05:14:13+00:00</updated>
<author>
<name>Srikanth Thokala</name>
<email>sthokal@xilinx.com</email>
</author>
<published>2014-04-23T14:53:26+00:00</published>
<link rel='alternate' type='text/html' href='http://rtsrv.cs.unc.edu/cgit/cgit.cgi/litmus-rt-ext-res.git/commit/?id=9cd4360de6090a6daf7fbe024e34953f2ae60ef2'/>
<id>9cd4360de6090a6daf7fbe024e34953f2ae60ef2</id>
<content type='text'>
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient two
dimensional DMA operations with independent asynchronous read
and write channel operation.

This module works on Zynq (ARM Based SoC) and Microblaze platforms.

Signed-off-by: Srikanth Thokala &lt;sthokal@xilinx.com&gt;
Acked-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
Reviewed-by: Levente Kurusa &lt;levex@linux.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This is the driver for the AXI Video Direct Memory Access (AXI
VDMA) core, which is a soft Xilinx IP core that provides high-
bandwidth direct memory access between memory and AXI4-Stream
type video target peripherals. The core provides efficient two
dimensional DMA operations with independent asynchronous read
and write channel operation.

This module works on Zynq (ARM Based SoC) and Microblaze platforms.

Signed-off-by: Srikanth Thokala &lt;sthokal@xilinx.com&gt;
Acked-by: Jassi Brar &lt;jassisinghbrar@gmail.com&gt;
Reviewed-by: Levente Kurusa &lt;levex@linux.com&gt;
Signed-off-by: Vinod Koul &lt;vinod.koul@intel.com&gt;
</pre>
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</content>
</entry>
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