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* | net: dsa: rename switch operations structureVivien Didelot2016-08-25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that the dsa_switch_driver structure contains only function pointers as it is supposed to, rename it to the more appropriate dsa_switch_ops, uniformly to any other operations structure in the kernel. No functional changes here, basically just the result of something like: s/dsa_switch_driver *drv/dsa_switch_ops *ops/g However keep the {un,}register_switch_driver functions and their dsa_switch_drivers list as is, since they represent the -- likely to be deprecated soon -- legacy DSA registration framework. In the meantime, also fix the following checks from checkpatch.pl to make it happy with this patch: CHECK: Comparison to NULL could be written "!ops" #403: FILE: net/dsa/dsa.c:470: + if (ops == NULL) { CHECK: Comparison to NULL could be written "ds->ops->get_strings" #773: FILE: net/dsa/slave.c:697: + if (ds->ops->get_strings != NULL) CHECK: Comparison to NULL could be written "ds->ops->get_ethtool_stats" #824: FILE: net/dsa/slave.c:785: + if (ds->ops->get_ethtool_stats != NULL) CHECK: Comparison to NULL could be written "ds->ops->get_sset_count" #835: FILE: net/dsa/slave.c:798: + if (ds->ops->get_sset_count != NULL) total: 0 errors, 0 warnings, 4 checks, 784 lines checked Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: mv88e6xxx: Enable PORT_CONTROL_FORWARD_UNKNOWN for DSA-tagged CPU portsJamie Lentin2016-08-23
| | | | | | | | | | | | | | | | | | Without it, a mv88e6131 switch will not forward incoming unicast packets to the CPU port. Signed-off-by: Jamie Lentin <jm@lentin.co.uk> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | dsa: mv88e6xxx: Delete ppu timer when removing moduleAndrew Lunn2016-08-23
| | | | | | | | | | | | | | | | | | | | The PPU method of accessing PHYs makes use of a timer. Make sure this timer is deleted before unloading the driver. Reported-by: Jamie Lentin <jm@lentin.co.uk> Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: Fix support for DSA tagging for older switches.Andrew Lunn2016-08-23
| | | | | | | | | | | | | | | | | | | | Older chips only support DSA tagging on the CPU port. New devices support both DSA and EDSA. The driver needs to tell the core the tag protocol to use, and configure the switch for what is available. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: Allow the DSA driver to indicate the tag protocolAndrew Lunn2016-08-23
| | | | | | | | | | | | | | | | | | | | DSA drivers may drive different families of switches which need different tag protocol. Rather than hard code the tag protocol in the driver structure, have a callback for the DSA core to call. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: bcm_sf2: Remove probing through old DSA bindingFlorian Fainelli2016-08-19
| | | | | | | | | | | | | | | | | | | | Remove our dsa_switch_driver::drv_probe callback to prevent probing through the old DSA binding, not that this could happen anymore now that we have moved the matching compatible string from net/dsa/dsa.c to drivers/net/dsa/bcm_sf2.c, so this is essentially dead code. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: bcm_sf2: Use device managed helpersFlorian Fainelli2016-08-19
| | | | | | | | | | | | | | | | | | Now that we have converted the drivers into a proper platform device driver, we can use the device managed helper functions to simplify the error paths a bit wrt. register resources and IRQs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: bcm_sf2: Make it a real platform device driverFlorian Fainelli2016-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom Starfighter 2 switch driver should be a proper platform driver, now that the DSA code has been updated to allow that, register a switch device, feed it with the proper configuration data coming from Device Tree and register our switch device with DSA. The bulk of the changes consist in moving what bcm_sf2_sw_setup() did into the platform driver probe function. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | dsa: mv88e6xxx: Make mv88e6xxx_wait() timeout verboseAndrew Lunn2016-08-19
| | | | | | | | | | | | | | | | When mv88e6xxx_wait() returns a timeout, something bad has happened. Make sure it is noticed by logging an error. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | dsa: mv88e6xxx: Use mv88e6xx_wait in mv88e6xxx_update()Andrew Lunn2016-08-19
| | | | | | | | | | | | | | | | | | Now that mv88e6xx_wait() iterated on a counter than a fixed time interval, it implements the same mechanism as mv88e6xxx_update() uses. So use it in mv88e6xx_wait(). Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | dsa: mv88e6xxx: Timeout based on iterations, not timeAndrew Lunn2016-08-19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mv88e6xxx driver times out operations on the switch based on looping until an elapsed wall clock time is reached. However, if usleep_range() sleeps much longer than expected, it could timeout with an error without actually checking to see if the devices has completed the operation. So replace the elapsed time with a fixed upper bound on the number of loops. Testing on various switches has shown that switches takes either 0 or 1 iteration, so a maximum of 16 iterations is a safe limit. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: use the new PHY APIVivien Didelot2016-08-15
| | | | | | | | | | | | | | | | | | | | | | This commit replaces every MDIO direct or indirect access with the new generic mv88e6xxx_phy_* routines. This allows us to get rid of the mv88e6xxx_mdio_{read,write}_{,in}direct and {_,}mv88e6xxx_mdio_page_{read,write} functions. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: describe PHY page and SerDesVivien Didelot2016-08-15
| | | | | | | | | | | | | | | | Add mv88e6xxx_phy_page_{read,write} routines and use them to access the SerDes PHY device registers. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: abstract PHY opsVivien Didelot2016-08-15
| | | | | | | | | | | | | | | | | | | | | | | | | | Old chips use a direct access to the PHY devices registers. Next chips have a PHY Polling Unit (PPU) which needs to be disabled before accessing PHY registers. Newer chips have an indirect access to the PHY devices so that disabling the PPU is not necessary. Introduce a new phy_ops structure in the chip to describe the required PHY access routines. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: rework Global2 SMI PHY accessVivien Didelot2016-08-15
| | | | | | | | | | | | | | | | | | | | | | | | Describe the presence of the Global2 SMI PHY registers, used to indirectly access the internal SMI devices registers on some chips. Also temporarily forward declare mv88e6xxx_g2_smi_phy_{read,write} to use them in mv88e6xxx_mdio_{read,write}_indirect, before getting rid of the later. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: describe Multi-chip registersVivien Didelot2016-08-15
| | | | | | | | | | | | | | | | | | Add flags to describe the presence of SMI Command and Data registers used to indirectly access internal SMI devices registers when the switch SMI address is not zero. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: mv88e6xxx: rename _mv88e6xxx_waitVivien Didelot2016-08-15
| | | | | | | | | | | | | | | | Now that there is no locked version of the wait routine anymore, rename the _ prefixed version and make it use the new read API. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: b53: remove .owner and .bus fields for driverWei Yongjun2016-08-15
| | | | | | | | | | | | | | | | | | | | Remove .owner and .bus fields since module_spi_driver() is used which set them automatically. Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* | net: dsa: b53: constify b53_io_ops structuresJulia Lawall2016-08-09
|/ | | | | | | | | | The b53_io_ops structures are never modified, so declare them as const. Done with the help of Coccinelle. Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Acked-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: b53: Add missing ULL suffix for 64-bit constantGeert Uytterhoeven2016-08-06
| | | | | | | | | | | On 32-bit (e.g. with m68k-linux-gnu-gcc-4.1): drivers/net/dsa/b53/b53_common.c: In function ‘b53_arl_read’: drivers/net/dsa/b53/b53_common.c:1072: warning: integer constant is too large for ‘long’ type Fixes: 1da6df85c6fbed8f ("net: dsa: b53: Implement ARL add/del/dump operations") Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: David S. Miller <davem@davemloft.net>
* dsa: b53: remove redundant ifxypron.glpk@gmx.de2016-08-01
| | | | | | | | For pdata == null the code leaves with an error. There is no need to check the condition again. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: bcm_sf2: Unwind errors in correct orderFlorian Fainelli2016-07-31
| | | | | | | | | | | | | In case we cannot complete bcm_sf2_sw_setup() for any reason, and we go to the out_unmap label, but the MDIO bus has not been registered yet, we will hit the BUG condition in drivers/net/phy/mdio_bus.c about the bus not being registered. Fix this by dedicating a specific lable for when we fail after the MDIO bus has been successfully registered. Fixes: 461cd1b03e32 ("net: dsa: bcm_sf2: Register our slave MDIO bus") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: kill last locked reg_readVivien Didelot2016-07-21
| | | | | | | | | | Get rid of the last usage of the locked mv88e6xxx_reg_read function with a new mv88e6xxx_port_read helper, useful later for chips with different port registers base address. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: rework EEPROM accessVivien Didelot2016-07-21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 6352 family of switches and compatibles provide a 8-bit address and 16-bit data access to an optional EEPROM. Newer chip such as the 6390 family slightly changed the access to 16-bit address and 8-bit data. This commit cleans up the EEPROM access code for 16-bit access and makes it easy to eventually introduce future support for 8-bit access. Here's a list of notable changes brought by this patch: - provide Global2 unlocked helpers for EEPROM commands - remove eeprom_mutex, only reg_lock is necessary for driver functions - eeprom_len is 0 for chip without EEPROM, so return it directly - the Running bit must be 0 before r/w, so wait for Busy *and* Running - remove now unused mv88e6xxx_wait and mv88e6xxx_reg_write - other than that, the logic (in _{get,set}_eeprom16) didn't change Chips with an 8-bit EEPROM access will require to implement the 8-suffixed variant of G2 helpers and the related flag: #define MV88E6XXX_FLAGS_EEPROM8 \ (MV88E6XXX_FLAG_G2_EEPROM_CMD | \ MV88E6XXX_FLAG_G2_EEPROM_ADDR) Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: remove unused phy_mutexVivien Didelot2016-07-21
| | | | | | | | Only reg_lock is necessary now and phy_mutex is dead. Remove it. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add support for DSA ageing timeVivien Didelot2016-07-19
| | | | | | | | Implement the DSA driver function to configure the bridge ageing time. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add G1 helper for ageing timeVivien Didelot2016-07-19
| | | | | | | | | | | | | | | | All Marvell switch chips from (88E6060 to 88E6390) have a ATU Control register containing bits 11:4 to configure an ATU Age Time quotient. However the coefficient used to calculate the ATU Age Time vary with the models. E.g. 88E6060, 88E6352 and 88E6390 use respectively 16, 15 and 3.75 seconds. Add a age_time_coeff to the info structure to handle this and a Global 1 helper to set the default age time of 5 minutes in the setup code. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add cap for IRLVivien Didelot2016-07-19
| | | | | | | | | | | | | | Add capability flags to describe the presence of Ingress Rate Limit unit registers and an helper function to clear it. In the meantime, fix a few harmless issues: - 6185 and 6095 don't have such registers (reserved) - the previous code didn't wait for the IRL operation to complete Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add cap for Priority OverrideVivien Didelot2016-07-19
| | | | | | | | | Add flags and helpers to describe the presence of Priority Override Table (POT) related registers and simplify the setup of Global 2. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add cap for PVTVivien Didelot2016-07-19
| | | | | | | | | Add flags to describe the presence of Cross-chip Port VLAN Table (PVT) related registers and simplify the setup of Global 2. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: rework Switch MAC setterVivien Didelot2016-07-19
| | | | | | | | | | | | | | | | | Switches such as 88E6185 as 3 Switch MAC registers in Global 1. Newer chips such as 88E6352 have freed these registers in favor of an indirect access in a Switch MAC/WoL/WoF register in Global 2. Explicit this difference with G1 and G2 helpers and flags. Also, note that this indirect access is a single-register which doesn't require to wait for the operation to complete (like Switch MAC, Trunk Mapping, etc.), in contrary to multi-registers indirect accesses with several operations and a busy bit. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add cap for MGMT Enables bitsVivien Didelot2016-07-19
| | | | | | | | | | | | | | | | | | | | | | | | | | Some switches provide a Rsvd2CPU mechanism used to choose which of the 16 reserved multicast destination addresses matching 01:80:c2:00:00:0x should be considered as MGMT and thus forwarded to the CPU port. Other switches extend this mechanism to also configure as MGMT the additional 16 reserved multicast addresses matching 01:80:c2:00:00:2x. This mechanism is exposed via two registers in Global 2, and an Rsvd2CPU enable bit in the management register. Newer chip (such as 88E6390) has replaced these registers with a new indirect MGMT mechanism in Global 1. The patch adds two MV88E6XXX_FLAG_G2_MGMT_EN_{0,2}X flags to describe the presence of these Global 2 registers. If 88E6390 support is added, a MV88E6XXX_FLAG_G1_MGMT_CTRL flag will be needed to setup Rsvd2CPU. Note: all switches still support in parallel the ATU Load operation with an MGMT Entry State to forward such frames in a less convenient way. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: extract trunk mappingVivien Didelot2016-07-19
| | | | | | | | | | | The Trunk Mask and Trunk Mapping registers are two Global 2 indirect accesses to trunking configuration. Add helpers for these tables and simplify the Global 2 setup. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: extract device mappingVivien Didelot2016-07-19
| | | | | | | | | | | The Device Mapping register is an indirect table access. Provide helpers to access this table and explicit the checking of the new DSA_RTABLE_NONE routing table value. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: split setup of Global 1 and 2Vivien Didelot2016-07-19
| | | | | | | | | | | Separate the setup of Global 1 and Global 2 internal SMI devices and add a flag to describe the presence of this second registers set. Also rearrange the G1 setup in the registers order. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: remove basic function flagsVivien Didelot2016-07-19
| | | | | | | | | | | | | | | All 88E6xxx Marvell switches (even the old not supported yet 88E6060) have at least an ATU, per-port STP states and VLAN map, to run basic switch functions such as Spanning Tree and port based VLANs. Get rid of the related MV88E6XXX_FLAG_{ATU,PORTSTATE,VLANTABLE} flags, as they are defaults to every chip. This enables STP on 6185 and removes many inconsistencies on others. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* b53: Fix build warning.David S. Miller2016-07-11
| | | | | | | | | | drivers/net/dsa/b53/b53_srab.c: In function 'b53_srab_probe': >> drivers/net/dsa/b53/b53_srab.c:388:20: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] pdata->chip_id = (u32)of_id->data; ^ Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: b53: Add support for BCM585xx/586xx/88312 integrated switchFlorian Fainelli2016-07-11
| | | | | | | | Update the SRAB, core driver and binding document to support the BCM585xx/586xx/88312 integrated switch (Northstar Plus SoCs family). Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: b53: Allow SRAB driver to specify platform dataFlorian Fainelli2016-07-11
| | | | | | | | | | For Northstart Plus SoCs, we cannot detect the switch because only the revision information is provied in the Management page, instead, rely on Device Tree to tell us the chip id, and pass it down using the b53_platform_data structure. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* dsa: b53: avoid 'maybe-uninitialized' warningArnd Bergmann2016-06-29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In some configurations, gcc produces a warning for correct code in this driver: drivers/net/dsa/b53/b53_mmap.c: In function 'b53_mmap_read64': drivers/net/dsa/b53/b53_mmap.c:107:10: error: 'hi' may be used uninitialized in this function [-Werror=maybe-uninitialized] *val = ((u64)hi << 32) | lo; ^~~~~~~ drivers/net/dsa/b53/b53_mmap.c: In function 'b53_mmap_read48': drivers/net/dsa/b53/b53_mmap.c:91:11: error: 'hi' may be used uninitialized in this function [-Werror=maybe-uninitialized] *val = ((u64)hi << 32) | lo; ^~~~~~~ drivers/net/dsa/b53/b53_mmap.c:83:11: error: 'hi' may be used uninitialized in this function [-Werror=maybe-uninitialized] *val = ((u64)hi << 16) | lo; I have seen the warning before and at the time thought I had fixed it with 55e7f6abe131 ("dsa: b53: fix big-endian register access"), however it now came back in a different randconfig build that happens to have different inlining decisions in the compiler. The mistake that gcc makes here is that it thinks the second call to readl() might fail because the address 'reg + 4' is not a multiple of four despite having knowing that 'reg' itself is a multiple of four. By open-coding the two reads without the redundant alignment check, we can avoid the warning and produce slightly better object code, but get slightly longer source code instead. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: rename single-chip supportVivien Didelot2016-06-25
| | | | | | | | | | | | With the upcoming support for cross-chip operations, it will be hard to distinguish portions of code supporting a single-chip or a switch fabric of interconnected chips. Make the code clearer now, by renaming the mv88e6xxx_priv_state chip structure to mv88e6xxx_chip. This patch brings no functional changes. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: move driver in its own folderVivien Didelot2016-06-25
| | | | | | | | | | | | | | With the upcoming support for cross-chip operations and other mv88e6xxx enhancements, new files will be added. Similarly to mlxsw or b53, move mv88e6xxx files into their own folder. In the meantime, update the MAINTAINERS entry to please checkpatch.pl, by replacing the invalid 88E6352 entry with 88E6XXX, maintained by Andrew and myself. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: b53: Fix statistics readingsFlorian Fainelli2016-06-23
| | | | | | | | | | | | | | | | Due to a typo we would always be using the MIB counter width of the first element of the counter array instead of the current element, and we would always be accessing the register statistics with a 64-bits read, while some could be 32-bits. This got unnoticed in testing with MDIO and SRAB which tolerate doing this, but testing with the SPI bus revealed bogus values being returned. Fix this by using the proper iterator here. Fixes: 967dd82ffc52 ("net: dsa: b53: Add support for Broadcom RoboSwitch") Reported-by: Jonas Gorski <jogo@openwrt.org> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: abstract switch registers accessesVivien Didelot2016-06-21
| | | | | | | | | | | | | | | | | | | | | | When the SMI address of the switch chip is zero, the chip assumes to be the only one on the SMI master bus and thus responds to all its known SMI devices addresses (port registers, Global2, etc.) When its SMI address is not zero, some chips (e.g. 88E6352) use an indirect access through two SMI Command and Data registers. Other models (e.g. 88E6060) using less than 16 internal SMI addresses always use a direct access. Add a capability flag to describe chips supporting the (indirect) Multi-chip Addressing Mode, and a low-level API to access the registers via SMI. Other accesses (like Ethernet management frames) may be added later. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add port base address to infoVivien Didelot2016-06-21
| | | | | | | | | | | | | The switch ID is located at address 0x3 of every Port Registers bank. But not all Marvell switches have their Port Registers SMI Addresses starting at 0x10. 88E6060 starts at 0x8 and 88E6390 starts at 0x0. Add this data in the info structure and use it in the detection code. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: pass compatible infoVivien Didelot2016-06-21
| | | | | | | | | | | | | | After allocating the chip structure, pass it a compatible info pointer. The compatible info structure will be used later to describe how to access the switch registers and where to read the switch ID. For the standard MDIO probe, get it from the device node data. For the legacy DSA driver probing, pass it the 88E6085 info. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add detection helperVivien Didelot2016-06-21
| | | | | | | | | Extract the common detection code which assigns the info structure to the chip given the read switch ID. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add SMI init helperVivien Didelot2016-06-21
| | | | | | | | | | | | | | Add an helper function to isolate SMI specific assignments and checks. This function will later help choosing the different SMI accesses based of the compatible info. Since the chip structure is already allocated in the legacy probe, use the mv88e6xxx_reg_read access routine instead of __mv88e6xxx_reg_read. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: add chip allocation helperVivien Didelot2016-06-21
| | | | | | | | | Add an helper function to allocate the chip structure at the beginning of the probe functions. It will be used to initialize the SMI access. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: dsa: mv88e6xxx: rename smi_mutex to reg_lockVivien Didelot2016-06-21
| | | | | | | | | | | | The chip smi_mutex mutex is used to protect the access to the internal switch registers, not only the Multi-chip Addressing Mode, as commented. Since we will isolate SMI-specific pieces of code, avoid the confusion now by renaming smi_mutex to reg_lock. No functional changes here. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
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