| Commit message (Collapse) | Author | Age |
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The GPU code doesn't need to deal with the IOMMU directly, instead
it can all be hidden behind the etnaviv mmu interface. Move the
last remaining part into etnaviv mmu.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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So we can call the v2 restore code once it is there.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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It is only relevant for the V1 MMU, so we should not do this in the
common code.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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This function has external visibility and only handles the Vivant IOMMU
version 1. Rename to make this more clear and allow a clear separation
of the different IOMMU versions.
Also drop the domain parameter, as we can infer it from the GPU we are
dealing with.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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There is no linear window on MMUv2 and the FE can access the full 4GB
address space either directly (as long as the MMU isn't configured) or
through the MMU, once it is up.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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As the comment above the code states, the linear window is only
available on MMUv1. Don't try to use it on MMUv2.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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The driver doesn't ever enable individual clocks alone, so there
is no need to scatter the clock enable/disable sequences through
multiple functions. Fold them into the top one.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
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There is no need to initialize variable 'err' with 0 because it will
be properly assigned later on.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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In the etnaviv_gpu_platform_probe() error path the 'fail' label is
used to just return the error code.
This can be simplified by returning the error code immediately, so
get rid of the unneeded 'fail' label.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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clk_prepare_enable() may fail, so we should better check for its return
value and propagate it in the case of failure.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into drm-next
Allwinner sun4i DRM fixes for 4.9
A few fixes for the sun4i drm driver that range, including some fixes that
might prevent multiple planes from working depending on the sequence where
they are enabled.
* tag 'sunxi-drm-fixes-for-4.9' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
drm/sun4i: Fix the high buffer address mask
drm/sun4i: tv: Check mode pointer
drm/sun4i: Fix formats usable by the primary plane
drm/sun4i: dotclock: Round to closest clock rate
drm/sun4i: Fix sparse warnings
drm/sun4i: dotclock: Allow divider = 127
drm/sun4i: dotclock: Fix clock rate read back calcation
drm/sun4i: backend: remove redundant dev_err call in sun4i_backend_bind()
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The highest 3bits of the 4 layers buffers are all part of the same
register. However, our mask computation was wrong, leading to all the
lowest register bits being removed when we use regmap_update_bits, which
will lead to the buffers being set to some random part of the RAM.
Fix our mask.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The drm_mode_create call might return NULL in case of a failure, and the
current code doesn't check for that. Make sure it does.
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Even though all our planes can support the ARGB formats, the lowest plane
(ie the primary plane) cannot use the alpha component, otherwise it will
just result in the transparent area being entirely black.
Since some applications will still require the ARGB format, let's force the
format to XRGB to drop the alpha component entirely.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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With display pixel clocks we want to have the closest possible clock
rate, to minimize timing and refresh rate skews. Whether the actual
clock rate is higher or lower than the requested rate is less important.
Also check candidates against the requested rate, rather than the
ideal parent rate, the varying dividers also influence the difference
between the requested rate and the rounded rate.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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drm/sun4i/sun4i_tv.c:181:21: warning: symbol 'ntsc_video_levels' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:185:21: warning: symbol 'pal_video_levels' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:189:21: warning: symbol 'ntsc_burst_levels' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:193:21: warning: symbol 'pal_burst_levels' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:197:20: warning: symbol 'ntsc_color_gains' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:201:20: warning: symbol 'pal_color_gains' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:205:26: warning: symbol 'ntsc_resync_parameters' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:209:26: warning: symbol 'pal_resync_parameters' was not declared. Should it be static?
drm/sun4i/sun4i_tv.c:213:16: warning: symbol 'tv_modes' was not declared. Should it be static?
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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The dot clock divider is 7 bits wide, and the divider range is 1 ~ 127,
or 6 ~ 127 if phase offsets are used. The 0 register value also
represents a divider of 1 or bypass.
Make the end condition of the for loop inclusive of 127 in the
round_rate callback.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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When reading back the divider set in the register, we mask off the
bits that aren't part of the divider. Unfortunately the mask used
here was not converted from the field width.
Fix this by converting the field width to a proper bit mask.
Fixes: 9026e0d122ac ("drm: Add Allwinner A10 Display Engine support")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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into drm-next
I've included some improvements to PSR from myself, as well as a great
series from Tomasz to clean up and tighten up vblank/flip handling.
The last patch is one from Tomeu that has been floating around for a
while, and since rockchip is one of the beneficiaries, I figured this
would be a good place to pick it up.
* 'for-next' of ssh://people.freedesktop.org/~seanpaul/dogwood:
drm/rockchip: Balance irq refcount on failure
drm/rockchip: Kill vop_plane_state
drm/rockchip: Always signal event in next vblank after cfg_done
drm/rockchip: Do not enable vblank without event
drm/rockchip: Replace custom wait_for_vblanks with helper
drm/rockchip: Unreference framebuffers from flip work
drm/rockchip: Avoid race with vblank count increment
drm/rockchip: Get rid of some unnecessary code
drm/rockchip: Clear interrupt status bits before enabling
drm/rockchip: Fix up bug in psr state machine
drm/bridge: analogix_dp: Remove duplicated code
drm/rockchip: Reduce psr flush time to 100ms
drm/rockchip: Don't key off vblank for psr
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If create_crtc fails in vop bind, ensure the irq refcount is zeroed
back out before exiting.
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
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After changes introduced by last patches, there is no useful data stored
in vop_plane_state struct. Let's remove it and make the driver use
generic plane state alone.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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This patch makes the driver send the pending vblank event in next vblank
following the commit, relying on vblank signalling improvements done in
previous patches. This gives us vblank events that always represent the
real moment of changes hitting on the screen (which was the case only
for complete FB changes before) and lets us remove the manual window
update check.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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Originally we needed to enable vblank for any atomic commit to kick the
PSR machine, but that was changed and we no longer need to do so from
a vblank interrupt. Let's return to original behavior of enabling
vblank only if it is really necessary.
This essentially reverts commit 5b6804034ae9 ("drm/rockchip: Enable
vblank without event").
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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Currently the driver uses a custom function to wait for flip to complete
after an atomic commit. It was needed before because of two problems:
- there is no hardware vblank counter, so the original helper would
have a race condition with the vblank interrupt,
- the driver didn't support unreferencing cursor framebuffers
asynchronously to the commit, which was what the helper expected.
Since both problems have been solved by previous patches, we can now
make the driver use the generic helper and remove custom waiting code.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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Currently the driver waits for vblank and then unreferences old
framebuffers from atomic commit code path. This is however breaking the
legacy cursor API, which requires the updates to be fully asynchronous.
Instead of just adding a special case for cursor, we can have actually
smaller amount of code to unreference any changed framebuffer from a
flip work.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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Since VOP does not have a hardware vblank count register, the ongoing
commit might be racing with a requested vblank interrupt, which would
increment the software vblank counter before the changes being committed
actually happen.
To avoid this, we can extend .atomic_flush(), so after it sets cfg_done
bit, it polls the vblank interrupt bit until it's inactive to make sure
that any old vblank interrupt gets to the handler and then uses
synchronize_irq(vop->irq) to make sure the handler finishes running.
The polling case should happen very rarely, but even if, the total wait
time should be relatively low and in practice almost equal to the vop
hardirq handler running time.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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Current code implements prepare_fb and cleanup_fb callbacks only to
grab/release fb references, which is already done by atomic framework
when creating/destryoing plane state. Let's remove these
unused bits.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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The enable register only masks the raw status bits to signal CPU
interrupt only for enabled interrupts. The status bits are activated
regardless of the enable register. This means that we might have an old
interrupt event queued, which we are not interested in. To avoid getting
a spurious interrupt signalled, we have to clear the old bit before we
update the enable register.
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
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The ->set() callback would always be called when transitioning
from FLUSH->DISABLE since we assign state to psr->state right
above the skip condition.
Reported-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
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Remove code for reading the EDID and DPCD fields and use the helpers
instead.
Besides the obvious code reduction, other helpers are being added to the
core that could be used in this driver and will be good to be able to
use them instead of duplicating them.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Tested-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Yakir Yang <ykk@rock-chips.com>
Cc: Daniel Vetter <daniel.vetter@intel.com>
Cc: Archit Taneja <architt@codeaurora.org>
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3 seconds is a bit too conservative, drop this to 100ms for
better power savings.
Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
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Instead of keying off vblank for psr, just flush every time
we get an atomic update. This ensures that cursor updates
will properly disable psr (without turning vblank on/off),
and unifies the paths between fb_dirty and atomic psr
enable/disable.
Reviewed-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Sean Paul <seanpaul@chromium.org>
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Second attempt for 3rd drm/tilcdc pull request for v4.9.
* tag 'tilcdc-4.9-3.1' of https://github.com/jsarha/linux:
drm/tilcdc: fix wrong error handling
drm/tilcdc: Return directly after a failed kfree_table_init() in tilcdc_convert_slave_node()
drm/tilcdc: Remove "default" from blue-and-red-wiring property binding
drm/tilcdc: Fix non static symbol warning
drm/tilcdc: mark symbols static where possible
drm/tilcdc: add missing header dependencies
drm/tilcdc: WARN if CRTC is touched without CRTC lock
drm/tilcdc: Take CRTC lock when calling tilcdc_crtc_disable()
drm/tilcdc: Remove unnecessary tilcdc_crtc_disable() from tilcdc_unload()
drm/tilcdc: Flush flip-work workqueue before drm_flip_work_cleanup()
drm/tilcdc: Clean up LCDC functional clock rate setting code
drm/tilcdc: Take crtc modeset lock while updating the crtc clock rate
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When 'component_bind_all' fails it should not try to unbind components
in the error handling. This will produce a null pointer kernel panic when
no component exist.
This patch changes the order of the error handling. Now, it will only
unbind components if the are bound. Otherwise, the module will jump to
an error label below.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
Reviewed-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
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tilcdc_convert_slave_node()
Return directly after a memory allocation failed in this function
at the beginning.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
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Fixes the following sparse warning:
drivers/gpu/drm/tilcdc/tilcdc_drv.c:64:5: warning:
symbol 'tilcdc_atomic_check' was not declared. Should it be static?
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
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We get 3 warnings when building kernel with W=1:
drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c:142:29: warning: no previous prototype for 'tilcdc_get_overlay' [-Wmissing-prototypes]
drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c:198:13: warning: no previous prototype for 'tilcdc_convert_slave_node' [-Wmissing-prototypes]
drivers/gpu/drm/tilcdc/tilcdc_slave_compat.c:264:12: warning: no previous prototype for 'tilcdc_slave_compat_init' [-Wmissing-prototypes]
In fact, these functions are only used in the file in which they are
declared and don't need a declaration, but can be made static.
So this patch marks these functions with 'static'.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
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We get 4 warnings when building kernel with W=1:
drivers/gpu/drm/tilcdc/tilcdc_tfp410.c:393:12: warning: no previous prototype for 'tilcdc_tfp410_init' [-Wmissing-prototypes]
drivers/gpu/drm/tilcdc/tilcdc_tfp410.c:398:13: warning: no previous prototype for 'tilcdc_tfp410_fini' [-Wmissing-prototypes]
drivers/gpu/drm/tilcdc/tilcdc_panel.c:443:12: warning: no previous prototype for 'tilcdc_panel_init' [-Wmissing-prototypes]
drivers/gpu/drm/tilcdc/tilcdc_panel.c:448:13: warning: no previous prototype for 'tilcdc_panel_fini' [-Wmissing-prototypes]
In fact, these functions are declared in
drivers/gpu/drm/tilcdc/tilcdc_tfp410.h,
drivers/gpu/drm/tilcdc/tilcdc_panel.h,
so this patch adds missing header dependencies.
Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
Signed-off-by: Jyri Sarha <jsarha@ti.com>
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WARN if CRTC is touched without CRTC lock. The crtc functions should
not be called simultaneously from multiple threads. Having the DRM
CRTC lock should take care of that.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Take CRTC lock when calling tilcdc_crtc_disable() in
tilcdc_crtc_destroy().
In theory there could still be some operation ongoing, which should
finish before destroying the CRTC. However, the main reason for
adding this is to be able to add WARNing in tilcdc_crtc_disable() if
CRTC is not locked.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Remove unnecessary tilcdc_crtc_disable() from tilcdc_unload(). The
tilcdc_crtc_disable() called via tilcdc_crtc_destroy() by
drm_mode_config_cleanup() couple of lines later.
The early call to tilcdc_crtc_disable() was a wrong fix (that worked)
for calling drm_flip_work_cleanup() before flushing the flip-work
queue.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Flush flip-work workqueue before drm_flip_work_cleanup(). It causes a
nasty warning if there is unfinished flip-work in the queue when
drm_flip_work_cleanup() is called. The flush_workqueue() has to be
called before drm_crtc_cleanup() for unref_worker() to be able to do
its job.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Clean up LCDC functional clock rate setting code.
The LCDC functional clock is set by two functions: mode_set_nofb() and
cpufreq_transition().
When tilcdc_crtc_mode_set_nofb() is called in atomic commit phase the
drm atomic helpers have taken all the necessary drm locks and turned
off the crtc, while tilcdc_commit() is keeping LCDC powered on. For
mode_set_nofb() just a simple clock setting function without any
locking or power management code is enough. The new tilcdc_crtc_set_clk()
is implemented for that purpose.
cpufreq_transition() on the other hand is called from outside DRM and
it needs to take the necessary locks and turn off the CRTC while
keeping the LCDC powered. The reimplemented tilcdc_crtc_update_clk()
is for that purpose and it uses the new tilcdc_crtc_set_clk() to
actually set the clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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Take crtc modeset lock while updating the crtc clock rate. To avoid a
race in tilcdc_crtc_update_clk(), we do not want crtc mode to change
while we update crtc clock.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
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into drm-next
Here are some patches for drm-next.
It contains:
- minor fixes for typo and warning.
- sparse and coccicheck warning fixes
- bunch of patches fixing issues found while testing drm/sti with an
atomic version of weston
- the removal of the support of stih415-416 sti platform
* 'sti-drm-next-2016-09-20' of https://github.com/vinceab/linux:
drm/sti: remove stih415-416 platform support
drm/sti: fix compositor debugfs creation
drm/sti: use valid video mode
drm/sti: in crtc_atomic_flush, enable only planes of this crtc
drm/sti: use vtg array instead of vtg_main/aux
drm/sti: use different notifier_block for each pipe
drm/sti: fix atomic_disable check
drm/sti: run gdp init sequence only once
drm/sti: run hqvdp init sequence only once
drm/sti: fix debug logs
drm/sti: dpms function missing for HDMI connector
drm/sti: Fix sparse warnings
drm: sti: fix coccicheck warnings
drm: sti: Replace drm_fb_get_bpp_depth() with drm_format_plane_cpp()
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stih415 and stih416 platform are obsolete and no more supported.
Only stih407 and stih410 platform are maintained.
Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
Acked-by: Peter Griffin <peter.griffin@linaro.org>
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Fix typo and issue while creating the vid and mixer debugfs entries.
Signed-off-by: Vincent Abriou <vincent.abriou@st.com>
Acked-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
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In atomic mode the crtc_xxx (eg crtc_hdisplay) members of the mode
structure may be unset before calling atomic_check/commit for planes.
Instead of, use xxx members which are actually set.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Vincent Abriou <vincent.abriou@st.com>
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crtc_atomic_flush performs some additional processing, like plane
enable at mixer level.
Enable only the planes attached to the CRTC.
Signed-off-by: Fabien Dessenne <fabien.dessenne@st.com>
Acked-by: Vincent Abriou <vincent.abriou@st.com>
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