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* drm/nouveau/fifo/gm107: KeplerChannelGpfifoB, and 2048 channelsBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk110: expose KeplerChannelGpfifoBBen Skeggs2016-03-13
| | | | | | | | | | | | | | | This class supports a WFI method (0x0078) that's not present on the KeplerChannelGpfifoA class. The binary driver exposes both classes on these GPUs for some reason, though there doesn't appear to be any difference in the setup that's done for each (ie. even if you allocate GpfifoA, the WFI method will still work). We shall just expose GpfifoB, as I don't see a good reason to report the presence of both. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104: add vic plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104: add sec plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104: add nvdec plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104: add nvenc plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add vic plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add nvdec plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add nvenc plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add msenc plumbingBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: sort engine indices alphabeticallyBen Skeggs2016-03-13
| | | | | | Unlike subdevs, these aren't initialised in a defined order. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fifo/gk104: make use of topology info during gpfifo constructionBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gm206: remove implementation, it's now identical to gm200Ben Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/hwmon: add power consumptionKarol Herbst2016-03-13
| | | | | | | v2: expose only if the sensor reading is valid Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/iccsense: implement for ina209, ina219 and ina3221Karol Herbst2016-03-13
| | | | | | | | | | | | | based on Martins initial work v3: fix ina2x9 calculations v4: don't kmalloc(0), fix the lsb/pga stuff v5: add a field to tell if the power reading may be invalid add nkvm_iccsense_read_all function check for the device on the i2c bus Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/nvbios/iccsense: add parsing of the SENSE tableMartin Peres2016-03-13
| | | | | | | | | Karol Herbst: v4: don't kmalloc(0) v5: stricter validation Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/subdev/iccsense: add new subdev for power sensorsMartin Peres2016-03-13
| | | | | Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Reviewed-by: Martin Peres <martin.peres@free.fr>
* drm/nouveau/secboot/gm20b: add secure boot supportAlexandre Courbot2016-03-13
| | | | | | | | | | | | Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/secboot/gm200: add secure-boot supportAlexandre Courbot2016-03-13
| | | | | | | | | | | | | Add secure-boot for the dGPU set of GM20X chips, using the PMU as the high-secure falcon. This work is based on Deepak Goyal's initial port of Secure Boot to Nouveau. v2. use proper memory target function Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add support for secure bootAlexandre Courbot2016-03-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | On GM200 and later GPUs, firmware for some essential falcons (notably GR ones) must be authenticated by a NVIDIA-produced signature and loaded by a high-secure falcon in order to be able to access privileged registers, in a process known as Secure Boot. Secure Boot requires building a binary blob containing the firmwares and signatures of the falcons to be loaded. This blob is then given to a high-secure falcon running a signed loader firmware that copies the blob into a write-protected region, checks that the signatures are valid, and finally loads the verified firmware into the managed falcons and switches them to privileged mode. This patch adds infrastructure code to support this process on chips that require it. v2: - The IRQ mask of the PMU falcon was left - replace it with the proper irq_mask variable. - The falcon reset procedure expecting a falcon in an initialized state, which was accidentally provided by the PMU subdev. Make sure that secboot can manage the falcon on its own. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add gpuobj memcpy helper functionsAlexandre Courbot2016-03-13
| | | | | | | | Add memcpy functions to copy a buffer to a gpuobj and vice-versa. This will be used by the secure boot code. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/gr/gm200: s/gm204/gm200/Ben Skeggs2016-03-13
| | | | | | | | | | Most of the per-chipset differences will go away when we fully switch to using the register lists provided by the firmware files, which will leave all the remaining code "belonging" to GM200. This is a preemptive rename from GM204 to GM200. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau: s/gm204/gm200/ in a number of placesBen Skeggs2016-03-13
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/core: add firmware handling functionsAlexandre Courbot2016-03-13
| | | | | | | | | | | Add two functions nvkm_firmware_get() and nvkm_firmware_put() to load a firmware file and free its resources, respectively. Since firmware files are becoming a necessity for new GPUs, and their location has been standardized to nvidia/chip/, this will prevent duplicate and error-prone name-generation code. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/perf: add fields for pci speed and width and use it for the pstatesKarol Herbst2016-01-10
| | | | Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/bios/perf: parse the pci speed from the bios for tesla and newer ↵Karol Herbst2016-01-10
| | | | | | cards Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/pci: implement generic code for pcie speed changeKarol Herbst2016-01-10
| | | | | | | | | | | | v2: rename and group functions v4: change copyright information move printing of pcie speeds into oneinit, rename all pcie functions to nvkm_pcie_* don't try to raise the pcie version when no higher one is supported v5: revert Copyright changes and rename nvkm_pcie_raise_version to nvkm_pcie_set_version v6: remove some useless pci_is_pcie checks and rework messages Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/pci: add gk104 variantKarol Herbst2016-01-10
| | | | | | | | v2: change email used in header v4: change Copyright information v5: revert Copyright changes Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/pci: add gf106 variantKarol Herbst2016-01-10
| | | | | | | | v2: change email used in header v4: change Copyright information v5: revert Copyright changes Signed-off-by: Karol Herbst <nouveau@karolherbst.de>
* drm/nouveau/nouveau/perfmon: add interface files for current core voltageKarol Herbst2016-01-10
| | | | | Signed-off-by: Karol Herbst <nouveau@karolherbst.de> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/clk: remove references to "daemon"Ben Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ltc/gm204: split implementation from gm107Ben Skeggs2016-01-10
| | | | | | | | Differences from GM10x: - GM20x LTC count detection differs from GM10x - GM20x init doesn't require large page size setting Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/ibus/gm204: split implementation from gk104Ben Skeggs2016-01-10
| | | | | | GM20x doesn't require the priv ring timeout bumps that GK/GM10x have. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: modify nvif_unvers/nvif_unpack macros to be more obviousBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out client interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out device interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out ctxdma interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out perfmon interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out device control interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out fifo interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out display interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out nvsw interface definitonsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: split out fermi interface definitionsBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/nvif: move internal class identifiers to class.hBen Skeggs2016-01-10
| | | | Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pmu: remove whitelist for PGOB-exit WAR, enable by defaultBen Skeggs2015-12-08
| | | | | | | | | NVIDIA have indicated that the workaround is required on all GK10[467] boards that have the PGOB fuse set. I've left the commandline option in place for now, as paranoia. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/instmem: protect instobj list with a spinlockBen Skeggs2015-11-25
| | | | | | | | | No locking is required for the traversal of this list, as it only happens during suspend/resume where nothing else can be executing. Fixes some of the issues noticed during parallel piglit runs. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bus/hwsq: Implement VBLANK waiting heuristicRoy Spliet2015-11-03
| | | | | | | | | Avoids waiting for VBLANKS that never arrive on headless or otherwise unconventional set-ups. Strategy taken from MEMX. Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Tested-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/fb/ramgt215: Change FBVDD/Q when BIOS asks for itRoy Spliet2015-11-03
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/bios/rammap: Identify DLLoff for >= GF100Roy Spliet2015-11-03
| | | | | Signed-off-by: Roy Spliet <rspliet@eclipso.eu> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
* drm/nouveau/pci: Handle 5-bit and 8-bit tag fieldPierre Moreau2015-11-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the hardware supports extended tag field (8-bit ones), then enable it. This is usually done by the VBIOS, but not on some MBPs (see fdo#86537). In case extended tag field is not supported, 5-bit tag field is used which limits the possible number of requests to 32. Apparently bits 7:0 of 0x08841c stores some number of outstanding requests, so cap it to 32 if extended tag is unsupported. Fixes: fdo#86537 v2: Restrict changes to chipsets >= 0x84 v3: * Add nvkm_pci_mask to pci.h * Mask bit 8 before setting it v4: * Rename `add` argument of nvkm_pci_mask to `value` * Move code from nvkm_pci_init to g84_pci_init and remove PCIe and chipset checks v5: * Rebase code on latest PCI structure * Restore PCIe check * Fix namings in nvkm_pci_mask * Rephrase part of the commit message Signed-off-by: Pierre Moreau <pierre.morrow@free.fr> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
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