aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/clk/samsung
Commit message (Collapse)AuthorAge
...
| * clk: samsung: exynos5433: Add clocks for CMU_DISP domainChanwoo Choi2015-02-04
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the the mux/divider/gate clocks for CMU_DISP domain which includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER). Also, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP domain. This patch adds the clocks of CMU_TOP related to HDMI. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add clocks for CMU_MIF domainChanwoo Choi2015-02-04
| | | | | | | | | | | | | | | | | | | | This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect). The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add clocks for CMU_G2D domainChanwoo Choi2015-02-04
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds ths mux/divider/gate clocks of CMU_G2D domain which includes G2D/MDMA IPs. The CMU_G2D requires its parent defined in the CMU_TOP domain. Hence this patch adds G2D related clocks to the CMU_TOP domain. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add clocks for CMU_PERIS domainChanwoo Choi2015-02-04
| | | | | | | | | | | | | | | | | | | | | | This patch adds missing gate clocks of CMU_PERIS domain which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs. The special clocks of CMU_PERIS use oscclk source clock directly. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add clocks for CMU_PERIC domainChanwoo Choi2015-02-04
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds missing divider/gate clocks of CMU_PERIC domain which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use external input clock which has 'ioclk_*' prefix. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on] Signed-off-by: Inha Song <ideal.song@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domainChanwoo Choi2015-02-04
| | | | | | | | | | | | | | | | | | | | This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433. CMU_TOP domain provides source clocks to other CMU domains. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos5433: Add clocks using common clock frameworkChanwoo Choi2015-02-04
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the CMU (Clock Management Units) of Exynos5433 which is an Octa-core 64bit SoC. This patch supports necessary clocks (PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation for Exynos5433 clock controller. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Inki Dae <inki.dae@samsung.com> [s.nawrocki@samsung.com: whitespace cleanup in dt-bindings/clock/exynos5433.h] [ added U suffix to first arguments of PLL_35XX_RATE()] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-21
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
| * | Merge tag 'v3.20-exynos-clk' of git://linuxtv.org/snawrocki/samsung into ↵Michael Turquette2015-02-02
| |\| | | | | | | | | | | | | | | | | | | clk-next Exynos 3250, 4415 drivers cleanup by using common code and addition of clock definitions for DVFS on Exynos4.
| | * clk: samsung: exynos4: Add divider clock id for memory bus frequencyChanwoo Choi2015-01-28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the divider clock id for Exynos4 memory bus frequency. The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling) feature of the exynos memory bus. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify codeChanwoo Choi2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the samsung_cmu_register_one() to simplify code for Exynos4415. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify codeChanwoo Choi2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch uses the samsung_cmu_register_one() to simplify code for Exynos3250. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * clk: samsung: Change the return value of samsung_cmu_register_one()Chanwoo Choi2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the return value of samsung_cmu_register_one() from 'void' to 'samsung_clk_provider structure' pointer type because samsung_clk_provider may be used in each clock driver. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | Merge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung ↵Michael Turquette2015-01-20
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | into clk-next - Clock definitions for Exynos7 SoC peripheral devices: video scaler, USB, DMA, SPI and the audio subsystem.
| | * | clk: samsung: exynos7: add clocks for audio blockPadmavathi Venna2015-01-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add required clk support for I2S, PCM and SPDIF. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | clk: samsung: exynos7: add clocks for SPI blockPadmavathi Venna2015-01-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock support for 5 SPI channels. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | clk: samsung: exynos7: add gate clock for DMA blockPadmavathi Venna2015-01-15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for PDMA0 and PDMA1 gate clks. Signed-off-by: Padmavathi Venna <padma.v@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | clk: samsung: exynos7: Add required clock tree for USBVivek Gautam2014-12-23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adding required gate clocks for USB3.0 DRD controller present on Exynos7. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | clk: samsung: exynos7: Add clocks for MSCL blockTony K Nadackal2014-12-23
| | |/ | | | | | | | | | | | | | | | | | | | | | Add clock support for the MSCL block for Exynos7. Signed-off-by: Tony K Nadackal <tony.kn@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * / clk: exynos-audss: Fix memory leak on driver unbind or probe failureKrzysztof Kozlowski2015-01-17
| |/ | | | | | | | | | | | | | | | | | | | | | | The memory allocated by basic clock divider/gate/mux (struct clk_gate, clk_divider and clk_mux) was leaking. During driver unbind or probe failure the driver only unregistered the clocks. Use clk_unregister_{gate,divider,mux} to release all resources. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
* / clk: exynos5420: Add IDs for clocks used in DISP1 power domainJavier Martinez Canillas2015-01-28
|/ | | | | | | | | | | | | | | | | | | | | | | When a power domain is powered off on Exynos5420 SoC, the input clocks of the devices attached to this power domain are re-parented to oscclk and restored to the original parent after powering on the power domain. So a reference to the input and parent clocks for the devices attached to a power domain are needed to be able to do the re-parenting. The DISP1 pd includes modules which uses the following clocks: ACLK_200_DISP1 (MIXER and HDMILINK) ACLK_300_DISP1 (FIMD1) ACLK_400_DISP1 (Internal Buses) Each of these clocks are generated as the output of a clock mux so add an ID for all of these clock muxes and their parents to be referenced in the DISP1 power domain device node. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Acked-by: Michael Turquette <mturquette@linaro.org> Signed-off-by: Kukjin Kim <kgene@kernel.org>
* Merge tag 'clk-for-linus-3.19' of ↵Linus Torvalds2014-12-20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
| * clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to ↵Krzysztof Kozlowski2014-12-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | domain being gated Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll. The system hang on one of steps: 1. Disabling unused clocks from audss block. 2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated. Add a workaround for this by enabling the 'mau_epll' clock in probe. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * clk: samsung: Fix double add of syscore ops after driver rebindKrzysztof Kozlowski2014-12-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During driver unbind the syscore ops were not unregistered which lead to double add on syscore list: $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind [ 1463.044061] ------------[ cut here ]------------ [ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0() [ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84. [ 1463.061625] Modules linked in: [ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G W 3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022 [ 1463.075338] [<c0014e2c>] (unwind_backtrace) from [<c0011d80>] (show_stack+0x10/0x14) [ 1463.083046] [<c0011d80>] (show_stack) from [<c048bb70>] (dump_stack+0x70/0xbc) [ 1463.090236] [<c048bb70>] (dump_stack) from [<c00233d4>] (warn_slowpath_common+0x74/0xb0) [ 1463.098295] [<c00233d4>] (warn_slowpath_common) from [<c00234a4>] (warn_slowpath_fmt+0x30/0x40) [ 1463.106962] [<c00234a4>] (warn_slowpath_fmt) from [<c020fe80>] (__list_add+0x8c/0xc0) [ 1463.114760] [<c020fe80>] (__list_add) from [<c0282094>] (register_syscore_ops+0x30/0x3c) [ 1463.122819] [<c0282094>] (register_syscore_ops) from [<c0392f20>] (exynos_audss_clk_probe+0x36c/0x460) [ 1463.132091] [<c0392f20>] (exynos_audss_clk_probe) from [<c0283084>] (platform_drv_probe+0x48/0xa4) [ 1463.141013] [<c0283084>] (platform_drv_probe) from [<c0281a14>] (driver_probe_device+0x13c/0x37c) [ 1463.149852] [<c0281a14>] (driver_probe_device) from [<c0280560>] (bind_store+0x90/0xe0) [ 1463.157822] [<c0280560>] (bind_store) from [<c027fd10>] (drv_attr_store+0x20/0x2c) [ 1463.165363] [<c027fd10>] (drv_attr_store) from [<c0143898>] (sysfs_kf_write+0x4c/0x50) [ 1463.173252] [<c0143898>] (sysfs_kf_write) from [<c0142c80>] (kernfs_fop_write+0xbc/0x198) [ 1463.181395] [<c0142c80>] (kernfs_fop_write) from [<c00e2be0>] (vfs_write+0xa0/0x1a8) [ 1463.189104] [<c00e2be0>] (vfs_write) from [<c00e2f00>] (SyS_write+0x40/0x8c) [ 1463.196122] [<c00e2f00>] (SyS_write) from [<c000f2a0>] (ret_fast_syscall+0x0/0x48) [ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]--- [ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Fixes: 1241ef94ccc3 ("clk: samsung: register audio subsystem clocks using common clock framework") Cc: <stable@vger.kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmiAndrzej Hajda2014-12-02
| | | | | | | | | | | | | | | | | | | | | | sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock. The patch models this dependency using parent/child hirerarchy. The patch fixes issue with system hangs during mixer device access, mixer uses sclk_hdmiphy descendant clock. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos4415: Fix build with PM_SLEEP disabledKrzysztof Kozlowski2014-12-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following build errors when PM_SLEEP is disabled (e.g. by disabling SUSPEND and HIBERNATION): drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_init’: drivers/clk/samsung/clk-exynos4415.c:982:2: error: ‘exynos4415_ctx’ undeclared (first use in this function) drivers/clk/samsung/clk-exynos4415.c:982:2: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_dmc_init’: drivers/clk/samsung/clk-exynos4415.c:1123:2: error: ‘exynos4415_dmc_ctx’ undeclared (first use in this function) make[3]: *** [drivers/clk/samsung/clk-exynos4415.o] Error 1 Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: remove unnecessary inclusion of header files from clk.hPankaj Dubey2014-12-02
| | | | | | | | | | | | | | | | | | Let's remove unnecessary include of header files from clk.h and add required one in clk.c Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> [s.nawrocki@samsung.com: dropped removal of '#include <linux/syscore_ops.h>'] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: remove unnecessary CONFIG_OF from clk.cPankaj Dubey2014-12-02
| | | | | | | | | | | | | | Remove unnecessary CONFIG_OF from samsung/clk.c. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: Spelling s/bwtween/between/Pankaj Dubey2014-12-02
| | | | | | | | | | | | | | Fix a typo in comment section of "struct samsung_clk_provider". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos7: add gate clock for ADC blockAbhilash Kesavan2014-10-31
| | | | | | | | | | | | | | Add clock support for the ADC interface in Exynos7. Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocksNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | | | Add clock support for the watchdog timer, pwm timer and thermal management unit IPs in Exynos7. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos7: add clocks for RTC blockNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | Add clock support for the RTC block in Exynos7. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos7: add clocks for MMC blockNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | | | Exynos7 supports 3 MMC channels, add the MMC gate clocks to support them. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos7: add clocks for I2C blockNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | | | Exynos7 supports 12 I2C channels, add the I2C gate clocks to support them. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: add initial clock support for Exynos7 SoCNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | | | | | | | Add initial clock support for Exynos7 SoC which is required to bring up platforms based on Exynos7. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_infoNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | | | | | | | | | Add the fields "fixed_factor_clks" and "nr_fixed_factor_clks" to "struct exynos_cmu_info" to allow registering of fixed factor clocks as well with exynos_cmu_register_one(). Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: Factor out the common code to clk.cNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | While adding clock support for Exynos5260, the infrastructure to register multiple clock controllers was introduced. Factor out the support for registering multiple clock controller from Exynos5260 clock code to common samsung clock code so that it can be used by other Exynos SoC which have multiple clock controllers. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: add support for 145xx and 1460x PLLsNaveen Krishna Ch2014-10-31
| | | | | | | | | | | | | | | | | | | | | | | | | | PLL145xx is similar to PLL35xx and PLL1460x is almost similar to PLL46xx with minor differences in bit positions. Hence, reuse the functions defined for pll_35xx and pll_46xx to support 145xx and 1460x PLLs respectively. Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com> Reviewed-by: Thomas Abraham <thomas.ab@samsung.com> Tested-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * clk: samsung: exynos4415: Add clocks using common clock frameworkChanwoo Choi2014-10-30
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using common clock framework. The CMU (Clock Management Unit) of Exynos4415 controls PLLs(Phase Locked Loops) and generates system clocks for CPU, busses and function clocks for individual IPs. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
* | Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds2014-12-14
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
| * | clk: samsung: drop owner assignment from platform_driversWolfram Sang2014-10-20
| |/ | | | | | | | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* / clk: exynos5440: move restart code into clock driverPankaj Dubey2014-11-22
|/ | | | | | | | | | | | | Let's register restart handler for Exynos5440 from it's clock driver for restart functionality. So that we can cleanup restart hooks from machine specific file. CC: Sylwester Nawrocki <s.nawrocki@samsung.com> CC: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Merge tag 'v3.18-rockchip-clk2' of ↵Mike Turquette2014-10-01
|\ | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next Allow parent rate changes for i2s on rk3288 and rockchip as well as s3c24xx restart handlers.
| * clk: samsung: register restart handlers for s3c2412 and s3c2443Heiko Stübner2014-10-01
| | | | | | | | | | | | | | | | | | | | | | | | S3C2412, S3C2443 and their derivatives contain a special software-reset register in their system-controller. Therefore register a restart handler for those. Tested on a s3c2416-based board, s3c2412 compile-tested. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
* | Merge tag 'for_3.18/samsung-clk' of ↵Mike Turquette2014-09-30
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next Samsung clock patches for v3.18 1) non-critical fixes (without the need to push to stable) fa0111be4ff3 clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation b511593d7165 clk: samsung: exynos4: fix g3d clocks c14254300131 clk: samsung: exynos4: add missing smmu_g2d clock and update comments 22842d244af3 clk: samsung: exynos5260: fix typo in clock name e82ba578ccde clk: samsung: exynos3250: fix width field of mout_mmc0/1 59037b92f440 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock 5ce37f266650 clk: samsung: exynos3250: fix mout_cam_blk parent list 2) Clock driver extensions 07ccf02ba5c3 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU d0e73eaf1925 ARM: dts: exynos3250: Add CMU node for DMC domain clocks e3c3f19bc618 clk: samsung: exynos3250: Register DMC clk provider 4676f0aab9dc clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
| * clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiationThomas Abraham2014-09-24
| | | | | | | | | | | | | | | | | | The 'div_core2' clock and the 'arm_clk' divider clocks are instances of the same divider clock. So remove the 'arm_clk' clock instance. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> [tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos4: fix g3d clocksMarek Szyprowski2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked g3d gate clock bits for this purpose and didn't provide real g3d clock at all. This patch fixes this issue by adding proper definition for g3d clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d. In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because it does not make any sense and most likely has been added by mistake. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> [tomasz.figa@gmail.com: Adjusted commit message.] Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocksMarek Szyprowski2014-09-22
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for exporting mout_hdmi and mout_mixer to device tree. Access to those clocks is required to correctly setup HDMI module on Exynos 4210 and 4x12 SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> CC: Mike Turquette <mturquette@linaro.org> CC: Tomasz Figa <t.figa@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos4: add missing smmu_g2d clock and update commentsMarek Szyprowski2014-09-22
| | | | | | | | | | | | | | | | | | | | This patch adds missing smmu_g2d clock implementation and updates comment about Exynos4 clocks from 278-282 range. Those clocks are available on all Exynos4 SoC series, so the misleading comment has been removed. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
| * clk: samsung: exynos3250: Register DMC clk providerKrzysztof Kozlowski2014-09-22
| | | | | | | | | | | | | | | | | | | | | | | | | | Add clock provider for clocks in DMC domain including EPLL and BPLL. The DMC clocks are necessary for Exynos3 devfreq driver. The DMC clock domain uses different address space (0x105C0000) than standard clock domain (0x10030000 - 0x10050000). The difference is huge enough to add new DT node for the clock provider, rather than extending existing address space. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-08 11:22:54 -0400