aboutsummaryrefslogtreecommitdiffstats
path: root/arch/mips/math-emu
Commit message (Collapse)AuthorAge
...
* MIPS: math-emu: Implement the FCCR, FEXR and FENR registersMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | Implement the FCCR, FEXR and FENR "shadow" FPU registers for the architecture levels that include them, for the CFC1 and CTC1 instructions in the full emulation mode. For completeness add macros for the CP1 UFR and UNFR registers too, no actual implementation though. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9708/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Set FIR feature flags for full emulationMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | | Implement FIR feature flags in the FPU emulator according to features supported and architecture level requirements. The W, L and F64 bits have only been added at level #2 even though the features they refer to were also included with the MIPS64r1 ISA and the W fixed-point format also with the MIPS32r1 ISA. This is only relevant for the full emulation mode and the emulated CFC1 instruction as well as ptrace(2) accesses. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9707/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Move long fixed-point support into an `ar' libraryMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | Complement 593d33fe [MIPS: math-emu: Move various objects into an ar library.] and also move sp_tlong.o, sp_flong.o, dp_tlong.o, and dp_flong.o into an `ar' library. These objects implement long fixed-point format support that can be omitted from MIPS I, MIPS II and MIPS32r1 configurations. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9702/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Correct delay-slot exception propagationMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | Restore EPC at the branch whose delay slot is emulated if the delay-slot instruction signals. This is so that code in `fpu_emulator_cop1Handler' does not see EPC having advanced and mistakenly successfully resume userland execution from the location at the branch target in that case. Restoring EPC guarantees an immediate exit from the emulation loop and if EPC hasn't advanced at all since entering the loop, also issuing the signal reported by the delay-slot instruction. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9701/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Correct FP ISA requirementsMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct ISA requirements for floating-point instructions: * the CU3 exception signifies a real COP3 instruction in MIPS I & II, * the BC1FL and BC1TL instructions are not supported in MIPS I, * the SQRT.fmt instructions are indeed supported in MIPS II, * the LDC1 and SDC1 instructions are indeed supported in MIPS32r1, * the CEIL.W.fmt, FLOOR.W.fmt, ROUND.W.fmt and TRUNC.W.fmt instructions are indeed supported in MIPS32, * the CVT.L.fmt and CVT.fmt.L instructions are indeed supported in MIPS32r2 and MIPS32r6, * the CEIL.L.fmt, FLOOR.L.fmt, ROUND.L.fmt and TRUNC.L.fmt instructions are indeed supported in MIPS32r2 and MIPS32r6, * the RSQRT.fmt and RECIP.fmt instructions are indeed supported in MIPS64r1, Also simplify conditionals for MIPS III and MIPS IV FPU instructions and the handling of the MOVCI minor opcode. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9700/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix delay-slot emulation cache incoherencyMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct a cache coherency regression introduced with be1664c4 [Another round of fixes for the fp emulator.] for the emulation frame used in delay-slot emulation. Two instructions are copied into the frame and as from the commit referred a cache synchronisation call is made for the second instruction aka `badinst' of the two only. The `flush_cache_sigtramp' interface is reused that guarantees that synchronisation will be made for 8 bytes or 2 instructions starting from the address requested, although if cache lines are wider then a larger area may be synchronised. Change the call to point to the first of the two instructions aka `emul' instead, removing unpredictable behaviour resulting from cache incoherency. This bug only ever manifested itself on systems implementing 4-byte cache lines, typically MIPS I systems, causing all kinds of weirdness. This is because the sequence of two instructions starting from `emul' is 8-byte aligned and for 8-byte or wider cache lines the line synchronised will span both, so the vast majority of systems have escaped unharmed. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9698/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Make NaN classifiers staticMaciej W. Rozycki2015-04-07
| | | | | | | | | | | The `ieee754sp_isnan' and `ieee754dp_isnan' NaN classifiers are now no longer externally referred, remove their header prototypes and make them local to the two only respective places still making use of them. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9693/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Optimise qNaN handling in `ieee754sp_fdp'Maciej W. Rozycki2015-04-07
| | | | | | | | | | | Rewrite qNaN handling in `ieee754sp_fdp' using the `ieee754_class_nan' helper recently added, removing the external call to `ieee754sp_isnan' and reducing the size of code by 16 instructions or 64 bytes. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9692/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove dead comparison helpersMaciej W. Rozycki2015-04-07
| | | | | | | | | None of the comparison helpers in ieee754.h is used, remove them. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9691/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove redundant code from NaN comparisonMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | Remove a redundant call to `ieee754_setandtestcx' in `ieee754sp_cmp' and `ieee754dp_cmp'. The IEEE 754 exception requested will have already been set by a call to `ieee754_setcx' immediately above, because `sig' has to be non-zero to reach here, and the comparison result returned will be 0 regardless of the result from the call. Simplify the return expression remaining. All this reducing the size of code by 16 and 12 instructions or 64 and 48 bytes respectively. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9690/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Optimise NaN handling in comparisonsMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | We have the input operands already classified in `ieee754sp_cmp' and `ieee754dp_cmp' comparison operations, so use the class obtained to tell NaNs and numbers apart rather than classifying inputs again for this purpose, reducing the size of code by 24 and 40 instructions or 96 and 160 bytes respectively. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9689/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Reinstate sNaN quieting handlersMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | | | | Revert the changes made by commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.] to `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' sNaN quieting handlers and their callers so that sNaN processing is done within the handlers againg. Pass the sNaN causing an IEEE 754 invalid operation exception down to the relevant handler. Pass the sNaN in `fs' where two sNaNs are supplied to a binary operation. Set the Invalid Operation FCSR exception bits in the quieting handlers rather than at their call sites throughout. Make the handlers exclusive for sNaN processing. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9688/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Don't pass qNaNs through quieting handlersMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | Don't call the `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' sNaN quieting handlers for a qNaN supplied to floating-point format conversions or SQRT.S/SQRT.D instructions, or for a qNaN produced out of a negative operand supplied to SQRT.S/SQRT.D instructions. Return the qNaN right away in these cases. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9687/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Factor out NaN FP format conversionsMaciej W. Rozycki2015-04-07
| | | | | | | Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9686/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Update sNaN quieting handlersMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | | | | | | | Commit fdffbafb [Lots of FPU bug fixes from Kjeld Borch Egevang.] replaced the two single `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' places, where sNaN quieting used to happen for single and double floating-point operations respectively, with individual qNaN instantiations across all the call sites instead. It also made most of these two functions dead code as where called on a qNaN they return right away. To revert the damage and make sNaN quieting uniform again first rewrite `ieee754sp_nanxcpt' and `ieee754dp_nanxcpt' to do the same quieting all the call sites do, that is return the default qNaN encoding for all input sNaN values; never propagate any sNaN payload bits from its trailing significand field. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9685/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Factor out CFC1/CTC1 emulationMaciej W. Rozycki2015-04-07
| | | | | | | | | | | Move CFC1/CTC1 emulation code to separate functions to avoid excessive indentation in forthcoming changes. Adjust formatting in a minor way and remove extraneous round brackets. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9682/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Remove `modeindex' macroMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | | | | Commit 56a64733 [MIPS: math-emu: Switch to using the MIPS rounding modes.] removed the distinction between hardware and emulator rounding mode encodings, the hardware encoding is now used in emulation as well. Complement the change and remove the `modeindex' macro previously used for indexing into encoding translation tables, it now does nothing and only obfuscates code by reinserting the value extracted from FCSR. Adjust comments accordingly. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9680/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix oversize lines in comparisonsMaciej W. Rozycki2015-04-07
| | | | | | | Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9676/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Reindent `bc_op' emulationMaciej W. Rozycki2015-04-07
| | | | | | | | | Correct the double-tab indentation of the branch-likely not-taken case. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9674/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ieee754.h: Supplement comments for special valuesMaciej W. Rozycki2015-04-07
| | | | | | | | | | Add the remaining missing comments for IEEE 754 special value array indices. Reindent macro definitions for consistency. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9671/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: ieee754.h: Correct comments for special valuesMaciej W. Rozycki2015-04-07
| | | | | | | | | | | | IEEE754_SPCVAL_NMIN denotes the index into the special value array where the closest to zero negative normal number expressible is stored. Similarly IEEE754_SPCVAL_NMIND denotes such index for the closest to zero negative subnormal number expressible. Make comments match that. Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/9670/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Add FPU emulator counter for emulated delay slots.David Daney2015-04-01
| | | | | | | | | | | Delay slot emulation in the FPU emulator is the only kernel user of an executable stack, it is also very slow. Add a counter so we can see how many of these emulations are done. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/8634/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: LLVMLinux: Silence variable self-assignment warnings.Toma Tabacu2015-04-01
| | | | | | | | | | | | | | Remove variable self-assignments. This silences a bunch of -Wself-assign warnings reported by clang. The changed code can be compiled without warnings by both gcc and clang. Signed-off-by: Toma Tabacu <toma.tabacu@imgtec.com> Signed-off-by: Daniel Sanders <daniel.sanders@imgtec.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/9314/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Handle MIPS IV, V and R2 FPU instructions on MIPS R6 as wellMarkos Chandras2015-02-17
| | | | | | | MIPS R2 FPU instructions are also present in MIPS R6 so amend the preprocessor definitions to take MIPS R6 into consideration. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: mips-r2-to-r6-emul: Add R2 emulator for MIPS R6Leonid Yegoshin2015-02-17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS R6 removed quite a few R2 instructions. However, there is plenty of <R6 userland code so we add an in-kernel emulator so we can still be able to execute all R2 userland out there. The emulator comes with a handy debugfs under /mips/ directory (r2-emul-stats) to provide some basic statistics of the instructions that are being emulated. Below are some statistics from booting a minimal buildroot image: Instruction Total BDslot ------------------------------ movs 236969 0 hilo 56686 0 muls 55279 0 divs 10941 0 dsps 0 0 bops 1 0 traps 0 0 fpus 0 0 loads 214981 17 stores 103364 0 llsc 56898 0 dsemul 150418 0 jr 370158 bltzl 43 bgezl 1594 bltzll 0 bgezll 0 bltzal 39 bgezal 39 beql 14503 bnel 138741 blezl 0 bgtzl 3988 Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BNEZC and JIALC instructionsMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BEQZC and JIC instructionsMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 ldc2 opcode for the new BEQZC and JIC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BALC instructionMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 swc2 opcode for the new BALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BNVC, BNEC and BNEZLAC instructionsMarkos Chandras2015-02-17
| | | | | | | MIPS R6 uses the <R6 DADDI opcode for the new BNVC, BNEC and BNEZLAC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 BOVC, BEQC and BEQZALC instructionsMarkos Chandras2015-02-17
| | | | | | | MIPS R6 uses the <R6 ADDI opcode for the new BOVC, BEQC and BEQZALC instructions. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 branch compact (BC) instructionMarkos Chandras2015-02-17
| | | | | | MIPS R6 uses the <R6 LWC2 opcode for the new BC instruction. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 B{L,G}T{Z,}{AL,}C instructionsMarkos Chandras2015-02-17
| | | | | | | | | | | | | | MIPS R6 added the following four instructions which share the BGTZ and BGTZL opcode: BLTZALC: Compact branch-and-link if GPR rt is < to zero BGTZALC: Compact branch-and-link if GPR rt is > to zero BLTZL : Compact branch if GPR rt is < to zero BGTZL : Compact branch if GPR rt is > to zero BLTC : Compact branch if GPR rs is less than GPR rt BLTUC : Similar to BLTC but unsigned Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the new MIPS R6 B{L,G}Ε{Z,}{AL,}C instructionsMarkos Chandras2015-02-17
| | | | | | | | | | | | | | MIPS R6 added the following four instructions which share the BLEZ and BLEZL opcodes: BLEZALC: Compact branch-and-link if GPR rt is <= to zero BGEZALC: Compact branch-and-link if GPR rt is >= to zero BLEZC : Compact branch if GPR rt is <= to zero BGEZC : Compact branch if GPR rt is >= to zero BGEC : Compact branch if GPR rs is less than or equal to GPR rt BGEUC : Similar to BGEC but unsigned. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Emulate the BC1{EQ,NE}Z FPU instructionsMarkos Chandras2015-02-17
| | | | | | | | | MIPS R6 introduced the following two branch instructions for COP1: BC1EQZ: Branch if Cop1 (FPR) Register Bit 0 is Equal to Zero BC1NEZ: Branch if Cop1 (FPR) Register Bit 0 is Not Equal to Zero Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: branch: Do not emulate the branch likelies on MIPS R6Markos Chandras2015-02-17
| | | | | | | | MIPS R6 removed the BLTZL, BGEZL, BLTZAL, BGEZAL, BEQL, BNEL, BLEZL, BGTZL branch likely instructions so we must not try to emulate them on MIPS R6 if the R2-to-R6 emulator is not present. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: kernel: Prepare the JR instruction for emulation on MIPS R6Markos Chandras2015-02-17
| | | | | | | The MIPS R6 JR instruction is an alias to the JALR one, so it may need emulation for non-R6 userlands. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
* MIPS: Support for hybrid FPRsPaul Burton2014-11-24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Hybrid FPRs is a scheme where scalar FP registers are 64b wide, but accesses to odd indexed single registers use bits 63:32 of the preceeding even indexed 64b register. In this mode all FP code except that built for the plain FP64 ABI can execute correctly. Most notably a combination of FP64A & FP32 code can execute correctly, allowing for existing FP32 binaries to be linked with new FP64A binaries that can make use of 64 bit FP & MSA. Hybrid FPRs are implemented by setting both the FR & FRE bits, trapping & emulating single precision FP instructions (via Reserved Instruction exceptions) whilst allowing others to execute natively. It therefore has a penalty in terms of execution speed, and should only be used when no fully native mode can be. As more binaries are recompiled to use either the FPXX or FP64(A) ABIs, the need for hybrid FPRs should diminish. However in the short to mid term it allows for a gradual transition towards that world, rather than a complete ABI break which is not feasible for some users & not desirable for many. A task will be executed using the hybrid FPR scheme when its TIF_HYBRID_FPREGS flag is set & TIF_32BIT_FPREGS is clear. A further patch will set the flags as necessary, this patch simply adds the infrastructure necessary for the hybrid FPR mode to work. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Alexander Viro <viro@zeniv.linux.org.uk> Cc: linux-fsdevel@vger.kernel.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7683/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Remove useless parenthesesRalf Baechle2014-11-24
| | | | | | | | | | | | | | | Based on the spatch @@ expression e; @@ - return (e); + return e; with heavy hand editing because some of the changes are either whitespace or identation only or result in excessivly long lines. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix build with binutils 2.24.51+Manuel Lauss2014-11-07
| | | | | | | | | | | | | | | | | | | | | | | | | Starting with version 2.24.51.20140728 MIPS binutils complain loudly about mixing soft-float and hard-float object files, leading to this build failure since GCC is invoked with "-msoft-float" on MIPS: {standard input}: Warning: .gnu_attribute 4,3 requires `softfloat' LD arch/mips/alchemy/common/built-in.o mipsel-softfloat-linux-gnu-ld: Warning: arch/mips/alchemy/common/built-in.o uses -msoft-float (set by arch/mips/alchemy/common/prom.o), arch/mips/alchemy/common/sleeper.o uses -mhard-float To fix this, we detect if GAS is new enough to support "-msoft-float" command option, and if it does, we can let GCC pass it to GAS; but then we also need to sprinkle the files which make use of floating point registers with the necessary ".set hardfloat" directives. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Cc: Matthew Fortune <Matthew.Fortune@imgtec.com> Cc: Markos Chandras <Markos.Chandras@imgtec.com> Cc: Maciej W. Rozycki <macro@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/8355/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: cp1emu: Fix ISA restrictions for cop1x_op instructionsMarkos Chandras2014-10-21
| | | | | | | | | | | | | | | | | | | Commit 08a07904e1828 ("MIPS: math-emu: Remove most ifdefery") removed the #ifdef ISA conditions and switched to runtime detection. However, according to the instruction set manual, the cop1x_op instructions are available in >=MIPS32r2 as well. This fixes a problem on MIPS32r2 with the ntpd package which failed to execute with a SIGILL exit code due to the fact that a madd.d instruction was not being emulated. Signed-off-by: Markos Chandras <markos.chandras@imgtec.com> Fixes: 08a07904e1828 ("MIPS: math-emu: Remove most ifdefery") Cc: <stable@vger.kernel.org> # v3.16+ Cc: linux-mips@linux-mips.org Reviewed-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Markos Chandras <markos.chandras@imgtec.com> Patchwork: https://patchwork.linux-mips.org/patch/8173/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Fix MFC1 & MFHC1 emulation for 64-bit MIPS systemsPaul Burton2014-09-26
| | | | | | | | | | | | | | | | | | | Commit bbd426f542cb "MIPS: Simplify FP context access" modified the SIFROMREG & SIFROMHREG macros such that they return unsigned rather than signed 32b integers. I had believed that to be fine, but inadvertently missed the MFC1 & MFHC1 cases which write to a struct pt_regs regs element. On MIPS32 this is fine, but on 64 bit those saved regs' fields are 64 bit wide. Using unsigned values caused the 32 bit value from the FP register to be zero rather than sign extended as the architecture specifies, causing incorrect emulation of the MFC1 & MFHc1 instructions. Fix by reintroducing the casts to signed integers, and therefore the sign extension. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: stable@vger.kernel.org # v3.15+ Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7848/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Fix instruction decoding.Rob Kendrick2014-07-30
| | | | | | Tested-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Reduce code duplication.Ralf Baechle2014-06-26
| | | | | | | The fix in the preceeding commit did do exactly the same thing in two places showing some code cleanup was due. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Work around limitations of older GCC.Ralf Baechle2014-06-16
| | | | | | | | | | Older GCC doesn't get named initializations of anonymous structs right, that is members are not initializable in the containing structure through name however old style initializations are working fine. The issue exists with gcc up to 4.5.x. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: OCTEON: Enable use of FPUDavid Daney2014-05-30
| | | | | | | | | | | | | | | | | | | | Some versions of the assembler will not assemble CFC1 for OCTEON, so override the ISA for these. Add r4k_fpu.o to handle low level FPU initialization. Modify octeon_switch.S to save the FPU registers. And include r4k_switch.S to pick up more FPU support. Get rid of "#define cpu_has_fpu 0" Signed-off-by: David Daney <david.daney@cavium.com> Signed-off-by: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: James Hogan <james.hogan@imgtec.com> Cc: kvm@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/7006/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Add IEEE754 exception statistics to debugfsDeng-Cheng Zhu2014-05-30
| | | | | | | | | | | | | | | | | | | | Sometimes it's useful to let the user, while doing performance research, know what in the IEEE754 exceptions has caused many times of FP emulation when running a specific application. This patch adds 5 more files to /sys/kernel/debug/mips/fpuemustats/, whose filenames begin with "ieee754". These stats are in addition to the existing cp1ops, cp1xops, errors, loads and stores, which may not be useful in understanding the reasons of ieee754 exceptions. [ralf@linux-mips.org: Fixed reject due to other changes to the kernel FP assist software.] Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Cc: linux-mips@linux-mips.org Cc: Steven.Hill@imgtec.com Cc: james.hogan@imgtec.com Patchwork: http://patchwork.linux-mips.org/patch/7044/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Reduce microMIPS bloat.Ralf Baechle2014-05-23
| | | | | | | | Move microMIPS32_to_MIPS32() to a separate file which only gets built for mipsMIPS configurations; for other configurations the optimizer eleminates calls to microMIPS32_to_MIPS32(). Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Switch to using the MIPS rounding modes.Ralf Baechle2014-05-23
| | | | | | | | | | Previously math-emu was using the IEEE-754 constants internally. These were differing by having the constants for rounding to +/- infinity switched, so a conversion was necessary. This would be entirely avoidable if the MIPS constants were used throughout, so get rid of the bloat. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: math-emu: Nuke alternative names for IEEE-754 rounding modes.Ralf Baechle2014-05-23
| | | | Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Sort out mm_isBranchInstr.Ralf Baechle2014-05-23
| | | | | | | | | | | | | | | | | | | | | | | | mm_isBranchInstr() did reside in the math emu code even though it logically is separate and also is used outside the math emu code. In addition GCC 4.9.0 leaves the following unnnecessarily bloated function body for a non-microMIPS configuration: <mm_isBranchInstr>: 105c: afa50004 sw a1,4(sp) 1060: afa60008 sw a2,8(sp) 1064: afa7000c sw a3,12(sp) 1068: 03e00008 jr ra 106c: 00001021 move v0,zero which stores arguments that are never going to be used on the stack frame. Move mm_isBranchInstr() from cp1emu.c to branch.c, then split mm_isBranchInstr() into a __mm_isBranchInstr() core and a mm_isBranchInstr() wrapper inline function which only invokes __mm_isBranchInstr() on microMIPS configurations. This shaves off 112 bytes off the kernel and improves code flow a bit. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-16 19:57:23 -0400