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path: root/arch/arm/mach-omap2/cpuidle44xx.c
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* ARM: OMAP4: cpuidle - remove omap4_idle_data initialization at boot timeDaniel Lezcano2012-05-03
| | | | | | | | | | | | We initialized it at compile time, no need to do that at boot time. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: cpuidle - use the omap4_idle_data variable directlyDaniel Lezcano2012-05-03
| | | | | | | | | | | | | We are storing the 'omap4_idle_data' in the private data field of the cpuidle device. As we are using this variable only in this file, that does not really make sense. Let's use the global variable directly. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: cpuidle - Initialize omap4_idle_data at compile timeDaniel Lezcano2012-05-03
| | | | | | | | | | | | We initialize the omap4_idle_data variable at compile time allowing us to remove in the next patch the initialization done at boot time. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: cpuidle - fix static omap4_idle_data declarationDaniel Lezcano2012-05-03
| | | | | | | | | | | | Add the static declaration for the omap4_idle_data variable because its scope is in the file only. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: cpuidle - Remove the cpuidle_params_table tableDaniel Lezcano2012-05-03
| | | | | | | | | | | | We do not longer need this table as we defined the values in the driver states. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: cpuidle - Declare the states with the driver declarationDaniel Lezcano2012-05-03
| | | | | | | | | | | | | | The cpuidle API allows to declare statically the states in the driver structure. Let's use it. We do no longer need the fill_cstate function called at runtime and by the way adding more instructions at boot time. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: cpuidle - Remove unused valid fieldDaniel Lezcano2012-05-03
| | | | | | | | | | | The 'valid' field is never used in the code, let's remove it. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Reviewed-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: omap: Consolidate OMAP4 time keeping and irq enableRobert Lee2012-03-21
| | | | | | | | | | | Enable core cpuidle timekeeping and irq enabling and remove that handling from this code. Signed-off-by: Robert Lee <rob.lee@linaro.org> Reviewed-by: Kevin Hilman <khilman@ti.com> Reviewed-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Jean Pihet <j-pihet@ti.com> Signed-off-by: Len Brown <len.brown@intel.com>
* ARM: OMAP4: cpuidle: Fix the C-state reporting to cpuidle governor.Santosh Shilimkar2012-02-14
| | | | | | | | | | | | | OMAP4 cpuidle driver is reporting the state requested by governor rather than the actually attempted one. This is obviously misleading sysfs and powertop cpuidle statistics. Fix it so that stats are reported correctly. Reported-by: Kevin Hilman <khilman@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> [khilman@ti.com: minor changelog edits] Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: cpuidle: Switch to gptimer from twd in deeper C-states.Santosh Shilimkar2011-12-08
| | | | | | | | | | | | | | | | | | | | | CPU local timer(TWD) stops when the CPU is transitioning into deeper C-States. Since these timers are not wakeup capable, we need the wakeup capable global timer to program the wakeup time depending on the next timer expiry. It can be handled by registering a global wakeup capable timer along with local timers marked with (mis)feature flag CLOCK_EVT_FEAT_C3STOP. Then notify the clock events layer from idle code using CLOCK_EVT_NOTIFY_BROADCAST_ENTER/EXIT). ARM local timers are already marked with C3STOP feature. Add the notifiers to OMAP4 CPU idle code for the broadcast entry and exit. Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Acked-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>
* ARM: OMAP4: PM: Add CPUidle supportSantosh Shilimkar2011-12-08
Add OMAP4 CPUIDLE support. CPU1 is left with defualt idle and the low power state for it is managed via cpu-hotplug. This patch adds MPUSS low power states in cpuidle. C1 - CPU0 ON + CPU1 ON + MPU ON C2 - CPU0 OFF + CPU1 OFF + MPU CSWR C3 - CPU0 OFF + CPU1 OFF + MPU OSWR OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more anymore just like CORE power domain. The deepest state supported is OSWr. Ofcourse when MPUSS and CORE PD transitions to OSWR along with device off mode, even the memory contemts are lost which is as good as the PD off state. On OMAP4 because of hardware constraints, no low power states are targeted when both CPUs are online and in SMP mode. The low power states are attempted only when secondary CPU gets offline to OFF through hotplug infrastructure. Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive C-state latency profiling. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: Jean Pihet <j-pihet@ti.com> Reviewed-by: Kevin Hilman <khilman@ti.com> Tested-by: Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by: Kevin Hilman <khilman@ti.com>