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| | * ARM: imx: move clock event variables into imx_timerShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | Since we now have imx_timer structure, it makes more sense to move those clock event related variables into the structure, so that we can save some global variables. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: set up .set_next_event hook via imx_gpt_dataShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | Set up .set_next_event hook via imx_gpt_data, so that we can save the use of timer_is_v2(). Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: setup tctl register in device specific functionShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | It creates a gpt device speicific data structure and adds function hook gpt_setup_tctl in there to set up gpt TCTL register. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: initialize gpt device type for DT bootShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | Use different initialization function in CLOCKSOURCE_OF_DECLARE() to initialize gpt device type for DT boot. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: define an enum for gpt timer device typeShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define an enum for gpt timer device type in include/soc/imx/timer.h to tell the gpt block differences among SoCs. Update non-DT users (clock drivers) to pass the device type. As we now have include/soc/imx/timer.h, the declaration of mxc_timer_init() is moved into there as the best fit. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: move timer resources into a structureShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing around as individual argument, let's move timer resources like irq and clocks together with base address into a data structure, and pass pointer of the structure as argument to simplify the function call interface. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: use relaxed IO accessor in timer driverShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | Replace the __raw_readl/__raw_writel with readl_relaxed/writel_relaxed which is endian-safe, as a step of moving the driver code into folder drivers/clocksource. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: make imx51/3 suspend optionalArnd Bergmann2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A recent change to the imx53 power management caused a build regression when CONFIG_SOC_IMX53 is disabled: mach-imx/built-in.o:(.init.rodata+0x60): undefined reference to `imx53_suspend' mach-imx/built-in.o:(.init.rodata+0x64): undefined reference to `imx53_suspend_sz' This avoids the problem by compiling the code in question conditionally on the presence of CONFIG_SOC_IMX53. For consistency, I'm also changing the same thing for CONFIG_SOC_IMX51. An additional benefit of this approach is reduced code size for kernels that only include support for one of the two SoCs. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 1579c7b9fe01 ("ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.") Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: mach-imx: iomux-imx31: Use DECLARE_BITMAPJoe Perches2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | Use the generic mechanism to declare a bitmap instead of unsigned long. Signed-off-by: Joe Perches <joe@perches.com> Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx53: Set DDR pins to high impedance when in suspend to RAM.Martin Fuzzey2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to save power the DDR pins should be put into high impedance when in suspend to RAM. This requires manually requesting self refresh (rather than using the automatic mode implemented by the CCM / ESDCTL), followed by reconfiguring the IOMUXC. Of course the code to do this cannot itself run from DDR so the code is copied to and executed from internal memory. In my tests using a custom i.MX53 board with LPDDR2 RAM this reduced the suspend power consumption from 200mW to 60mW. Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: add msl support for imx7dAnson Huang2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | Add i.MX7D MSL support. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Frank Li <Frank.Li@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: mmdc: Include "common.h" header fileFabio Estevam2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Include the "common.h" header file to fix the following sparse warning: arch/arm/mach-imx/mmdc.c:66:5: warning: symbol 'imx_mmdc_get_ddr_type' was not declared. Should it be static? Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: Correct the comments in time.cShenwei Wang2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | The comments were corrected as the following to reflect the real situation of Freescale MXC timer IP block. There are totally 4 version of the timer on Freescale i.MX SoCs. Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: Remove the duplicated function declarationShenwei Wang2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | Removed the duplicated function declaration of mxc_timer_init which was already declared in drivers/clk/imx/clk.h. Signed-off-by: Shenwei Wang <shenwei.wang@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: Constify irq_domain_opsKrzysztof Kozlowski2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | The irq_domain_ops are not modified by the driver and the irqdomain core code accepts pointer to a const data. Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx6: initialize CCM_CLPCR_LPM into RUN mode earlierShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 4631960d26da ("ARM: imx6: set initial power mode in pm function") moves imx6_set_lpm() from clock init function into imx6_pm_common_init(). This causes a hang when cpuidle support is enabled. The reason for that is ARM core clock is shut down unexpectedly by WAIT mode. It happens with the following call stack: cpuidle_register_governor() cpuidle_switch_governor() cpuidle_uninstall_idle_handler() synchronize_sched() wait_rcu_gp() wait_for_completion() When wait_for_completion() is called as above, all cores are idle/WFI. Hence, the reset value of CCM_CLPCR_LPM - WAIT mode, will trigger a hardware shutdown of the ARM core clock. To fix the regression, we need to ensure that CCM_CLPCR_LPM is initialized into RUN mode earlier than cpuidle governor registration, which is a postcore_initcall. This patch creates function imx6_pm_ccm_init() to map CCM block and initialize CCM_CLPCR_LPM into RUN mode, and have the function called from machine .init_irq hook, which should be early enough. Reported-by: Kevin Hilman <khilman@kernel.org> Fixes: 8fb76a07e2cb ("ARM: imx6: set initial power mode in pm function") Tested-by: Kevin Hilman <khilman@linaro.org> Tested-by: Tyler Baker <tyler.baker@linaro.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: move clock drivers into drivers/clkShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | After the cleanup on clock drivers, they are now ready to be moved into drivers/clk. Let's move them into drivers/clk/imx folder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| | * ARM: imx: remove inclusions of platform headersShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | With the cleanup done before, we now can simply define base address and irq as needed in clock driver, to get those platform header inclusions removed. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: add clk-pllv1 type supportShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of calling cpu_is_xxx() in clk-pllv1 driver, let's add clk-pllv1 type support to handle the difference/quirk in particular SoC designs. Doing so will help get clk-pllv1 driver ready for being moved out of arch/arm/mach-imx folder. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx6: do not use cpu_is_xxx() in clock driverShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | As we're about to move clock drivers out of arch/arm/mach-imx, cpu_is_xxx() shouldn't be used any more. Let's avoid the call by looking at the device tree machine compatible string to determine which SoC the clock driver is running on. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx6: let pm code map CCM block on its ownShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | We are about to move imx6 clock driver into drivers/clk, so let's get imx6 pm code map CCM block on its own rather than relying on clock driver to do the mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx6: set initial power mode in pm functionShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than setting initial low-power mode in every single i.MX6 clock initialization function, we should really do that in pm code. Let's move imx6q_set_lpm(WAIT_CLOCKED) call into imx6_pm_common_init(). While at it, let's rename the function to imx6_set_lpm() since it's actually common for all i.MX6 SoCs. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx5: let pm code map CCM block on its ownShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | We are about to move imx5 clock driver into drivers/clk, so let's get imx5 pm code map CCM block on its own rather than relying on clock driver to do the mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: move revision definitions and declarations into a headerShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | The revision definitions and declarations are widely used by clock drivers. As a step of moving clock drivers out of arch/arm/mach-imx, let's create header include/soc/imx/revision.h to accommodate them. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: use dynamic mapping for CCMShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | Replace the static mapping of CCM block in clock drivers with dynamic mapping. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * ARM: imx: use dynamic mapping for timerShawn Guo2015-06-03
| | | | | | | | | | | | | | | | | | | | | | | | Pass physical address of timer block to mxc_timer_init() call, which in turn does dynamic mapping within the function. Thus, we can avoid using static mapping in clock drivers. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | ARM: vf610: enable Cortex-M4 configuration on Vybrid SoCStefan Agner2015-05-20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows to build the Kernel for Vybrid (VF6xx) SoC when ARMv7-M CPU is selected. The resulting image runs on the secondary Cortex-M4 core. This core has equally access to all peripherals as the main Cortex-A5 core. However, there is no resource control mechanism, hence when both cores are used simultaneously, orthogonal device tree's are required. The boot CPU is dependent on the SoC variant. The available boards use mostly variants where the Cortex-A5 is the primary and hence the boot CPU. Booting the secondary Cortex-M4 CPU needs SoC specific registers written. There is no in kernel support for this right now, a external userspace utility called "m4boot" can be used to boot the kernel: m4boot xipImage initramfs.cpio.lzo vf610m4-colibri.dtb Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* | | Merge tag 'armsoc-cleanup' of ↵Linus Torvalds2015-06-26
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC cleanups from Kevin Hilman: "A relatively small setup of cleanups this time around, and similar to last time the bulk of it is removal of legacy board support: - OMAP: removal of legacy (non-DT) booting for several platforms - i.MX: remove some legacy board files" * tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (36 commits) ARM: fix EFM32 build breakage caused by cpu_resume_arm ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state ARM: v7 setup function should invalidate L1 cache mach-omap2: Remove use of deprecated marco, PTR_RET in devices.c ARM: OMAP2+: Remove calls to deprecacted marco,PTR_RET in the files,fb.c and pmu.c ARM: OMAP2+: Constify irq_domain_ops ARM: OMAP2+: use symbolic defines for console loglevels instead of numbers ARM: at91: remove useless Makefile.boot ARM: at91: remove at91rm9200_sdramc.h ARM: at91: remove mach/at91_ramc.h and mach/at91rm9200_mc.h ARM: at91/pm: use the atmel-mc syscon defines pcmcia: at91_cf: Use syscon to configure the MC/smc ARM: at91: declare the at91rm9200 memory controller as a syscon mfd: syscon: Add Atmel MC (Memory Controller) registers definition ARM: at91: drop sam9_smc.c ata: at91: use syscon to configure the smc ARM: ux500: delete static resource defines ARM: ux500: rename ux500_map_io ARM: ux500: look up PRCMU resource from DT ARM: ux500: kill off L2CC static map ...
| * \ \ Merge branch 'for-arm-soc' of ↵Kevin Hilman2015-06-12
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://ftp.arm.linux.org.uk/pub/armlinux/kernel/git-cur/linux-2.6-arm into next/cleanup * 'for-arm-soc' of http://ftp.arm.linux.org.uk/pub/armlinux/kernel/git-cur/linux-2.6-arm: ARM: fix EFM32 build breakage caused by cpu_resume_arm ARM: 8389/1: Add cpu_resume_arm() for firmwares that resume in ARM state ARM: v7 setup function should invalidate L1 cache
| | * | | ARM: v7 setup function should invalidate L1 cacheRussell King2015-06-01
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | All ARMv5 and older CPUs invalidate their caches in the early assembly setup function, prior to enabling the MMU. This is because the L1 cache should not contain any data relevant to the execution of the kernel at this point; all data should have been flushed out to memory. This requirement should also be true for ARMv6 and ARMv7 CPUs - indeed, these typically do not search their caches when caching is disabled (as it needs to be when the MMU is disabled) so this change should be safe. ARMv7 allows there to be CPUs which search their caches while caching is disabled, and it's permitted that the cache is uninitialised at boot; for these, the architecture reference manual requires that an implementation specific code sequence is used immediately after reset to ensure that the cache is placed into a sane state. Such functionality is definitely outside the remit of the Linux kernel, and must be done by the SoC's firmware before _any_ CPU gets to the Linux kernel. Changing the data cache clean+invalidate to a mere invalidate allows us to get rid of a lot of platform specific hacks around this issue for their secondary CPU bringup paths - some of which were buggy. Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Florian Fainelli <f.fainelli@gmail.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by: Shawn Guo <shawn.guo@linaro.org> Tested-by: Thierry Reding <treding@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Michal Simek <michal.simek@xilinx.com> Tested-by: Wei Xu <xuwei5@hisilicon.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
| * | | | Merge tag 'imx-cleanup-4.2' of ↵Arnd Bergmann2015-06-01
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/cleanup Merge "The i.MX cleanup for 4.2" from Shawn Guo: - Remove eukrea_mbimxsd35 non-DT board files - Remove .owner field from gpc platform driver * tag 'imx-cleanup-4.2' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: ARM: imx: gpc: Remove .owner field ARM: imx: Remove eukrea_mbimxsd35 non-dt support
| | * | | | ARM: imx: gpc: Remove .owner fieldFabio Estevam2015-05-11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This platform_driver does not need to set an owner as it will be populated by the driver core. The semantic patch that makes this change is available in scripts/coccinelle/api/platform_no_drv_owner.cocci. More information about semantic patching is available at http://coccinelle.lip6.fr/ Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| | * | | | ARM: imx: Remove eukrea_mbimxsd35 non-dt supportFabio Estevam2015-05-11
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | eukrea_mbimxsd35 board has device tree support, so we can get rid of the board related files. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | | Merge branch 'for-arm-soc' of git://ftp.arm.linux.org.uk/~rmk/linux-arm into ↵Arnd Bergmann2015-05-29
| |\ \ \ \ | | | |/ / | | |/| / | | |_|/ | |/| | | | | | | | | | | | | | | | | | next/cleanup Merge cleanups from Russell King: * 'for-arm-soc' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: ARM: Show proper respect for Heinrich Hertz by using the correct unit for frequency
| | * | ARM: Show proper respect for Heinrich Hertz by using the correct unit for ↵Russell King2015-05-14
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | frequency The SI unit of frequency is Hertz, named after Heinrich Hertz, and is given the symbol "Hz" to denote this. "hz" is not the unit of frequency, and is in fact meaningless. Fix arch/arm to correctly use "Hz", thereby acknowledging Heinrich Hertz' contribution to the modern world. Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Robert Jarzmik <robert.jarzmik@free.fr> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
* | | ARM: imx6: gpc: don't register power domain if DT data is missingLucas Stach2015-05-27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the devicetree is too old and does not provide the regulator and clocks for the power domain, we need to avoid registering the power domain. Otherwise runtime PM will try to control the domain, which will lead to machine hangs without the proper DT configuration data. This restores functionality to the kernel 4.0 level if an old DT is detected, where the power domain is constantly powered on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | | ARM: imx6: allow booting with old DTLucas Stach2015-05-27
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPC rewrite to IRQ domains has been on the premise that it may break suspend/resume for new kernels on old DT, but otherwise keep things working from a user perspective. This was an accepted compromise to be able to move the GIC cleanup forward. What actually happened was that booting a new kernel on an old DT crashes before even the console is up, so the user does not even see the warning that the DT is too old. The warning message suggests that this has been known before, which is clearly unacceptable. Fix the early crash by mapping the GPC memory space if the IRQ controller doesn't claim it. This keeps at least CPUidle and the needed CPU wakeup workarounds working. With this fixed the system is able to boot up properly minus the expected suspend/resume breakage. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* / ARM: mach-imx: devices: platform-sdhci-esdhc-imx: fix broken email addressWolfram Sang2015-04-27
|/ | | | | | | | | | My Pengutronix address is not valid anymore, redirect people to the Pengutronix kernel team. Reported-by: Harald Geyer <harald@ccbib.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de> Acked-by: Robert Schwebel <r.schwebel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Merge tag 'armsoc-late' of ↵Linus Torvalds2015-04-22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC late changes from Olof Johansson: "We were expecting to sit on this branch through most of the merge window since the contents was merged into our tree late, but we ended up sitting on all of our contents so it can go in with the rest. The contents here is: - a large branch of cleanups of the CM/PRM blocks on OMAP. - a couple of patches plumbing up CM/PRM on OMAP5 and DRA7. - a branch with DT updates for Freescale i.MX. including some shuffling from .dts to .dtsi (include) files that causes a little churn" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits) ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON ARM: OMAP4+: control: add support for initializing control module via DT ARM: dts: dra7: add minimal l4 bus layout with control module support ARM: dts: omap5: add minimal l4 bus layout with control module support ARM: OMAP4+: control: remove support for legacy pad read/write ARM: OMAP4: display: convert display to use syscon for dsi muxing ARM: dts: omap4: add minimal l4 bus layout with control module support ARM: dts: am4372: add minimal l4 bus layout with control module support ARM: dts: am43xx-epos-evm: fix pinmux node layout ARM: dts: am33xx: add minimal l4 bus layout with control module support ARM: dts: omap3: add minimal l4 bus layout with control module support ARM: dts: omap24xx: add minimal l4 bus layout with control module support ARM: OMAP2+: control: add syscon support for register accesses ARM: OMAP2+: id: cache omap_type value ARM: OMAP2+: control: remove API for getting control module base address ARM: OMAP2+: clock: add low-level support for regmap ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags ARM: OMAP2+: CM: move SoC specific init calls within a generic API ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility ...
| * ARM: imx6: Warn when an old DT is detectedMarc Zyngier2015-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | Now that the GPC has been converted to be a full blown irqchip (and not a mole on the side of the GIC), booting a new kernel with an old DT is likely to result in a rough ride for the user. This patch makes sure such a situation is promptly detected and the user made aware that a DT update is in order. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6: Allow GPC interrupts affinity to be changedMarc Zyngier2015-03-30
| | | | | | | | | | | | | | | | | | | | | | | | While converting the GPC code to a stacked irqchip, we lost the possibility to change the CPU affinity of an interrupt routed through the GPC. This patch restore the expected behaviour by forwarding the affinity setup to the underlying irqchip (GIC). Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx6: convert GPC to stacked domainsMarc Zyngier2015-03-30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IMX6 has been (ab)using the gic_arch_extn to provide wakeup from suspend, and it makes a lot of sense to convert this code to use stacked domains instead. This patch does just this, updating the DT files to actually reflect what the HW provides. BIG FAT WARNING: because the DTs were so far lying by not exposing the fact that the GPC block is actually the first interrupt controller in the chain, kernels with this patch applied wont have any suspend-resume facility when booted with old DTs, and old kernels with updated DTs won't even boot. Tested-by: Stefan Agner <stefan@agner.ch> Acked-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * Merge remote-tracking branch 'jcooper/irqchip/vybrid' into imx/dtShawn Guo2015-03-30
| |\
| * \ Merge branch 'imx/soc' into imx/dtShawn Guo2015-03-30
| |\ \
* | \ \ Merge tag 'armsoc-soc' of ↵Linus Torvalds2015-04-22
|\ \ \ \ | | |/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Olof Johansson: "Our SoC branch usually contains expanded support for new SoCs and other core platform code. In this case, that includes: - support for the new Annapurna Labs "Alpine" platform - a rework greatly simplifying adding new platform support to the MCPM subsystem (Multi-cluster power management) - cpuidle and PM improvements for Exynos3250 - misc updates for Renesas, OMAP, Meson, i.MX. Some of these could have gone in other branches but ended up here for various reasons" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits) ARM: alpine: add support for generic pci ARM: Exynos: migrate DCSCB to the new MCPM backend abstraction ARM: vexpress: migrate DCSCB to the new MCPM backend abstraction ARM: vexpress: DCSCB: tighten CPU validity assertion ARM: vexpress: migrate TC2 to the new MCPM backend abstraction ARM: MCPM: move the algorithmic complexity to the core code ARM: EXYNOS: allow cpuidle driver usage on Exynos3250 SoC ARM: EXYNOS: add AFTR mode support for Exynos3250 ARM: EXYNOS: add code for setting/clearing boot flag ARM: EXYNOS: fix CPU1 hotplug on Exynos3250 ARM: S3C64XX: Use fixed IRQ bases to avoid conflicts on Cragganmore ARM: cygnus: fix const declaration bcm_cygnus_dt_compat ARM: DRA7: hwmod: Fix the hwmod class for GPTimer4 ARM: DRA7: hwmod: Add data for GPTimers 13 through 16 ARM: EXYNOS: Remove left over 'extra_save' ARM: EXYNOS: Constify exynos_pm_data array ARM: EXYNOS: use static in suspend.c ARM: EXYNOS: Use platform device name as power domain name ARM: EXYNOS: add support for async-bridge clocks for pm_domains ARM: omap-device: add missed callback for suspend-to-disk ...
| * | | ARM: imx: depend MXC debug board on 3DS machinesStefan Agner2015-03-13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Depend the MXC debug board on machines which actually support it. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6: gpc: Add PU power domain for GPU/VPUPhilipp Zabel2015-03-10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When generic pm domain support is enabled, the PGC can be used to completely gate power to the PU power domain containing GPU3D, GPU2D, and VPU cores. This code triggers the PGC powerdown sequence to disable the GPU/VPU isolation cells and gate power and then disables the PU regulator. To reenable, the reverse powerup sequence is triggered after the PU regulator is enabled again. The GPU and VPU devices in the PU power domain temporarily need to be clocked during powerup, so that the reset machinery can work. [Avoid explicit regulator enabling in probe, unless !PM] Signed-off-by: Markus Pargmann <mpa@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: clk: Add support for mipi_ipg clock as a shared clock gateLiu Ying2015-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CG8 field of the CCM CCGR3 register is the 'mipi_core_cfg' gate clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the ipg clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs takes the ipg clock as the pclk - the APB clock signal . In order to gate/ungate the ipg clock, this patch adds a new shared clock gate named as "mipi_ipg". Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: clk: Add support for mipi_core_cfg clock as a shared clock gateLiu Ying2015-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the hsi_tx_sel clock's output and the video_27m clock's output. The MIPI DSI host controller embedded in the i.MX6q/sdl SoCs uses the video_27m clock to generate PLL reference clock and MIPI core configuration clock. In order to gate/ungate the two MIPI DSI host controller relevant clocks, this patch adds the mipi_core_cfg clock as a shared clock gate. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * | | ARM: imx6q: clk: Change hsi_tx clock to be a shared clock gateLiu Ying2015-03-02
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CG8 field of the CCM CCGR3 register is named as 'mipi_core_cfg' clock, according to the i.MX6q/sdl reference manuals. This clock is actually the gate for several clocks, including the hsi_tx_sel clock's output and the video_27m clock's output. So, this patch changes the hsi_tx clock to be a shared clock gate. Suggested-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Liu Ying <Ying.Liu@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
generated by cgit v1.2.2 (git 2.25.0) at 2025-04-09 07:29:04 -0400