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path: root/drivers/video/exynos/exynos_dp_reg.c
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Diffstat (limited to 'drivers/video/exynos/exynos_dp_reg.c')
-rw-r--r--drivers/video/exynos/exynos_dp_reg.c58
1 files changed, 38 insertions, 20 deletions
diff --git a/drivers/video/exynos/exynos_dp_reg.c b/drivers/video/exynos/exynos_dp_reg.c
index 2db5b9aa250a..3f5ca8a0d5ea 100644
--- a/drivers/video/exynos/exynos_dp_reg.c
+++ b/drivers/video/exynos/exynos_dp_reg.c
@@ -77,7 +77,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3); 77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
78 78
79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
80 TX_CUR1_2X | TX_CUR_8_MA; 80 TX_CUR1_2X | TX_CUR_16_MA;
81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1); 81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
82 82
83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
@@ -148,9 +148,6 @@ void exynos_dp_reset(struct exynos_dp_device *dp)
148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH); 148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
149 149
150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL); 150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
151
152 exynos_dp_init_analog_param(dp);
153 exynos_dp_init_interrupt(dp);
154} 151}
155 152
156void exynos_dp_swreset(struct exynos_dp_device *dp) 153void exynos_dp_swreset(struct exynos_dp_device *dp)
@@ -179,7 +176,7 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
179 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK); 176 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
180} 177}
181 178
182u32 exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp) 179enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
183{ 180{
184 u32 reg; 181 u32 reg;
185 182
@@ -401,6 +398,7 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
401{ 398{
402 int reg; 399 int reg;
403 int retval = 0; 400 int retval = 0;
401 int timeout_loop = 0;
404 402
405 /* Enable AUX CH operation */ 403 /* Enable AUX CH operation */
406 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2); 404 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
@@ -409,8 +407,15 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
409 407
410 /* Is AUX CH command reply received? */ 408 /* Is AUX CH command reply received? */
411 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); 409 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
412 while (!(reg & RPLY_RECEIV)) 410 while (!(reg & RPLY_RECEIV)) {
411 timeout_loop++;
412 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
413 dev_err(dp->dev, "AUX CH command reply failed!\n");
414 return -ETIMEDOUT;
415 }
413 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA); 416 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
417 usleep_range(10, 11);
418 }
414 419
415 /* Clear interrupt source for AUX CH command reply */ 420 /* Clear interrupt source for AUX CH command reply */
416 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA); 421 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
@@ -471,7 +476,8 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
471 if (retval == 0) 476 if (retval == 0)
472 break; 477 break;
473 else 478 else
474 dev_err(dp->dev, "Aux Transaction fail!\n"); 479 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
480 __func__);
475 } 481 }
476 482
477 return retval; 483 return retval;
@@ -511,7 +517,8 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
511 if (retval == 0) 517 if (retval == 0)
512 break; 518 break;
513 else 519 else
514 dev_err(dp->dev, "Aux Transaction fail!\n"); 520 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
521 __func__);
515 } 522 }
516 523
517 /* Read data buffer */ 524 /* Read data buffer */
@@ -575,7 +582,8 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
575 if (retval == 0) 582 if (retval == 0)
576 break; 583 break;
577 else 584 else
578 dev_err(dp->dev, "Aux Transaction fail!\n"); 585 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
586 __func__);
579 } 587 }
580 588
581 start_offset += cur_data_count; 589 start_offset += cur_data_count;
@@ -632,7 +640,8 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
632 if (retval == 0) 640 if (retval == 0)
633 break; 641 break;
634 else 642 else
635 dev_err(dp->dev, "Aux Transaction fail!\n"); 643 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
644 __func__);
636 } 645 }
637 646
638 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 647 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -677,7 +686,7 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
677 /* Start AUX transaction */ 686 /* Start AUX transaction */
678 retval = exynos_dp_start_aux_transaction(dp); 687 retval = exynos_dp_start_aux_transaction(dp);
679 if (retval != 0) 688 if (retval != 0)
680 dev_err(dp->dev, "Aux Transaction fail!\n"); 689 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
681 690
682 return retval; 691 return retval;
683} 692}
@@ -717,7 +726,8 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
717 if (retval == 0) 726 if (retval == 0)
718 break; 727 break;
719 else 728 else
720 dev_err(dp->dev, "Aux Transaction fail!\n"); 729 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
730 __func__);
721 } 731 }
722 732
723 /* Read data */ 733 /* Read data */
@@ -777,7 +787,9 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
777 if (retval == 0) 787 if (retval == 0)
778 break; 788 break;
779 else 789 else
780 dev_err(dp->dev, "Aux Transaction fail!\n"); 790 dev_dbg(dp->dev,
791 "%s: Aux Transaction fail!\n",
792 __func__);
781 } 793 }
782 /* Check if Rx sends defer */ 794 /* Check if Rx sends defer */
783 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM); 795 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
@@ -883,7 +895,9 @@ void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
883{ 895{
884 u32 reg; 896 u32 reg;
885 897
886 reg = level << PRE_EMPHASIS_SET_SHIFT; 898 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
899 reg &= ~PRE_EMPHASIS_SET_MASK;
900 reg |= level << PRE_EMPHASIS_SET_SHIFT;
887 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL); 901 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
888} 902}
889 903
@@ -891,7 +905,9 @@ void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
891{ 905{
892 u32 reg; 906 u32 reg;
893 907
894 reg = level << PRE_EMPHASIS_SET_SHIFT; 908 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
909 reg &= ~PRE_EMPHASIS_SET_MASK;
910 reg |= level << PRE_EMPHASIS_SET_SHIFT;
895 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL); 911 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
896} 912}
897 913
@@ -899,7 +915,9 @@ void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
899{ 915{
900 u32 reg; 916 u32 reg;
901 917
902 reg = level << PRE_EMPHASIS_SET_SHIFT; 918 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
919 reg &= ~PRE_EMPHASIS_SET_MASK;
920 reg |= level << PRE_EMPHASIS_SET_SHIFT;
903 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL); 921 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
904} 922}
905 923
@@ -907,7 +925,9 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
907{ 925{
908 u32 reg; 926 u32 reg;
909 927
910 reg = level << PRE_EMPHASIS_SET_SHIFT; 928 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
929 reg &= ~PRE_EMPHASIS_SET_MASK;
930 reg |= level << PRE_EMPHASIS_SET_SHIFT;
911 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL); 931 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
912} 932}
913 933
@@ -994,7 +1014,7 @@ void exynos_dp_reset_macro(struct exynos_dp_device *dp)
994 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST); 1014 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
995} 1015}
996 1016
997int exynos_dp_init_video(struct exynos_dp_device *dp) 1017void exynos_dp_init_video(struct exynos_dp_device *dp)
998{ 1018{
999 u32 reg; 1019 u32 reg;
1000 1020
@@ -1012,8 +1032,6 @@ int exynos_dp_init_video(struct exynos_dp_device *dp)
1012 1032
1013 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1033 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1014 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8); 1034 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1015
1016 return 0;
1017} 1035}
1018 1036
1019void exynos_dp_set_video_color_format(struct exynos_dp_device *dp, 1037void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 17:36:17 -0500