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-rw-r--r--drivers/scsi/aic7xxx/aic79xx_core.c2
-rw-r--r--drivers/scsi/be2iscsi/be_main.c1
-rw-r--r--drivers/scsi/csiostor/Makefile2
-rw-r--r--drivers/scsi/csiostor/csio_hw.c1175
-rw-r--r--drivers/scsi/csiostor/csio_hw.h49
-rw-r--r--drivers/scsi/csiostor/csio_hw_chip.h65
-rw-r--r--drivers/scsi/csiostor/csio_hw_t4.c404
-rw-r--r--drivers/scsi/csiostor/csio_hw_t5.c150
-rw-r--r--drivers/scsi/csiostor/csio_init.c15
-rw-r--r--drivers/scsi/csiostor/csio_isr.c2
-rw-r--r--drivers/scsi/csiostor/csio_lnode.c2
-rw-r--r--drivers/scsi/csiostor/csio_mb.c56
-rw-r--r--drivers/scsi/csiostor/csio_scsi.c4
-rw-r--r--drivers/scsi/csiostor/csio_wr.c157
-rw-r--r--drivers/scsi/cxgbi/cxgb4i/cxgb4i.c41
-rw-r--r--drivers/scsi/device_handler/scsi_dh.c3
-rw-r--r--drivers/scsi/esas2r/esas2r_init.c5
-rw-r--r--drivers/scsi/ipr.c92
-rw-r--r--drivers/scsi/ipr.h1
-rw-r--r--drivers/scsi/pmcraid.c10
-rw-r--r--drivers/scsi/qla2xxx/tcm_qla2xxx.c4
-rw-r--r--drivers/scsi/scsi.c13
-rw-r--r--drivers/scsi/scsi_debug.c10
-rw-r--r--drivers/scsi/scsi_lib.c14
-rw-r--r--drivers/scsi/scsi_scan.c3
-rw-r--r--drivers/scsi/sd.c6
-rw-r--r--drivers/scsi/sg.c15
-rw-r--r--drivers/scsi/st.c7
-rw-r--r--drivers/scsi/virtio_scsi.c6
29 files changed, 993 insertions, 1321 deletions
diff --git a/drivers/scsi/aic7xxx/aic79xx_core.c b/drivers/scsi/aic7xxx/aic79xx_core.c
index 0bcacf71aef8..97f2accd3dbb 100644
--- a/drivers/scsi/aic7xxx/aic79xx_core.c
+++ b/drivers/scsi/aic7xxx/aic79xx_core.c
@@ -1298,7 +1298,7 @@ rescan_fifos:
1298 1298
1299 /* 1299 /*
1300 * Wait for any inprogress DMA to complete and clear DMA state 1300 * Wait for any inprogress DMA to complete and clear DMA state
1301 * if this if for an SCB in the qinfifo. 1301 * if this is for an SCB in the qinfifo.
1302 */ 1302 */
1303 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) { 1303 while (((ccscbctl = ahd_inb(ahd, CCSCBCTL)) & (CCARREN|CCSCBEN)) != 0) {
1304 1304
diff --git a/drivers/scsi/be2iscsi/be_main.c b/drivers/scsi/be2iscsi/be_main.c
index 9cc047bc763b..a7cc61837818 100644
--- a/drivers/scsi/be2iscsi/be_main.c
+++ b/drivers/scsi/be2iscsi/be_main.c
@@ -48,7 +48,6 @@ static unsigned int be_iopoll_budget = 10;
48static unsigned int be_max_phys_size = 64; 48static unsigned int be_max_phys_size = 64;
49static unsigned int enable_msix = 1; 49static unsigned int enable_msix = 1;
50 50
51MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
52MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR); 51MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
53MODULE_VERSION(BUILD_STR); 52MODULE_VERSION(BUILD_STR);
54MODULE_AUTHOR("Emulex Corporation"); 53MODULE_AUTHOR("Emulex Corporation");
diff --git a/drivers/scsi/csiostor/Makefile b/drivers/scsi/csiostor/Makefile
index 913b9a92fb06..3681a3fbd499 100644
--- a/drivers/scsi/csiostor/Makefile
+++ b/drivers/scsi/csiostor/Makefile
@@ -8,5 +8,5 @@ ccflags-y += -I$(srctree)/drivers/net/ethernet/chelsio/cxgb4
8obj-$(CONFIG_SCSI_CHELSIO_FCOE) += csiostor.o 8obj-$(CONFIG_SCSI_CHELSIO_FCOE) += csiostor.o
9 9
10csiostor-objs := csio_attr.o csio_init.o csio_lnode.o csio_scsi.o \ 10csiostor-objs := csio_attr.o csio_init.o csio_lnode.o csio_scsi.o \
11 csio_hw.o csio_hw_t4.o csio_hw_t5.o csio_isr.o \ 11 csio_hw.o csio_hw_t5.o csio_isr.o \
12 csio_mb.o csio_rnode.o csio_wr.o 12 csio_mb.o csio_rnode.o csio_wr.o
diff --git a/drivers/scsi/csiostor/csio_hw.c b/drivers/scsi/csiostor/csio_hw.c
index 9ab997e18b20..2e66f34ebb79 100644
--- a/drivers/scsi/csiostor/csio_hw.c
+++ b/drivers/scsi/csiostor/csio_hw.c
@@ -60,37 +60,10 @@ int csio_msi = 2;
60static int dev_num; 60static int dev_num;
61 61
62/* FCoE Adapter types & its description */ 62/* FCoE Adapter types & its description */
63static const struct csio_adap_desc csio_t4_fcoe_adapters[] = {
64 {"T440-Dbg 10G", "Chelsio T440-Dbg 10G [FCoE]"},
65 {"T420-CR 10G", "Chelsio T420-CR 10G [FCoE]"},
66 {"T422-CR 10G/1G", "Chelsio T422-CR 10G/1G [FCoE]"},
67 {"T440-CR 10G", "Chelsio T440-CR 10G [FCoE]"},
68 {"T420-BCH 10G", "Chelsio T420-BCH 10G [FCoE]"},
69 {"T440-BCH 10G", "Chelsio T440-BCH 10G [FCoE]"},
70 {"T440-CH 10G", "Chelsio T440-CH 10G [FCoE]"},
71 {"T420-SO 10G", "Chelsio T420-SO 10G [FCoE]"},
72 {"T420-CX4 10G", "Chelsio T420-CX4 10G [FCoE]"},
73 {"T420-BT 10G", "Chelsio T420-BT 10G [FCoE]"},
74 {"T404-BT 1G", "Chelsio T404-BT 1G [FCoE]"},
75 {"B420-SR 10G", "Chelsio B420-SR 10G [FCoE]"},
76 {"B404-BT 1G", "Chelsio B404-BT 1G [FCoE]"},
77 {"T480-CR 10G", "Chelsio T480-CR 10G [FCoE]"},
78 {"T440-LP-CR 10G", "Chelsio T440-LP-CR 10G [FCoE]"},
79 {"AMSTERDAM 10G", "Chelsio AMSTERDAM 10G [FCoE]"},
80 {"HUAWEI T480 10G", "Chelsio HUAWEI T480 10G [FCoE]"},
81 {"HUAWEI T440 10G", "Chelsio HUAWEI T440 10G [FCoE]"},
82 {"HUAWEI STG 10G", "Chelsio HUAWEI STG 10G [FCoE]"},
83 {"ACROMAG XAUI 10G", "Chelsio ACROMAG XAUI 10G [FCoE]"},
84 {"ACROMAG SFP+ 10G", "Chelsio ACROMAG SFP+ 10G [FCoE]"},
85 {"QUANTA SFP+ 10G", "Chelsio QUANTA SFP+ 10G [FCoE]"},
86 {"HUAWEI 10Gbase-T", "Chelsio HUAWEI 10Gbase-T [FCoE]"},
87 {"HUAWEI T4TOE 10G", "Chelsio HUAWEI T4TOE 10G [FCoE]"}
88};
89
90static const struct csio_adap_desc csio_t5_fcoe_adapters[] = { 63static const struct csio_adap_desc csio_t5_fcoe_adapters[] = {
91 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"}, 64 {"T580-Dbg 10G", "Chelsio T580-Dbg 10G [FCoE]"},
92 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"}, 65 {"T520-CR 10G", "Chelsio T520-CR 10G [FCoE]"},
93 {"T522-CR 10G/1G", "Chelsio T452-CR 10G/1G [FCoE]"}, 66 {"T522-CR 10G/1G", "Chelsio T522-CR 10G/1G [FCoE]"},
94 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"}, 67 {"T540-CR 10G", "Chelsio T540-CR 10G [FCoE]"},
95 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"}, 68 {"T520-BCH 10G", "Chelsio T520-BCH 10G [FCoE]"},
96 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"}, 69 {"T540-BCH 10G", "Chelsio T540-BCH 10G [FCoE]"},
@@ -107,7 +80,9 @@ static const struct csio_adap_desc csio_t5_fcoe_adapters[] = {
107 {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"}, 80 {"T580-LP-CR 40G", "Chelsio T580-LP-CR 40G [FCoE]"},
108 {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"}, 81 {"T520-LL-CR 10G", "Chelsio T520-LL-CR 10G [FCoE]"},
109 {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"}, 82 {"T560-CR 40G", "Chelsio T560-CR 40G [FCoE]"},
110 {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"} 83 {"T580-CR 40G", "Chelsio T580-CR 40G [FCoE]"},
84 {"T580-SO 40G", "Chelsio T580-SO 40G [FCoE]"},
85 {"T502-BT 1G", "Chelsio T502-BT 1G [FCoE]"}
111}; 86};
112 87
113static void csio_mgmtm_cleanup(struct csio_mgmtm *); 88static void csio_mgmtm_cleanup(struct csio_mgmtm *);
@@ -188,9 +163,9 @@ void
188csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr, 163csio_hw_tp_wr_bits_indirect(struct csio_hw *hw, unsigned int addr,
189 unsigned int mask, unsigned int val) 164 unsigned int mask, unsigned int val)
190{ 165{
191 csio_wr_reg32(hw, addr, TP_PIO_ADDR); 166 csio_wr_reg32(hw, addr, TP_PIO_ADDR_A);
192 val |= csio_rd_reg32(hw, TP_PIO_DATA) & ~mask; 167 val |= csio_rd_reg32(hw, TP_PIO_DATA_A) & ~mask;
193 csio_wr_reg32(hw, val, TP_PIO_DATA); 168 csio_wr_reg32(hw, val, TP_PIO_DATA_A);
194} 169}
195 170
196void 171void
@@ -256,7 +231,7 @@ csio_hw_seeprom_read(struct csio_hw *hw, uint32_t addr, uint32_t *data)
256 } 231 }
257 232
258 pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data); 233 pci_read_config_dword(hw->pdev, base + PCI_VPD_DATA, data);
259 *data = le32_to_cpu(*data); 234 *data = le32_to_cpu(*(__le32 *)data);
260 235
261 return 0; 236 return 0;
262} 237}
@@ -421,17 +396,15 @@ csio_hw_sf1_read(struct csio_hw *hw, uint32_t byte_cnt, int32_t cont,
421 396
422 if (!byte_cnt || byte_cnt > 4) 397 if (!byte_cnt || byte_cnt > 4)
423 return -EINVAL; 398 return -EINVAL;
424 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) 399 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
425 return -EBUSY; 400 return -EBUSY;
426 401
427 cont = cont ? SF_CONT : 0; 402 csio_wr_reg32(hw, SF_LOCK_V(lock) | SF_CONT_V(cont) |
428 lock = lock ? SF_LOCK : 0; 403 BYTECNT_V(byte_cnt - 1), SF_OP_A);
429 404 ret = csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
430 csio_wr_reg32(hw, lock | cont | BYTECNT(byte_cnt - 1), SF_OP); 405 10, NULL);
431 ret = csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS,
432 10, NULL);
433 if (!ret) 406 if (!ret)
434 *valp = csio_rd_reg32(hw, SF_DATA); 407 *valp = csio_rd_reg32(hw, SF_DATA_A);
435 return ret; 408 return ret;
436} 409}
437 410
@@ -453,16 +426,14 @@ csio_hw_sf1_write(struct csio_hw *hw, uint32_t byte_cnt, uint32_t cont,
453{ 426{
454 if (!byte_cnt || byte_cnt > 4) 427 if (!byte_cnt || byte_cnt > 4)
455 return -EINVAL; 428 return -EINVAL;
456 if (csio_rd_reg32(hw, SF_OP) & SF_BUSY) 429 if (csio_rd_reg32(hw, SF_OP_A) & SF_BUSY_F)
457 return -EBUSY; 430 return -EBUSY;
458 431
459 cont = cont ? SF_CONT : 0; 432 csio_wr_reg32(hw, val, SF_DATA_A);
460 lock = lock ? SF_LOCK : 0; 433 csio_wr_reg32(hw, SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) |
461 434 OP_V(1) | SF_LOCK_V(lock), SF_OP_A);
462 csio_wr_reg32(hw, val, SF_DATA);
463 csio_wr_reg32(hw, cont | BYTECNT(byte_cnt - 1) | OP_WR | lock, SF_OP);
464 435
465 return csio_hw_wait_op_done_val(hw, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 436 return csio_hw_wait_op_done_val(hw, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS,
466 10, NULL); 437 10, NULL);
467} 438}
468 439
@@ -533,11 +504,11 @@ csio_hw_read_flash(struct csio_hw *hw, uint32_t addr, uint32_t nwords,
533 for ( ; nwords; nwords--, data++) { 504 for ( ; nwords; nwords--, data++) {
534 ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data); 505 ret = csio_hw_sf1_read(hw, 4, nwords > 1, nwords == 1, data);
535 if (nwords == 1) 506 if (nwords == 1)
536 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 507 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
537 if (ret) 508 if (ret)
538 return ret; 509 return ret;
539 if (byte_oriented) 510 if (byte_oriented)
540 *data = htonl(*data); 511 *data = (__force __u32) htonl(*data);
541 } 512 }
542 return 0; 513 return 0;
543} 514}
@@ -586,7 +557,7 @@ csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
586 if (ret) 557 if (ret)
587 goto unlock; 558 goto unlock;
588 559
589 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 560 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
590 561
591 /* Read the page to verify the write succeeded */ 562 /* Read the page to verify the write succeeded */
592 ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1); 563 ret = csio_hw_read_flash(hw, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
@@ -603,7 +574,7 @@ csio_hw_write_flash(struct csio_hw *hw, uint32_t addr,
603 return 0; 574 return 0;
604 575
605unlock: 576unlock:
606 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 577 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
607 return ret; 578 return ret;
608} 579}
609 580
@@ -641,7 +612,7 @@ out:
641 if (ret) 612 if (ret)
642 csio_err(hw, "erase of flash sector %d failed, error %d\n", 613 csio_err(hw, "erase of flash sector %d failed, error %d\n",
643 start, ret); 614 start, ret);
644 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 615 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
645 return 0; 616 return 0;
646} 617}
647 618
@@ -665,7 +636,7 @@ csio_hw_print_fw_version(struct csio_hw *hw, char *str)
665static int 636static int
666csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers) 637csio_hw_get_fw_version(struct csio_hw *hw, uint32_t *vers)
667{ 638{
668 return csio_hw_read_flash(hw, FW_IMG_START + 639 return csio_hw_read_flash(hw, FLASH_FW_START +
669 offsetof(struct fw_hdr, fw_ver), 1, 640 offsetof(struct fw_hdr, fw_ver), 1,
670 vers, 0); 641 vers, 0);
671} 642}
@@ -686,43 +657,6 @@ csio_hw_get_tp_version(struct csio_hw *hw, u32 *vers)
686} 657}
687 658
688/* 659/*
689 * csio_hw_check_fw_version - check if the FW is compatible with
690 * this driver
691 * @hw: HW module
692 *
693 * Checks if an adapter's FW is compatible with the driver. Returns 0
694 * if there's exact match, a negative error if the version could not be
695 * read or there's a major/minor version mismatch/minor.
696 */
697static int
698csio_hw_check_fw_version(struct csio_hw *hw)
699{
700 int ret, major, minor, micro;
701
702 ret = csio_hw_get_fw_version(hw, &hw->fwrev);
703 if (!ret)
704 ret = csio_hw_get_tp_version(hw, &hw->tp_vers);
705 if (ret)
706 return ret;
707
708 major = FW_HDR_FW_VER_MAJOR_G(hw->fwrev);
709 minor = FW_HDR_FW_VER_MINOR_G(hw->fwrev);
710 micro = FW_HDR_FW_VER_MICRO_G(hw->fwrev);
711
712 if (major != FW_VERSION_MAJOR(hw)) { /* major mismatch - fail */
713 csio_err(hw, "card FW has major version %u, driver wants %u\n",
714 major, FW_VERSION_MAJOR(hw));
715 return -EINVAL;
716 }
717
718 if (minor == FW_VERSION_MINOR(hw) && micro == FW_VERSION_MICRO(hw))
719 return 0; /* perfect match */
720
721 /* Minor/micro version mismatch */
722 return -EINVAL;
723}
724
725/*
726 * csio_hw_fw_dload - download firmware. 660 * csio_hw_fw_dload - download firmware.
727 * @hw: HW module 661 * @hw: HW module
728 * @fw_data: firmware image to write. 662 * @fw_data: firmware image to write.
@@ -762,9 +696,9 @@ csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size)
762 return -EINVAL; 696 return -EINVAL;
763 } 697 }
764 698
765 if (size > FW_MAX_SIZE) { 699 if (size > FLASH_FW_MAX_SIZE) {
766 csio_err(hw, "FW image too large, max is %u bytes\n", 700 csio_err(hw, "FW image too large, max is %u bytes\n",
767 FW_MAX_SIZE); 701 FLASH_FW_MAX_SIZE);
768 return -EINVAL; 702 return -EINVAL;
769 } 703 }
770 704
@@ -780,10 +714,10 @@ csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size)
780 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */ 714 i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
781 715
782 csio_dbg(hw, "Erasing sectors... start:%d end:%d\n", 716 csio_dbg(hw, "Erasing sectors... start:%d end:%d\n",
783 FW_START_SEC, FW_START_SEC + i - 1); 717 FLASH_FW_START_SEC, FLASH_FW_START_SEC + i - 1);
784 718
785 ret = csio_hw_flash_erase_sectors(hw, FW_START_SEC, 719 ret = csio_hw_flash_erase_sectors(hw, FLASH_FW_START_SEC,
786 FW_START_SEC + i - 1); 720 FLASH_FW_START_SEC + i - 1);
787 if (ret) { 721 if (ret) {
788 csio_err(hw, "Flash Erase failed\n"); 722 csio_err(hw, "Flash Erase failed\n");
789 goto out; 723 goto out;
@@ -796,14 +730,14 @@ csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size)
796 */ 730 */
797 memcpy(first_page, fw_data, SF_PAGE_SIZE); 731 memcpy(first_page, fw_data, SF_PAGE_SIZE);
798 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff); 732 ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
799 ret = csio_hw_write_flash(hw, FW_IMG_START, SF_PAGE_SIZE, first_page); 733 ret = csio_hw_write_flash(hw, FLASH_FW_START, SF_PAGE_SIZE, first_page);
800 if (ret) 734 if (ret)
801 goto out; 735 goto out;
802 736
803 csio_dbg(hw, "Writing Flash .. start:%d end:%d\n", 737 csio_dbg(hw, "Writing Flash .. start:%d end:%d\n",
804 FW_IMG_START, FW_IMG_START + size); 738 FW_IMG_START, FW_IMG_START + size);
805 739
806 addr = FW_IMG_START; 740 addr = FLASH_FW_START;
807 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) { 741 for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
808 addr += SF_PAGE_SIZE; 742 addr += SF_PAGE_SIZE;
809 fw_data += SF_PAGE_SIZE; 743 fw_data += SF_PAGE_SIZE;
@@ -813,7 +747,7 @@ csio_hw_fw_dload(struct csio_hw *hw, uint8_t *fw_data, uint32_t size)
813 } 747 }
814 748
815 ret = csio_hw_write_flash(hw, 749 ret = csio_hw_write_flash(hw,
816 FW_IMG_START + 750 FLASH_FW_START +
817 offsetof(struct fw_hdr, fw_ver), 751 offsetof(struct fw_hdr, fw_ver),
818 sizeof(hdr->fw_ver), 752 sizeof(hdr->fw_ver),
819 (const uint8_t *)&hdr->fw_ver); 753 (const uint8_t *)&hdr->fw_ver);
@@ -833,7 +767,7 @@ csio_hw_get_flash_params(struct csio_hw *hw)
833 ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID); 767 ret = csio_hw_sf1_write(hw, 1, 1, 0, SF_RD_ID);
834 if (!ret) 768 if (!ret)
835 ret = csio_hw_sf1_read(hw, 3, 0, 1, &info); 769 ret = csio_hw_sf1_read(hw, 3, 0, 1, &info);
836 csio_wr_reg32(hw, 0, SF_OP); /* unlock SF */ 770 csio_wr_reg32(hw, 0, SF_OP_A); /* unlock SF */
837 if (ret != 0) 771 if (ret != 0)
838 return ret; 772 return ret;
839 773
@@ -861,17 +795,17 @@ csio_hw_dev_ready(struct csio_hw *hw)
861 uint32_t reg; 795 uint32_t reg;
862 int cnt = 6; 796 int cnt = 6;
863 797
864 while (((reg = csio_rd_reg32(hw, PL_WHOAMI)) == 0xFFFFFFFF) && 798 while (((reg = csio_rd_reg32(hw, PL_WHOAMI_A)) == 0xFFFFFFFF) &&
865 (--cnt != 0)) 799 (--cnt != 0))
866 mdelay(100); 800 mdelay(100);
867 801
868 if ((cnt == 0) && (((int32_t)(SOURCEPF_GET(reg)) < 0) || 802 if ((cnt == 0) && (((int32_t)(SOURCEPF_G(reg)) < 0) ||
869 (SOURCEPF_GET(reg) >= CSIO_MAX_PFN))) { 803 (SOURCEPF_G(reg) >= CSIO_MAX_PFN))) {
870 csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt); 804 csio_err(hw, "PL_WHOAMI returned 0x%x, cnt:%d\n", reg, cnt);
871 return -EIO; 805 return -EIO;
872 } 806 }
873 807
874 hw->pfn = SOURCEPF_GET(reg); 808 hw->pfn = SOURCEPF_G(reg);
875 809
876 return 0; 810 return 0;
877} 811}
@@ -959,8 +893,8 @@ retry:
959 * timeout ... and then retry if we haven't exhausted 893 * timeout ... and then retry if we haven't exhausted
960 * our retries ... 894 * our retries ...
961 */ 895 */
962 pcie_fw = csio_rd_reg32(hw, PCIE_FW); 896 pcie_fw = csio_rd_reg32(hw, PCIE_FW_A);
963 if (!(pcie_fw & (PCIE_FW_ERR|PCIE_FW_INIT))) { 897 if (!(pcie_fw & (PCIE_FW_ERR_F|PCIE_FW_INIT_F))) {
964 if (waiting <= 0) { 898 if (waiting <= 0) {
965 if (retries-- > 0) 899 if (retries-- > 0)
966 goto retry; 900 goto retry;
@@ -976,10 +910,10 @@ retry:
976 * report errors preferentially. 910 * report errors preferentially.
977 */ 911 */
978 if (state) { 912 if (state) {
979 if (pcie_fw & PCIE_FW_ERR) { 913 if (pcie_fw & PCIE_FW_ERR_F) {
980 *state = CSIO_DEV_STATE_ERR; 914 *state = CSIO_DEV_STATE_ERR;
981 rv = -ETIMEDOUT; 915 rv = -ETIMEDOUT;
982 } else if (pcie_fw & PCIE_FW_INIT) 916 } else if (pcie_fw & PCIE_FW_INIT_F)
983 *state = CSIO_DEV_STATE_INIT; 917 *state = CSIO_DEV_STATE_INIT;
984 } 918 }
985 919
@@ -988,9 +922,9 @@ retry:
988 * there's not a valid Master PF, grab its identity 922 * there's not a valid Master PF, grab its identity
989 * for our caller. 923 * for our caller.
990 */ 924 */
991 if (mpfn == PCIE_FW_MASTER_MASK && 925 if (mpfn == PCIE_FW_MASTER_M &&
992 (pcie_fw & PCIE_FW_MASTER_VLD)) 926 (pcie_fw & PCIE_FW_MASTER_VLD_F))
993 mpfn = PCIE_FW_MASTER_GET(pcie_fw); 927 mpfn = PCIE_FW_MASTER_G(pcie_fw);
994 break; 928 break;
995 } 929 }
996 hw->flags &= ~CSIO_HWF_MASTER; 930 hw->flags &= ~CSIO_HWF_MASTER;
@@ -1078,7 +1012,7 @@ csio_do_reset(struct csio_hw *hw, bool fw_rst)
1078 1012
1079 if (!fw_rst) { 1013 if (!fw_rst) {
1080 /* PIO reset */ 1014 /* PIO reset */
1081 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 1015 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
1082 mdelay(2000); 1016 mdelay(2000);
1083 return 0; 1017 return 0;
1084 } 1018 }
@@ -1090,7 +1024,7 @@ csio_do_reset(struct csio_hw *hw, bool fw_rst)
1090 } 1024 }
1091 1025
1092 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, 1026 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
1093 PIORSTMODE | PIORST, 0, NULL); 1027 PIORSTMODE_F | PIORST_F, 0, NULL);
1094 1028
1095 if (csio_mb_issue(hw, mbp)) { 1029 if (csio_mb_issue(hw, mbp)) {
1096 csio_err(hw, "Issue of RESET command failed.n"); 1030 csio_err(hw, "Issue of RESET command failed.n");
@@ -1156,7 +1090,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1156 * If a legitimate mailbox is provided, issue a RESET command 1090 * If a legitimate mailbox is provided, issue a RESET command
1157 * with a HALT indication. 1091 * with a HALT indication.
1158 */ 1092 */
1159 if (mbox <= PCIE_FW_MASTER_MASK) { 1093 if (mbox <= PCIE_FW_MASTER_M) {
1160 struct csio_mb *mbp; 1094 struct csio_mb *mbp;
1161 1095
1162 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC); 1096 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
@@ -1166,7 +1100,7 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1166 } 1100 }
1167 1101
1168 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO, 1102 csio_mb_reset(hw, mbp, CSIO_MB_DEFAULT_TMO,
1169 PIORSTMODE | PIORST, FW_RESET_CMD_HALT_F, 1103 PIORSTMODE_F | PIORST_F, FW_RESET_CMD_HALT_F,
1170 NULL); 1104 NULL);
1171 1105
1172 if (csio_mb_issue(hw, mbp)) { 1106 if (csio_mb_issue(hw, mbp)) {
@@ -1193,8 +1127,9 @@ csio_hw_fw_halt(struct csio_hw *hw, uint32_t mbox, int32_t force)
1193 * rather than a RESET ... if it's new enough to understand that ... 1127 * rather than a RESET ... if it's new enough to understand that ...
1194 */ 1128 */
1195 if (retval == 0 || force) { 1129 if (retval == 0 || force) {
1196 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, UPCRST); 1130 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F);
1197 csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, PCIE_FW_HALT); 1131 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F,
1132 PCIE_FW_HALT_F);
1198 } 1133 }
1199 1134
1200 /* 1135 /*
@@ -1234,7 +1169,7 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1234 * doing it automatically, we need to clear the PCIE_FW.HALT 1169 * doing it automatically, we need to clear the PCIE_FW.HALT
1235 * bit. 1170 * bit.
1236 */ 1171 */
1237 csio_set_reg_field(hw, PCIE_FW, PCIE_FW_HALT, 0); 1172 csio_set_reg_field(hw, PCIE_FW_A, PCIE_FW_HALT_F, 0);
1238 1173
1239 /* 1174 /*
1240 * If we've been given a valid mailbox, first try to get the 1175 * If we've been given a valid mailbox, first try to get the
@@ -1243,21 +1178,21 @@ csio_hw_fw_restart(struct csio_hw *hw, uint32_t mbox, int32_t reset)
1243 * valid mailbox or the RESET command failed, fall back to 1178 * valid mailbox or the RESET command failed, fall back to
1244 * hitting the chip with a hammer. 1179 * hitting the chip with a hammer.
1245 */ 1180 */
1246 if (mbox <= PCIE_FW_MASTER_MASK) { 1181 if (mbox <= PCIE_FW_MASTER_M) {
1247 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0); 1182 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
1248 msleep(100); 1183 msleep(100);
1249 if (csio_do_reset(hw, true) == 0) 1184 if (csio_do_reset(hw, true) == 0)
1250 return 0; 1185 return 0;
1251 } 1186 }
1252 1187
1253 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 1188 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
1254 msleep(2000); 1189 msleep(2000);
1255 } else { 1190 } else {
1256 int ms; 1191 int ms;
1257 1192
1258 csio_set_reg_field(hw, CIM_BOOT_CFG, UPCRST, 0); 1193 csio_set_reg_field(hw, CIM_BOOT_CFG_A, UPCRST_F, 0);
1259 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) { 1194 for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
1260 if (!(csio_rd_reg32(hw, PCIE_FW) & PCIE_FW_HALT)) 1195 if (!(csio_rd_reg32(hw, PCIE_FW_A) & PCIE_FW_HALT_F))
1261 return 0; 1196 return 0;
1262 msleep(100); 1197 msleep(100);
1263 ms += 100; 1198 ms += 100;
@@ -1315,116 +1250,6 @@ csio_hw_fw_upgrade(struct csio_hw *hw, uint32_t mbox,
1315 return csio_hw_fw_restart(hw, mbox, reset); 1250 return csio_hw_fw_restart(hw, mbox, reset);
1316} 1251}
1317 1252
1318
1319/*
1320 * csio_hw_fw_config_file - setup an adapter via a Configuration File
1321 * @hw: the HW module
1322 * @mbox: mailbox to use for the FW command
1323 * @mtype: the memory type where the Configuration File is located
1324 * @maddr: the memory address where the Configuration File is located
1325 * @finiver: return value for CF [fini] version
1326 * @finicsum: return value for CF [fini] checksum
1327 * @cfcsum: return value for CF computed checksum
1328 *
1329 * Issue a command to get the firmware to process the Configuration
1330 * File located at the specified mtype/maddress. If the Configuration
1331 * File is processed successfully and return value pointers are
1332 * provided, the Configuration File "[fini] section version and
1333 * checksum values will be returned along with the computed checksum.
1334 * It's up to the caller to decide how it wants to respond to the
1335 * checksums not matching but it recommended that a prominant warning
1336 * be emitted in order to help people rapidly identify changed or
1337 * corrupted Configuration Files.
1338 *
1339 * Also note that it's possible to modify things like "niccaps",
1340 * "toecaps",etc. between processing the Configuration File and telling
1341 * the firmware to use the new configuration. Callers which want to
1342 * do this will need to "hand-roll" their own CAPS_CONFIGS commands for
1343 * Configuration Files if they want to do this.
1344 */
1345static int
1346csio_hw_fw_config_file(struct csio_hw *hw,
1347 unsigned int mtype, unsigned int maddr,
1348 uint32_t *finiver, uint32_t *finicsum, uint32_t *cfcsum)
1349{
1350 struct csio_mb *mbp;
1351 struct fw_caps_config_cmd *caps_cmd;
1352 int rv = -EINVAL;
1353 enum fw_retval ret;
1354
1355 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1356 if (!mbp) {
1357 CSIO_INC_STATS(hw, n_err_nomem);
1358 return -ENOMEM;
1359 }
1360 /*
1361 * Tell the firmware to process the indicated Configuration File.
1362 * If there are no errors and the caller has provided return value
1363 * pointers for the [fini] section version, checksum and computed
1364 * checksum, pass those back to the caller.
1365 */
1366 caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb);
1367 CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
1368 caps_cmd->op_to_write =
1369 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
1370 FW_CMD_REQUEST_F |
1371 FW_CMD_READ_F);
1372 caps_cmd->cfvalid_to_len16 =
1373 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
1374 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
1375 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
1376 FW_LEN16(*caps_cmd));
1377
1378 if (csio_mb_issue(hw, mbp)) {
1379 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD failed!\n");
1380 goto out;
1381 }
1382
1383 ret = csio_mb_fw_retval(mbp);
1384 if (ret != FW_SUCCESS) {
1385 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv);
1386 goto out;
1387 }
1388
1389 if (finiver)
1390 *finiver = ntohl(caps_cmd->finiver);
1391 if (finicsum)
1392 *finicsum = ntohl(caps_cmd->finicsum);
1393 if (cfcsum)
1394 *cfcsum = ntohl(caps_cmd->cfcsum);
1395
1396 /* Validate device capabilities */
1397 if (csio_hw_validate_caps(hw, mbp)) {
1398 rv = -ENOENT;
1399 goto out;
1400 }
1401
1402 /*
1403 * And now tell the firmware to use the configuration we just loaded.
1404 */
1405 caps_cmd->op_to_write =
1406 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
1407 FW_CMD_REQUEST_F |
1408 FW_CMD_WRITE_F);
1409 caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
1410
1411 if (csio_mb_issue(hw, mbp)) {
1412 csio_err(hw, "Issue of FW_CAPS_CONFIG_CMD failed!\n");
1413 goto out;
1414 }
1415
1416 ret = csio_mb_fw_retval(mbp);
1417 if (ret != FW_SUCCESS) {
1418 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv);
1419 goto out;
1420 }
1421
1422 rv = 0;
1423out:
1424 mempool_free(mbp, hw->mb_mempool);
1425 return rv;
1426}
1427
1428/* 1253/*
1429 * csio_get_device_params - Get device parameters. 1254 * csio_get_device_params - Get device parameters.
1430 * @hw: HW module 1255 * @hw: HW module
@@ -1547,7 +1372,8 @@ csio_config_device_caps(struct csio_hw *hw)
1547 } 1372 }
1548 1373
1549 /* Validate device capabilities */ 1374 /* Validate device capabilities */
1550 if (csio_hw_validate_caps(hw, mbp)) 1375 rv = csio_hw_validate_caps(hw, mbp);
1376 if (rv != 0)
1551 goto out; 1377 goto out;
1552 1378
1553 /* Don't config device capabilities if already configured */ 1379 /* Don't config device capabilities if already configured */
@@ -1756,9 +1582,9 @@ csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path)
1756 uint32_t *cfg_data; 1582 uint32_t *cfg_data;
1757 int value_to_add = 0; 1583 int value_to_add = 0;
1758 1584
1759 if (request_firmware(&cf, CSIO_CF_FNAME(hw), dev) < 0) { 1585 if (request_firmware(&cf, FW_CFG_NAME_T5, dev) < 0) {
1760 csio_err(hw, "could not find config file %s, err: %d\n", 1586 csio_err(hw, "could not find config file %s, err: %d\n",
1761 CSIO_CF_FNAME(hw), ret); 1587 FW_CFG_NAME_T5, ret);
1762 return -ENOENT; 1588 return -ENOENT;
1763 } 1589 }
1764 1590
@@ -1798,8 +1624,8 @@ csio_hw_flash_config(struct csio_hw *hw, u32 *fw_cfg_param, char *path)
1798 } 1624 }
1799 if (ret == 0) { 1625 if (ret == 0) {
1800 csio_info(hw, "config file upgraded to %s\n", 1626 csio_info(hw, "config file upgraded to %s\n",
1801 CSIO_CF_FNAME(hw)); 1627 FW_CFG_NAME_T5);
1802 snprintf(path, 64, "%s%s", "/lib/firmware/", CSIO_CF_FNAME(hw)); 1628 snprintf(path, 64, "%s%s", "/lib/firmware/", FW_CFG_NAME_T5);
1803 } 1629 }
1804 1630
1805leave: 1631leave:
@@ -1827,11 +1653,13 @@ leave:
1827static int 1653static int
1828csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param) 1654csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param)
1829{ 1655{
1656 struct csio_mb *mbp = NULL;
1657 struct fw_caps_config_cmd *caps_cmd;
1830 unsigned int mtype, maddr; 1658 unsigned int mtype, maddr;
1831 int rv; 1659 int rv = -EINVAL;
1832 uint32_t finiver = 0, finicsum = 0, cfcsum = 0; 1660 uint32_t finiver = 0, finicsum = 0, cfcsum = 0;
1833 int using_flash;
1834 char path[64]; 1661 char path[64];
1662 char *config_name = NULL;
1835 1663
1836 /* 1664 /*
1837 * Reset device if necessary 1665 * Reset device if necessary
@@ -1851,51 +1679,107 @@ csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param)
1851 rv = csio_hw_flash_config(hw, fw_cfg_param, path); 1679 rv = csio_hw_flash_config(hw, fw_cfg_param, path);
1852 spin_lock_irq(&hw->lock); 1680 spin_lock_irq(&hw->lock);
1853 if (rv != 0) { 1681 if (rv != 0) {
1854 if (rv == -ENOENT) { 1682 /*
1855 /* 1683 * config file was not found. Use default
1856 * config file was not found. Use default 1684 * config file from flash.
1857 * config file from flash. 1685 */
1858 */ 1686 config_name = "On FLASH";
1859 mtype = FW_MEMTYPE_CF_FLASH; 1687 mtype = FW_MEMTYPE_CF_FLASH;
1860 maddr = hw->chip_ops->chip_flash_cfg_addr(hw); 1688 maddr = hw->chip_ops->chip_flash_cfg_addr(hw);
1861 using_flash = 1;
1862 } else {
1863 /*
1864 * we revert back to the hardwired config if
1865 * flashing failed.
1866 */
1867 goto bye;
1868 }
1869 } else { 1689 } else {
1690 config_name = path;
1870 mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param); 1691 mtype = FW_PARAMS_PARAM_Y_G(*fw_cfg_param);
1871 maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16; 1692 maddr = FW_PARAMS_PARAM_Z_G(*fw_cfg_param) << 16;
1872 using_flash = 0;
1873 } 1693 }
1874 1694
1875 hw->cfg_store = (uint8_t)mtype; 1695 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
1696 if (!mbp) {
1697 CSIO_INC_STATS(hw, n_err_nomem);
1698 return -ENOMEM;
1699 }
1700 /*
1701 * Tell the firmware to process the indicated Configuration File.
1702 * If there are no errors and the caller has provided return value
1703 * pointers for the [fini] section version, checksum and computed
1704 * checksum, pass those back to the caller.
1705 */
1706 caps_cmd = (struct fw_caps_config_cmd *)(mbp->mb);
1707 CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
1708 caps_cmd->op_to_write =
1709 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
1710 FW_CMD_REQUEST_F |
1711 FW_CMD_READ_F);
1712 caps_cmd->cfvalid_to_len16 =
1713 htonl(FW_CAPS_CONFIG_CMD_CFVALID_F |
1714 FW_CAPS_CONFIG_CMD_MEMTYPE_CF_V(mtype) |
1715 FW_CAPS_CONFIG_CMD_MEMADDR64K_CF_V(maddr >> 16) |
1716 FW_LEN16(*caps_cmd));
1717
1718 if (csio_mb_issue(hw, mbp)) {
1719 rv = -EINVAL;
1720 goto bye;
1721 }
1722
1723 rv = csio_mb_fw_retval(mbp);
1724 /* If the CAPS_CONFIG failed with an ENOENT (for a Firmware
1725 * Configuration File in FLASH), our last gasp effort is to use the
1726 * Firmware Configuration File which is embedded in the
1727 * firmware. A very few early versions of the firmware didn't
1728 * have one embedded but we can ignore those.
1729 */
1730 if (rv == ENOENT) {
1731 CSIO_INIT_MBP(mbp, caps_cmd, CSIO_MB_DEFAULT_TMO, hw, NULL, 1);
1732 caps_cmd->op_to_write = htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
1733 FW_CMD_REQUEST_F |
1734 FW_CMD_READ_F);
1735 caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
1736
1737 if (csio_mb_issue(hw, mbp)) {
1738 rv = -EINVAL;
1739 goto bye;
1740 }
1741
1742 rv = csio_mb_fw_retval(mbp);
1743 config_name = "Firmware Default";
1744 }
1745 if (rv != FW_SUCCESS)
1746 goto bye;
1747
1748 finiver = ntohl(caps_cmd->finiver);
1749 finicsum = ntohl(caps_cmd->finicsum);
1750 cfcsum = ntohl(caps_cmd->cfcsum);
1876 1751
1877 /* 1752 /*
1878 * Issue a Capability Configuration command to the firmware to get it 1753 * And now tell the firmware to use the configuration we just loaded.
1879 * to parse the Configuration File.
1880 */ 1754 */
1881 rv = csio_hw_fw_config_file(hw, mtype, maddr, &finiver, 1755 caps_cmd->op_to_write =
1882 &finicsum, &cfcsum); 1756 htonl(FW_CMD_OP_V(FW_CAPS_CONFIG_CMD) |
1883 if (rv != 0) 1757 FW_CMD_REQUEST_F |
1758 FW_CMD_WRITE_F);
1759 caps_cmd->cfvalid_to_len16 = htonl(FW_LEN16(*caps_cmd));
1760
1761 if (csio_mb_issue(hw, mbp)) {
1762 rv = -EINVAL;
1884 goto bye; 1763 goto bye;
1764 }
1885 1765
1886 hw->cfg_finiver = finiver; 1766 rv = csio_mb_fw_retval(mbp);
1887 hw->cfg_finicsum = finicsum; 1767 if (rv != FW_SUCCESS) {
1888 hw->cfg_cfcsum = cfcsum; 1768 csio_dbg(hw, "FW_CAPS_CONFIG_CMD returned %d!\n", rv);
1889 hw->cfg_csum_status = true; 1769 goto bye;
1770 }
1890 1771
1772 mempool_free(mbp, hw->mb_mempool);
1891 if (finicsum != cfcsum) { 1773 if (finicsum != cfcsum) {
1892 csio_warn(hw, 1774 csio_warn(hw,
1893 "Config File checksum mismatch: csum=%#x, computed=%#x\n", 1775 "Config File checksum mismatch: csum=%#x, computed=%#x\n",
1894 finicsum, cfcsum); 1776 finicsum, cfcsum);
1895
1896 hw->cfg_csum_status = false;
1897 } 1777 }
1898 1778
1779 /* Validate device capabilities */
1780 rv = csio_hw_validate_caps(hw, mbp);
1781 if (rv != 0)
1782 goto bye;
1899 /* 1783 /*
1900 * Note that we're operating with parameters 1784 * Note that we're operating with parameters
1901 * not supplied by the driver, rather than from hard-wired 1785 * not supplied by the driver, rather than from hard-wired
@@ -1918,56 +1802,184 @@ csio_hw_use_fwconfig(struct csio_hw *hw, int reset, u32 *fw_cfg_param)
1918 /* Post event to notify completion of configuration */ 1802 /* Post event to notify completion of configuration */
1919 csio_post_event(&hw->sm, CSIO_HWE_INIT); 1803 csio_post_event(&hw->sm, CSIO_HWE_INIT);
1920 1804
1921 csio_info(hw, 1805 csio_info(hw, "Successfully configure using Firmware "
1922 "Firmware Configuration File %s, version %#x, computed checksum %#x\n", 1806 "Configuration File %s, version %#x, computed checksum %#x\n",
1923 (using_flash ? "in device FLASH" : path), finiver, cfcsum); 1807 config_name, finiver, cfcsum);
1924
1925 return 0; 1808 return 0;
1926 1809
1927 /* 1810 /*
1928 * Something bad happened. Return the error ... 1811 * Something bad happened. Return the error ...
1929 */ 1812 */
1930bye: 1813bye:
1814 if (mbp)
1815 mempool_free(mbp, hw->mb_mempool);
1931 hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS; 1816 hw->flags &= ~CSIO_HWF_USING_SOFT_PARAMS;
1932 csio_dbg(hw, "Configuration file error %d\n", rv); 1817 csio_warn(hw, "Configuration file error %d\n", rv);
1933 return rv; 1818 return rv;
1934} 1819}
1935 1820
1936/* 1821/* Is the given firmware API compatible with the one the driver was compiled
1937 * Attempt to initialize the adapter via hard-coded, driver supplied 1822 * with?
1938 * parameters ...
1939 */ 1823 */
1940static int 1824static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
1941csio_hw_no_fwconfig(struct csio_hw *hw, int reset)
1942{ 1825{
1943 int rv; 1826
1944 /* 1827 /* short circuit if it's the exact same firmware version */
1945 * Reset device if necessary 1828 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
1946 */ 1829 return 1;
1947 if (reset) { 1830
1948 rv = csio_do_reset(hw, true); 1831#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
1949 if (rv != 0) 1832 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
1950 goto out; 1833 SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
1834 return 1;
1835#undef SAME_INTF
1836
1837 return 0;
1838}
1839
1840/* The firmware in the filesystem is usable, but should it be installed?
1841 * This routine explains itself in detail if it indicates the filesystem
1842 * firmware should be installed.
1843 */
1844static int csio_should_install_fs_fw(struct csio_hw *hw, int card_fw_usable,
1845 int k, int c)
1846{
1847 const char *reason;
1848
1849 if (!card_fw_usable) {
1850 reason = "incompatible or unusable";
1851 goto install;
1951 } 1852 }
1952 1853
1953 /* Get and set device capabilities */ 1854 if (k > c) {
1954 rv = csio_config_device_caps(hw); 1855 reason = "older than the version supported with this driver";
1955 if (rv != 0) 1856 goto install;
1956 goto out; 1857 }
1957 1858
1958 /* device parameters */ 1859 return 0;
1959 rv = csio_get_device_params(hw);
1960 if (rv != 0)
1961 goto out;
1962 1860
1963 /* Configure SGE */ 1861install:
1964 csio_wr_sge_init(hw); 1862 csio_err(hw, "firmware on card (%u.%u.%u.%u) is %s, "
1863 "installing firmware %u.%u.%u.%u on card.\n",
1864 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
1865 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
1866 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
1867 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
1965 1868
1966 /* Post event to notify completion of configuration */ 1869 return 1;
1967 csio_post_event(&hw->sm, CSIO_HWE_INIT); 1870}
1968 1871
1969out: 1872static struct fw_info fw_info_array[] = {
1970 return rv; 1873 {
1874 .chip = CHELSIO_T5,
1875 .fs_name = FW_CFG_NAME_T5,
1876 .fw_mod_name = FW_FNAME_T5,
1877 .fw_hdr = {
1878 .chip = FW_HDR_CHIP_T5,
1879 .fw_ver = __cpu_to_be32(FW_VERSION(T5)),
1880 .intfver_nic = FW_INTFVER(T5, NIC),
1881 .intfver_vnic = FW_INTFVER(T5, VNIC),
1882 .intfver_ri = FW_INTFVER(T5, RI),
1883 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
1884 .intfver_fcoe = FW_INTFVER(T5, FCOE),
1885 },
1886 }
1887};
1888
1889static struct fw_info *find_fw_info(int chip)
1890{
1891 int i;
1892
1893 for (i = 0; i < ARRAY_SIZE(fw_info_array); i++) {
1894 if (fw_info_array[i].chip == chip)
1895 return &fw_info_array[i];
1896 }
1897 return NULL;
1898}
1899
1900static int csio_hw_prep_fw(struct csio_hw *hw, struct fw_info *fw_info,
1901 const u8 *fw_data, unsigned int fw_size,
1902 struct fw_hdr *card_fw, enum csio_dev_state state,
1903 int *reset)
1904{
1905 int ret, card_fw_usable, fs_fw_usable;
1906 const struct fw_hdr *fs_fw;
1907 const struct fw_hdr *drv_fw;
1908
1909 drv_fw = &fw_info->fw_hdr;
1910
1911 /* Read the header of the firmware on the card */
1912 ret = csio_hw_read_flash(hw, FLASH_FW_START,
1913 sizeof(*card_fw) / sizeof(uint32_t),
1914 (uint32_t *)card_fw, 1);
1915 if (ret == 0) {
1916 card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
1917 } else {
1918 csio_err(hw,
1919 "Unable to read card's firmware header: %d\n", ret);
1920 card_fw_usable = 0;
1921 }
1922
1923 if (fw_data != NULL) {
1924 fs_fw = (const void *)fw_data;
1925 fs_fw_usable = fw_compatible(drv_fw, fs_fw);
1926 } else {
1927 fs_fw = NULL;
1928 fs_fw_usable = 0;
1929 }
1930
1931 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
1932 (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
1933 /* Common case: the firmware on the card is an exact match and
1934 * the filesystem one is an exact match too, or the filesystem
1935 * one is absent/incompatible.
1936 */
1937 } else if (fs_fw_usable && state == CSIO_DEV_STATE_UNINIT &&
1938 csio_should_install_fs_fw(hw, card_fw_usable,
1939 be32_to_cpu(fs_fw->fw_ver),
1940 be32_to_cpu(card_fw->fw_ver))) {
1941 ret = csio_hw_fw_upgrade(hw, hw->pfn, fw_data,
1942 fw_size, 0);
1943 if (ret != 0) {
1944 csio_err(hw,
1945 "failed to install firmware: %d\n", ret);
1946 goto bye;
1947 }
1948
1949 /* Installed successfully, update the cached header too. */
1950 memcpy(card_fw, fs_fw, sizeof(*card_fw));
1951 card_fw_usable = 1;
1952 *reset = 0; /* already reset as part of load_fw */
1953 }
1954
1955 if (!card_fw_usable) {
1956 uint32_t d, c, k;
1957
1958 d = be32_to_cpu(drv_fw->fw_ver);
1959 c = be32_to_cpu(card_fw->fw_ver);
1960 k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
1961
1962 csio_err(hw, "Cannot find a usable firmware: "
1963 "chip state %d, "
1964 "driver compiled with %d.%d.%d.%d, "
1965 "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
1966 state,
1967 FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
1968 FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
1969 FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
1970 FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
1971 FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
1972 FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
1973 ret = EINVAL;
1974 goto bye;
1975 }
1976
1977 /* We're using whatever's on the card and it's known to be good. */
1978 hw->fwrev = be32_to_cpu(card_fw->fw_ver);
1979 hw->tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
1980
1981bye:
1982 return ret;
1971} 1983}
1972 1984
1973/* 1985/*
@@ -1977,48 +1989,52 @@ out:
1977 * latest firmware ECANCELED is returned 1989 * latest firmware ECANCELED is returned
1978 */ 1990 */
1979static int 1991static int
1980csio_hw_flash_fw(struct csio_hw *hw) 1992csio_hw_flash_fw(struct csio_hw *hw, int *reset)
1981{ 1993{
1982 int ret = -ECANCELED; 1994 int ret = -ECANCELED;
1983 const struct firmware *fw; 1995 const struct firmware *fw;
1984 const struct fw_hdr *hdr; 1996 struct fw_info *fw_info;
1985 u32 fw_ver; 1997 struct fw_hdr *card_fw;
1986 struct pci_dev *pci_dev = hw->pdev; 1998 struct pci_dev *pci_dev = hw->pdev;
1987 struct device *dev = &pci_dev->dev ; 1999 struct device *dev = &pci_dev->dev ;
2000 const u8 *fw_data = NULL;
2001 unsigned int fw_size = 0;
1988 2002
1989 if (request_firmware(&fw, CSIO_FW_FNAME(hw), dev) < 0) { 2003 /* This is the firmware whose headers the driver was compiled
1990 csio_err(hw, "could not find firmware image %s, err: %d\n", 2004 * against
1991 CSIO_FW_FNAME(hw), ret); 2005 */
2006 fw_info = find_fw_info(CHELSIO_CHIP_VERSION(hw->chip_id));
2007 if (fw_info == NULL) {
2008 csio_err(hw,
2009 "unable to get firmware info for chip %d.\n",
2010 CHELSIO_CHIP_VERSION(hw->chip_id));
1992 return -EINVAL; 2011 return -EINVAL;
1993 } 2012 }
1994 2013
1995 hdr = (const struct fw_hdr *)fw->data; 2014 if (request_firmware(&fw, FW_FNAME_T5, dev) < 0) {
1996 fw_ver = ntohl(hdr->fw_ver); 2015 csio_err(hw, "could not find firmware image %s, err: %d\n",
1997 if (FW_HDR_FW_VER_MAJOR_G(fw_ver) != FW_VERSION_MAJOR(hw)) 2016 FW_FNAME_T5, ret);
1998 return -EINVAL; /* wrong major version, won't do */ 2017 } else {
2018 fw_data = fw->data;
2019 fw_size = fw->size;
2020 }
1999 2021
2000 /* 2022 /* allocate memory to read the header of the firmware on the
2001 * If the flash FW is unusable or we found something newer, load it. 2023 * card
2002 */ 2024 */
2003 if (FW_HDR_FW_VER_MAJOR_G(hw->fwrev) != FW_VERSION_MAJOR(hw) || 2025 card_fw = kmalloc(sizeof(*card_fw), GFP_KERNEL);
2004 fw_ver > hw->fwrev) {
2005 ret = csio_hw_fw_upgrade(hw, hw->pfn, fw->data, fw->size,
2006 /*force=*/false);
2007 if (!ret)
2008 csio_info(hw,
2009 "firmware upgraded to version %pI4 from %s\n",
2010 &hdr->fw_ver, CSIO_FW_FNAME(hw));
2011 else
2012 csio_err(hw, "firmware upgrade failed! err=%d\n", ret);
2013 } else
2014 ret = -EINVAL;
2015 2026
2016 release_firmware(fw); 2027 /* upgrade FW logic */
2028 ret = csio_hw_prep_fw(hw, fw_info, fw_data, fw_size, card_fw,
2029 hw->fw_state, reset);
2017 2030
2031 /* Cleaning up */
2032 if (fw != NULL)
2033 release_firmware(fw);
2034 kfree(card_fw);
2018 return ret; 2035 return ret;
2019} 2036}
2020 2037
2021
2022/* 2038/*
2023 * csio_hw_configure - Configure HW 2039 * csio_hw_configure - Configure HW
2024 * @hw - HW module 2040 * @hw - HW module
@@ -2039,7 +2055,7 @@ csio_hw_configure(struct csio_hw *hw)
2039 } 2055 }
2040 2056
2041 /* HW version */ 2057 /* HW version */
2042 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV); 2058 hw->chip_ver = (char)csio_rd_reg32(hw, PL_REV_A);
2043 2059
2044 /* Needed for FW download */ 2060 /* Needed for FW download */
2045 rv = csio_hw_get_flash_params(hw); 2061 rv = csio_hw_get_flash_params(hw);
@@ -2074,50 +2090,43 @@ csio_hw_configure(struct csio_hw *hw)
2074 if (rv != 0) 2090 if (rv != 0)
2075 goto out; 2091 goto out;
2076 2092
2093 csio_hw_get_fw_version(hw, &hw->fwrev);
2094 csio_hw_get_tp_version(hw, &hw->tp_vers);
2077 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) { 2095 if (csio_is_hw_master(hw) && hw->fw_state != CSIO_DEV_STATE_INIT) {
2078 rv = csio_hw_check_fw_version(hw);
2079 if (rv == -EINVAL) {
2080 2096
2081 /* Do firmware update */ 2097 /* Do firmware update */
2082 spin_unlock_irq(&hw->lock); 2098 spin_unlock_irq(&hw->lock);
2083 rv = csio_hw_flash_fw(hw); 2099 rv = csio_hw_flash_fw(hw, &reset);
2084 spin_lock_irq(&hw->lock); 2100 spin_lock_irq(&hw->lock);
2085 2101
2086 if (rv == 0) { 2102 if (rv != 0)
2087 reset = 0; 2103 goto out;
2088 /* 2104
2089 * Note that the chip was reset as part of the 2105 /* If the firmware doesn't support Configuration Files,
2090 * firmware upgrade so we don't reset it again 2106 * return an error.
2091 * below and grab the new firmware version.
2092 */
2093 rv = csio_hw_check_fw_version(hw);
2094 }
2095 }
2096 /*
2097 * If the firmware doesn't support Configuration
2098 * Files, use the old Driver-based, hard-wired
2099 * initialization. Otherwise, try using the
2100 * Configuration File support and fall back to the
2101 * Driver-based initialization if there's no
2102 * Configuration File found.
2103 */ 2107 */
2104 if (csio_hw_check_fwconfig(hw, param) == 0) { 2108 rv = csio_hw_check_fwconfig(hw, param);
2105 rv = csio_hw_use_fwconfig(hw, reset, param); 2109 if (rv != 0) {
2106 if (rv == -ENOENT) 2110 csio_info(hw, "Firmware doesn't support "
2107 goto out; 2111 "Firmware Configuration files\n");
2108 if (rv != 0) { 2112 goto out;
2109 csio_info(hw,
2110 "No Configuration File present "
2111 "on adapter. Using hard-wired "
2112 "configuration parameters.\n");
2113 rv = csio_hw_no_fwconfig(hw, reset);
2114 }
2115 } else {
2116 rv = csio_hw_no_fwconfig(hw, reset);
2117 } 2113 }
2118 2114
2119 if (rv != 0) 2115 /* The firmware provides us with a memory buffer where we can
2116 * load a Configuration File from the host if we want to
2117 * override the Configuration File in flash.
2118 */
2119 rv = csio_hw_use_fwconfig(hw, reset, param);
2120 if (rv == -ENOENT) {
2121 csio_info(hw, "Could not initialize "
2122 "adapter, error%d\n", rv);
2123 goto out;
2124 }
2125 if (rv != 0) {
2126 csio_info(hw, "Could not initialize "
2127 "adapter, error%d\n", rv);
2120 goto out; 2128 goto out;
2129 }
2121 2130
2122 } else { 2131 } else {
2123 if (hw->fw_state == CSIO_DEV_STATE_INIT) { 2132 if (hw->fw_state == CSIO_DEV_STATE_INIT) {
@@ -2217,7 +2226,7 @@ out:
2217 return; 2226 return;
2218} 2227}
2219 2228
2220#define PF_INTR_MASK (PFSW | PFCIM) 2229#define PF_INTR_MASK (PFSW_F | PFCIM_F)
2221 2230
2222/* 2231/*
2223 * csio_hw_intr_enable - Enable HW interrupts 2232 * csio_hw_intr_enable - Enable HW interrupts
@@ -2229,21 +2238,21 @@ static void
2229csio_hw_intr_enable(struct csio_hw *hw) 2238csio_hw_intr_enable(struct csio_hw *hw)
2230{ 2239{
2231 uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw)); 2240 uint16_t vec = (uint16_t)csio_get_mb_intr_idx(csio_hw_to_mbm(hw));
2232 uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI)); 2241 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2233 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE); 2242 uint32_t pl = csio_rd_reg32(hw, PL_INT_ENABLE_A);
2234 2243
2235 /* 2244 /*
2236 * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up 2245 * Set aivec for MSI/MSIX. PCIE_PF_CFG.INTXType is set up
2237 * by FW, so do nothing for INTX. 2246 * by FW, so do nothing for INTX.
2238 */ 2247 */
2239 if (hw->intr_mode == CSIO_IM_MSIX) 2248 if (hw->intr_mode == CSIO_IM_MSIX)
2240 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG), 2249 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2241 AIVEC(AIVEC_MASK), vec); 2250 AIVEC_V(AIVEC_M), vec);
2242 else if (hw->intr_mode == CSIO_IM_MSI) 2251 else if (hw->intr_mode == CSIO_IM_MSI)
2243 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG), 2252 csio_set_reg_field(hw, MYPF_REG(PCIE_PF_CFG_A),
2244 AIVEC(AIVEC_MASK), 0); 2253 AIVEC_V(AIVEC_M), 0);
2245 2254
2246 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE)); 2255 csio_wr_reg32(hw, PF_INTR_MASK, MYPF_REG(PL_PF_INT_ENABLE_A));
2247 2256
2248 /* Turn on MB interrupts - this will internally flush PIO as well */ 2257 /* Turn on MB interrupts - this will internally flush PIO as well */
2249 csio_mb_intr_enable(hw); 2258 csio_mb_intr_enable(hw);
@@ -2253,19 +2262,19 @@ csio_hw_intr_enable(struct csio_hw *hw)
2253 /* 2262 /*
2254 * Disable the Serial FLASH interrupt, if enabled! 2263 * Disable the Serial FLASH interrupt, if enabled!
2255 */ 2264 */
2256 pl &= (~SF); 2265 pl &= (~SF_F);
2257 csio_wr_reg32(hw, pl, PL_INT_ENABLE); 2266 csio_wr_reg32(hw, pl, PL_INT_ENABLE_A);
2258 2267
2259 csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE | 2268 csio_wr_reg32(hw, ERR_CPL_EXCEED_IQE_SIZE_F |
2260 EGRESS_SIZE_ERR | ERR_INVALID_CIDX_INC | 2269 EGRESS_SIZE_ERR_F | ERR_INVALID_CIDX_INC_F |
2261 ERR_CPL_OPCODE_0 | ERR_DROPPED_DB | 2270 ERR_CPL_OPCODE_0_F | ERR_DROPPED_DB_F |
2262 ERR_DATA_CPL_ON_HIGH_QID1 | 2271 ERR_DATA_CPL_ON_HIGH_QID1_F |
2263 ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 | 2272 ERR_DATA_CPL_ON_HIGH_QID0_F | ERR_BAD_DB_PIDX3_F |
2264 ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 | 2273 ERR_BAD_DB_PIDX2_F | ERR_BAD_DB_PIDX1_F |
2265 ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO | 2274 ERR_BAD_DB_PIDX0_F | ERR_ING_CTXT_PRIO_F |
2266 ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR, 2275 ERR_EGR_CTXT_PRIO_F | INGRESS_SIZE_ERR_F,
2267 SGE_INT_ENABLE3); 2276 SGE_INT_ENABLE3_A);
2268 csio_set_reg_field(hw, PL_INT_MAP0, 0, 1 << pf); 2277 csio_set_reg_field(hw, PL_INT_MAP0_A, 0, 1 << pf);
2269 } 2278 }
2270 2279
2271 hw->flags |= CSIO_HWF_HW_INTR_ENABLED; 2280 hw->flags |= CSIO_HWF_HW_INTR_ENABLED;
@@ -2281,16 +2290,16 @@ csio_hw_intr_enable(struct csio_hw *hw)
2281void 2290void
2282csio_hw_intr_disable(struct csio_hw *hw) 2291csio_hw_intr_disable(struct csio_hw *hw)
2283{ 2292{
2284 uint32_t pf = SOURCEPF_GET(csio_rd_reg32(hw, PL_WHOAMI)); 2293 uint32_t pf = SOURCEPF_G(csio_rd_reg32(hw, PL_WHOAMI_A));
2285 2294
2286 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED)) 2295 if (!(hw->flags & CSIO_HWF_HW_INTR_ENABLED))
2287 return; 2296 return;
2288 2297
2289 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED; 2298 hw->flags &= ~CSIO_HWF_HW_INTR_ENABLED;
2290 2299
2291 csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE)); 2300 csio_wr_reg32(hw, 0, MYPF_REG(PL_PF_INT_ENABLE_A));
2292 if (csio_is_hw_master(hw)) 2301 if (csio_is_hw_master(hw))
2293 csio_set_reg_field(hw, PL_INT_MAP0, 1 << pf, 0); 2302 csio_set_reg_field(hw, PL_INT_MAP0_A, 1 << pf, 0);
2294 2303
2295 /* Turn off MB interrupts */ 2304 /* Turn off MB interrupts */
2296 csio_mb_intr_disable(hw); 2305 csio_mb_intr_disable(hw);
@@ -2300,7 +2309,7 @@ csio_hw_intr_disable(struct csio_hw *hw)
2300void 2309void
2301csio_hw_fatal_err(struct csio_hw *hw) 2310csio_hw_fatal_err(struct csio_hw *hw)
2302{ 2311{
2303 csio_set_reg_field(hw, SGE_CONTROL, GLOBALENABLE, 0); 2312 csio_set_reg_field(hw, SGE_CONTROL_A, GLOBALENABLE_F, 0);
2304 csio_hw_intr_disable(hw); 2313 csio_hw_intr_disable(hw);
2305 2314
2306 /* Do not reset HW, we may need FW state for debugging */ 2315 /* Do not reset HW, we may need FW state for debugging */
@@ -2594,7 +2603,7 @@ csio_hws_removing(struct csio_hw *hw, enum csio_hw_ev evt)
2594 * register directly. 2603 * register directly.
2595 */ 2604 */
2596 csio_err(hw, "Resetting HW and waiting 2 seconds...\n"); 2605 csio_err(hw, "Resetting HW and waiting 2 seconds...\n");
2597 csio_wr_reg32(hw, PIORSTMODE | PIORST, PL_RST); 2606 csio_wr_reg32(hw, PIORSTMODE_F | PIORST_F, PL_RST_A);
2598 mdelay(2000); 2607 mdelay(2000);
2599 break; 2608 break;
2600 2609
@@ -2682,11 +2691,11 @@ static void csio_tp_intr_handler(struct csio_hw *hw)
2682{ 2691{
2683 static struct intr_info tp_intr_info[] = { 2692 static struct intr_info tp_intr_info[] = {
2684 { 0x3fffffff, "TP parity error", -1, 1 }, 2693 { 0x3fffffff, "TP parity error", -1, 1 },
2685 { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 }, 2694 { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
2686 { 0, NULL, 0, 0 } 2695 { 0, NULL, 0, 0 }
2687 }; 2696 };
2688 2697
2689 if (csio_handle_intr_status(hw, TP_INT_CAUSE, tp_intr_info)) 2698 if (csio_handle_intr_status(hw, TP_INT_CAUSE_A, tp_intr_info))
2690 csio_hw_fatal_err(hw); 2699 csio_hw_fatal_err(hw);
2691} 2700}
2692 2701
@@ -2698,52 +2707,52 @@ static void csio_sge_intr_handler(struct csio_hw *hw)
2698 uint64_t v; 2707 uint64_t v;
2699 2708
2700 static struct intr_info sge_intr_info[] = { 2709 static struct intr_info sge_intr_info[] = {
2701 { ERR_CPL_EXCEED_IQE_SIZE, 2710 { ERR_CPL_EXCEED_IQE_SIZE_F,
2702 "SGE received CPL exceeding IQE size", -1, 1 }, 2711 "SGE received CPL exceeding IQE size", -1, 1 },
2703 { ERR_INVALID_CIDX_INC, 2712 { ERR_INVALID_CIDX_INC_F,
2704 "SGE GTS CIDX increment too large", -1, 0 }, 2713 "SGE GTS CIDX increment too large", -1, 0 },
2705 { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 }, 2714 { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
2706 { ERR_DROPPED_DB, "SGE doorbell dropped", -1, 0 }, 2715 { ERR_DROPPED_DB_F, "SGE doorbell dropped", -1, 0 },
2707 { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0, 2716 { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
2708 "SGE IQID > 1023 received CPL for FL", -1, 0 }, 2717 "SGE IQID > 1023 received CPL for FL", -1, 0 },
2709 { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1, 2718 { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
2710 0 }, 2719 0 },
2711 { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1, 2720 { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
2712 0 }, 2721 0 },
2713 { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1, 2722 { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
2714 0 }, 2723 0 },
2715 { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1, 2724 { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
2716 0 }, 2725 0 },
2717 { ERR_ING_CTXT_PRIO, 2726 { ERR_ING_CTXT_PRIO_F,
2718 "SGE too many priority ingress contexts", -1, 0 }, 2727 "SGE too many priority ingress contexts", -1, 0 },
2719 { ERR_EGR_CTXT_PRIO, 2728 { ERR_EGR_CTXT_PRIO_F,
2720 "SGE too many priority egress contexts", -1, 0 }, 2729 "SGE too many priority egress contexts", -1, 0 },
2721 { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 }, 2730 { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
2722 { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 }, 2731 { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
2723 { 0, NULL, 0, 0 } 2732 { 0, NULL, 0, 0 }
2724 }; 2733 };
2725 2734
2726 v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1) | 2735 v = (uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE1_A) |
2727 ((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2) << 32); 2736 ((uint64_t)csio_rd_reg32(hw, SGE_INT_CAUSE2_A) << 32);
2728 if (v) { 2737 if (v) {
2729 csio_fatal(hw, "SGE parity error (%#llx)\n", 2738 csio_fatal(hw, "SGE parity error (%#llx)\n",
2730 (unsigned long long)v); 2739 (unsigned long long)v);
2731 csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF), 2740 csio_wr_reg32(hw, (uint32_t)(v & 0xFFFFFFFF),
2732 SGE_INT_CAUSE1); 2741 SGE_INT_CAUSE1_A);
2733 csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2); 2742 csio_wr_reg32(hw, (uint32_t)(v >> 32), SGE_INT_CAUSE2_A);
2734 } 2743 }
2735 2744
2736 v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3, sge_intr_info); 2745 v |= csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info);
2737 2746
2738 if (csio_handle_intr_status(hw, SGE_INT_CAUSE3, sge_intr_info) || 2747 if (csio_handle_intr_status(hw, SGE_INT_CAUSE3_A, sge_intr_info) ||
2739 v != 0) 2748 v != 0)
2740 csio_hw_fatal_err(hw); 2749 csio_hw_fatal_err(hw);
2741} 2750}
2742 2751
2743#define CIM_OBQ_INTR (OBQULP0PARERR | OBQULP1PARERR | OBQULP2PARERR |\ 2752#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
2744 OBQULP3PARERR | OBQSGEPARERR | OBQNCSIPARERR) 2753 OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
2745#define CIM_IBQ_INTR (IBQTP0PARERR | IBQTP1PARERR | IBQULPPARERR |\ 2754#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
2746 IBQSGEHIPARERR | IBQSGELOPARERR | IBQNCSIPARERR) 2755 IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
2747 2756
2748/* 2757/*
2749 * CIM interrupt handler. 2758 * CIM interrupt handler.
@@ -2751,53 +2760,53 @@ static void csio_sge_intr_handler(struct csio_hw *hw)
2751static void csio_cim_intr_handler(struct csio_hw *hw) 2760static void csio_cim_intr_handler(struct csio_hw *hw)
2752{ 2761{
2753 static struct intr_info cim_intr_info[] = { 2762 static struct intr_info cim_intr_info[] = {
2754 { PREFDROPINT, "CIM control register prefetch drop", -1, 1 }, 2763 { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
2755 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 }, 2764 { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
2756 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 }, 2765 { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
2757 { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 }, 2766 { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
2758 { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 }, 2767 { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
2759 { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 }, 2768 { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
2760 { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 }, 2769 { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
2761 { 0, NULL, 0, 0 } 2770 { 0, NULL, 0, 0 }
2762 }; 2771 };
2763 static struct intr_info cim_upintr_info[] = { 2772 static struct intr_info cim_upintr_info[] = {
2764 { RSVDSPACEINT, "CIM reserved space access", -1, 1 }, 2773 { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
2765 { ILLTRANSINT, "CIM illegal transaction", -1, 1 }, 2774 { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
2766 { ILLWRINT, "CIM illegal write", -1, 1 }, 2775 { ILLWRINT_F, "CIM illegal write", -1, 1 },
2767 { ILLRDINT, "CIM illegal read", -1, 1 }, 2776 { ILLRDINT_F, "CIM illegal read", -1, 1 },
2768 { ILLRDBEINT, "CIM illegal read BE", -1, 1 }, 2777 { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
2769 { ILLWRBEINT, "CIM illegal write BE", -1, 1 }, 2778 { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
2770 { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 }, 2779 { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
2771 { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 }, 2780 { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
2772 { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 }, 2781 { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
2773 { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 }, 2782 { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
2774 { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 }, 2783 { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
2775 { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 }, 2784 { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
2776 { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 }, 2785 { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
2777 { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 }, 2786 { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
2778 { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 }, 2787 { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
2779 { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 }, 2788 { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
2780 { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 }, 2789 { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
2781 { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 }, 2790 { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
2782 { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 }, 2791 { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
2783 { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 }, 2792 { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
2784 { SGLRDPLINT , "CIM single read from PL space", -1, 1 }, 2793 { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
2785 { SGLWRPLINT , "CIM single write to PL space", -1, 1 }, 2794 { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
2786 { BLKRDPLINT , "CIM block read from PL space", -1, 1 }, 2795 { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
2787 { BLKWRPLINT , "CIM block write to PL space", -1, 1 }, 2796 { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
2788 { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 }, 2797 { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
2789 { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 }, 2798 { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
2790 { TIMEOUTINT , "CIM PIF timeout", -1, 1 }, 2799 { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
2791 { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 }, 2800 { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
2792 { 0, NULL, 0, 0 } 2801 { 0, NULL, 0, 0 }
2793 }; 2802 };
2794 2803
2795 int fat; 2804 int fat;
2796 2805
2797 fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE, 2806 fat = csio_handle_intr_status(hw, CIM_HOST_INT_CAUSE_A,
2798 cim_intr_info) + 2807 cim_intr_info) +
2799 csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE, 2808 csio_handle_intr_status(hw, CIM_HOST_UPACC_INT_CAUSE_A,
2800 cim_upintr_info); 2809 cim_upintr_info);
2801 if (fat) 2810 if (fat)
2802 csio_hw_fatal_err(hw); 2811 csio_hw_fatal_err(hw);
2803} 2812}
@@ -2813,7 +2822,7 @@ static void csio_ulprx_intr_handler(struct csio_hw *hw)
2813 { 0, NULL, 0, 0 } 2822 { 0, NULL, 0, 0 }
2814 }; 2823 };
2815 2824
2816 if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE, ulprx_intr_info)) 2825 if (csio_handle_intr_status(hw, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
2817 csio_hw_fatal_err(hw); 2826 csio_hw_fatal_err(hw);
2818} 2827}
2819 2828
@@ -2823,19 +2832,19 @@ static void csio_ulprx_intr_handler(struct csio_hw *hw)
2823static void csio_ulptx_intr_handler(struct csio_hw *hw) 2832static void csio_ulptx_intr_handler(struct csio_hw *hw)
2824{ 2833{
2825 static struct intr_info ulptx_intr_info[] = { 2834 static struct intr_info ulptx_intr_info[] = {
2826 { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1, 2835 { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
2827 0 }, 2836 0 },
2828 { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1, 2837 { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
2829 0 }, 2838 0 },
2830 { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1, 2839 { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
2831 0 }, 2840 0 },
2832 { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1, 2841 { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
2833 0 }, 2842 0 },
2834 { 0xfffffff, "ULPTX parity error", -1, 1 }, 2843 { 0xfffffff, "ULPTX parity error", -1, 1 },
2835 { 0, NULL, 0, 0 } 2844 { 0, NULL, 0, 0 }
2836 }; 2845 };
2837 2846
2838 if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE, ulptx_intr_info)) 2847 if (csio_handle_intr_status(hw, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
2839 csio_hw_fatal_err(hw); 2848 csio_hw_fatal_err(hw);
2840} 2849}
2841 2850
@@ -2845,20 +2854,20 @@ static void csio_ulptx_intr_handler(struct csio_hw *hw)
2845static void csio_pmtx_intr_handler(struct csio_hw *hw) 2854static void csio_pmtx_intr_handler(struct csio_hw *hw)
2846{ 2855{
2847 static struct intr_info pmtx_intr_info[] = { 2856 static struct intr_info pmtx_intr_info[] = {
2848 { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 }, 2857 { PCMD_LEN_OVFL0_F, "PMTX channel 0 pcmd too large", -1, 1 },
2849 { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 }, 2858 { PCMD_LEN_OVFL1_F, "PMTX channel 1 pcmd too large", -1, 1 },
2850 { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 }, 2859 { PCMD_LEN_OVFL2_F, "PMTX channel 2 pcmd too large", -1, 1 },
2851 { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 }, 2860 { ZERO_C_CMD_ERROR_F, "PMTX 0-length pcmd", -1, 1 },
2852 { 0xffffff0, "PMTX framing error", -1, 1 }, 2861 { 0xffffff0, "PMTX framing error", -1, 1 },
2853 { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 }, 2862 { OESPI_PAR_ERROR_F, "PMTX oespi parity error", -1, 1 },
2854 { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 2863 { DB_OPTIONS_PAR_ERROR_F, "PMTX db_options parity error", -1,
2855 1 }, 2864 1 },
2856 { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 }, 2865 { ICSPI_PAR_ERROR_F, "PMTX icspi parity error", -1, 1 },
2857 { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1}, 2866 { PMTX_C_PCMD_PAR_ERROR_F, "PMTX c_pcmd parity error", -1, 1},
2858 { 0, NULL, 0, 0 } 2867 { 0, NULL, 0, 0 }
2859 }; 2868 };
2860 2869
2861 if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE, pmtx_intr_info)) 2870 if (csio_handle_intr_status(hw, PM_TX_INT_CAUSE_A, pmtx_intr_info))
2862 csio_hw_fatal_err(hw); 2871 csio_hw_fatal_err(hw);
2863} 2872}
2864 2873
@@ -2868,17 +2877,17 @@ static void csio_pmtx_intr_handler(struct csio_hw *hw)
2868static void csio_pmrx_intr_handler(struct csio_hw *hw) 2877static void csio_pmrx_intr_handler(struct csio_hw *hw)
2869{ 2878{
2870 static struct intr_info pmrx_intr_info[] = { 2879 static struct intr_info pmrx_intr_info[] = {
2871 { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 }, 2880 { ZERO_E_CMD_ERROR_F, "PMRX 0-length pcmd", -1, 1 },
2872 { 0x3ffff0, "PMRX framing error", -1, 1 }, 2881 { 0x3ffff0, "PMRX framing error", -1, 1 },
2873 { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 }, 2882 { OCSPI_PAR_ERROR_F, "PMRX ocspi parity error", -1, 1 },
2874 { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 2883 { DB_OPTIONS_PAR_ERROR_F, "PMRX db_options parity error", -1,
2875 1 }, 2884 1 },
2876 { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 }, 2885 { IESPI_PAR_ERROR_F, "PMRX iespi parity error", -1, 1 },
2877 { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1}, 2886 { PMRX_E_PCMD_PAR_ERROR_F, "PMRX e_pcmd parity error", -1, 1},
2878 { 0, NULL, 0, 0 } 2887 { 0, NULL, 0, 0 }
2879 }; 2888 };
2880 2889
2881 if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE, pmrx_intr_info)) 2890 if (csio_handle_intr_status(hw, PM_RX_INT_CAUSE_A, pmrx_intr_info))
2882 csio_hw_fatal_err(hw); 2891 csio_hw_fatal_err(hw);
2883} 2892}
2884 2893
@@ -2888,16 +2897,16 @@ static void csio_pmrx_intr_handler(struct csio_hw *hw)
2888static void csio_cplsw_intr_handler(struct csio_hw *hw) 2897static void csio_cplsw_intr_handler(struct csio_hw *hw)
2889{ 2898{
2890 static struct intr_info cplsw_intr_info[] = { 2899 static struct intr_info cplsw_intr_info[] = {
2891 { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 }, 2900 { CIM_OP_MAP_PERR_F, "CPLSW CIM op_map parity error", -1, 1 },
2892 { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 }, 2901 { CIM_OVFL_ERROR_F, "CPLSW CIM overflow", -1, 1 },
2893 { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 }, 2902 { TP_FRAMING_ERROR_F, "CPLSW TP framing error", -1, 1 },
2894 { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 }, 2903 { SGE_FRAMING_ERROR_F, "CPLSW SGE framing error", -1, 1 },
2895 { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 }, 2904 { CIM_FRAMING_ERROR_F, "CPLSW CIM framing error", -1, 1 },
2896 { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 }, 2905 { ZERO_SWITCH_ERROR_F, "CPLSW no-switch error", -1, 1 },
2897 { 0, NULL, 0, 0 } 2906 { 0, NULL, 0, 0 }
2898 }; 2907 };
2899 2908
2900 if (csio_handle_intr_status(hw, CPL_INTR_CAUSE, cplsw_intr_info)) 2909 if (csio_handle_intr_status(hw, CPL_INTR_CAUSE_A, cplsw_intr_info))
2901 csio_hw_fatal_err(hw); 2910 csio_hw_fatal_err(hw);
2902} 2911}
2903 2912
@@ -2907,15 +2916,15 @@ static void csio_cplsw_intr_handler(struct csio_hw *hw)
2907static void csio_le_intr_handler(struct csio_hw *hw) 2916static void csio_le_intr_handler(struct csio_hw *hw)
2908{ 2917{
2909 static struct intr_info le_intr_info[] = { 2918 static struct intr_info le_intr_info[] = {
2910 { LIPMISS, "LE LIP miss", -1, 0 }, 2919 { LIPMISS_F, "LE LIP miss", -1, 0 },
2911 { LIP0, "LE 0 LIP error", -1, 0 }, 2920 { LIP0_F, "LE 0 LIP error", -1, 0 },
2912 { PARITYERR, "LE parity error", -1, 1 }, 2921 { PARITYERR_F, "LE parity error", -1, 1 },
2913 { UNKNOWNCMD, "LE unknown command", -1, 1 }, 2922 { UNKNOWNCMD_F, "LE unknown command", -1, 1 },
2914 { REQQPARERR, "LE request queue parity error", -1, 1 }, 2923 { REQQPARERR_F, "LE request queue parity error", -1, 1 },
2915 { 0, NULL, 0, 0 } 2924 { 0, NULL, 0, 0 }
2916 }; 2925 };
2917 2926
2918 if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE, le_intr_info)) 2927 if (csio_handle_intr_status(hw, LE_DB_INT_CAUSE_A, le_intr_info))
2919 csio_hw_fatal_err(hw); 2928 csio_hw_fatal_err(hw);
2920} 2929}
2921 2930
@@ -2929,19 +2938,22 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
2929 { 0, NULL, 0, 0 } 2938 { 0, NULL, 0, 0 }
2930 }; 2939 };
2931 static struct intr_info mps_tx_intr_info[] = { 2940 static struct intr_info mps_tx_intr_info[] = {
2932 { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 }, 2941 { TPFIFO_V(TPFIFO_M), "MPS Tx TP FIFO parity error", -1, 1 },
2933 { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 }, 2942 { NCSIFIFO_F, "MPS Tx NC-SI FIFO parity error", -1, 1 },
2934 { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 }, 2943 { TXDATAFIFO_V(TXDATAFIFO_M), "MPS Tx data FIFO parity error",
2935 { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 }, 2944 -1, 1 },
2936 { BUBBLE, "MPS Tx underflow", -1, 1 }, 2945 { TXDESCFIFO_V(TXDESCFIFO_M), "MPS Tx desc FIFO parity error",
2937 { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 }, 2946 -1, 1 },
2938 { FRMERR, "MPS Tx framing error", -1, 1 }, 2947 { BUBBLE_F, "MPS Tx underflow", -1, 1 },
2948 { SECNTERR_F, "MPS Tx SOP/EOP error", -1, 1 },
2949 { FRMERR_F, "MPS Tx framing error", -1, 1 },
2939 { 0, NULL, 0, 0 } 2950 { 0, NULL, 0, 0 }
2940 }; 2951 };
2941 static struct intr_info mps_trc_intr_info[] = { 2952 static struct intr_info mps_trc_intr_info[] = {
2942 { FILTMEM, "MPS TRC filter parity error", -1, 1 }, 2953 { FILTMEM_V(FILTMEM_M), "MPS TRC filter parity error", -1, 1 },
2943 { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 }, 2954 { PKTFIFO_V(PKTFIFO_M), "MPS TRC packet FIFO parity error",
2944 { MISCPERR, "MPS TRC misc parity error", -1, 1 }, 2955 -1, 1 },
2956 { MISCPERR_F, "MPS TRC misc parity error", -1, 1 },
2945 { 0, NULL, 0, 0 } 2957 { 0, NULL, 0, 0 }
2946 }; 2958 };
2947 static struct intr_info mps_stat_sram_intr_info[] = { 2959 static struct intr_info mps_stat_sram_intr_info[] = {
@@ -2957,36 +2969,37 @@ static void csio_mps_intr_handler(struct csio_hw *hw)
2957 { 0, NULL, 0, 0 } 2969 { 0, NULL, 0, 0 }
2958 }; 2970 };
2959 static struct intr_info mps_cls_intr_info[] = { 2971 static struct intr_info mps_cls_intr_info[] = {
2960 { MATCHSRAM, "MPS match SRAM parity error", -1, 1 }, 2972 { MATCHSRAM_F, "MPS match SRAM parity error", -1, 1 },
2961 { MATCHTCAM, "MPS match TCAM parity error", -1, 1 }, 2973 { MATCHTCAM_F, "MPS match TCAM parity error", -1, 1 },
2962 { HASHSRAM, "MPS hash SRAM parity error", -1, 1 }, 2974 { HASHSRAM_F, "MPS hash SRAM parity error", -1, 1 },
2963 { 0, NULL, 0, 0 } 2975 { 0, NULL, 0, 0 }
2964 }; 2976 };
2965 2977
2966 int fat; 2978 int fat;
2967 2979
2968 fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE, 2980 fat = csio_handle_intr_status(hw, MPS_RX_PERR_INT_CAUSE_A,
2969 mps_rx_intr_info) + 2981 mps_rx_intr_info) +
2970 csio_handle_intr_status(hw, MPS_TX_INT_CAUSE, 2982 csio_handle_intr_status(hw, MPS_TX_INT_CAUSE_A,
2971 mps_tx_intr_info) + 2983 mps_tx_intr_info) +
2972 csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE, 2984 csio_handle_intr_status(hw, MPS_TRC_INT_CAUSE_A,
2973 mps_trc_intr_info) + 2985 mps_trc_intr_info) +
2974 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM, 2986 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_SRAM_A,
2975 mps_stat_sram_intr_info) + 2987 mps_stat_sram_intr_info) +
2976 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO, 2988 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_TX_FIFO_A,
2977 mps_stat_tx_intr_info) + 2989 mps_stat_tx_intr_info) +
2978 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO, 2990 csio_handle_intr_status(hw, MPS_STAT_PERR_INT_CAUSE_RX_FIFO_A,
2979 mps_stat_rx_intr_info) + 2991 mps_stat_rx_intr_info) +
2980 csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE, 2992 csio_handle_intr_status(hw, MPS_CLS_INT_CAUSE_A,
2981 mps_cls_intr_info); 2993 mps_cls_intr_info);
2982 2994
2983 csio_wr_reg32(hw, 0, MPS_INT_CAUSE); 2995 csio_wr_reg32(hw, 0, MPS_INT_CAUSE_A);
2984 csio_rd_reg32(hw, MPS_INT_CAUSE); /* flush */ 2996 csio_rd_reg32(hw, MPS_INT_CAUSE_A); /* flush */
2985 if (fat) 2997 if (fat)
2986 csio_hw_fatal_err(hw); 2998 csio_hw_fatal_err(hw);
2987} 2999}
2988 3000
2989#define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE) 3001#define MEM_INT_MASK (PERR_INT_CAUSE_F | ECC_CE_INT_CAUSE_F | \
3002 ECC_UE_INT_CAUSE_F)
2990 3003
2991/* 3004/*
2992 * EDC/MC interrupt handler. 3005 * EDC/MC interrupt handler.
@@ -2998,28 +3011,28 @@ static void csio_mem_intr_handler(struct csio_hw *hw, int idx)
2998 unsigned int addr, cnt_addr, v; 3011 unsigned int addr, cnt_addr, v;
2999 3012
3000 if (idx <= MEM_EDC1) { 3013 if (idx <= MEM_EDC1) {
3001 addr = EDC_REG(EDC_INT_CAUSE, idx); 3014 addr = EDC_REG(EDC_INT_CAUSE_A, idx);
3002 cnt_addr = EDC_REG(EDC_ECC_STATUS, idx); 3015 cnt_addr = EDC_REG(EDC_ECC_STATUS_A, idx);
3003 } else { 3016 } else {
3004 addr = MC_INT_CAUSE; 3017 addr = MC_INT_CAUSE_A;
3005 cnt_addr = MC_ECC_STATUS; 3018 cnt_addr = MC_ECC_STATUS_A;
3006 } 3019 }
3007 3020
3008 v = csio_rd_reg32(hw, addr) & MEM_INT_MASK; 3021 v = csio_rd_reg32(hw, addr) & MEM_INT_MASK;
3009 if (v & PERR_INT_CAUSE) 3022 if (v & PERR_INT_CAUSE_F)
3010 csio_fatal(hw, "%s FIFO parity error\n", name[idx]); 3023 csio_fatal(hw, "%s FIFO parity error\n", name[idx]);
3011 if (v & ECC_CE_INT_CAUSE) { 3024 if (v & ECC_CE_INT_CAUSE_F) {
3012 uint32_t cnt = ECC_CECNT_GET(csio_rd_reg32(hw, cnt_addr)); 3025 uint32_t cnt = ECC_CECNT_G(csio_rd_reg32(hw, cnt_addr));
3013 3026
3014 csio_wr_reg32(hw, ECC_CECNT_MASK, cnt_addr); 3027 csio_wr_reg32(hw, ECC_CECNT_V(ECC_CECNT_M), cnt_addr);
3015 csio_warn(hw, "%u %s correctable ECC data error%s\n", 3028 csio_warn(hw, "%u %s correctable ECC data error%s\n",
3016 cnt, name[idx], cnt > 1 ? "s" : ""); 3029 cnt, name[idx], cnt > 1 ? "s" : "");
3017 } 3030 }
3018 if (v & ECC_UE_INT_CAUSE) 3031 if (v & ECC_UE_INT_CAUSE_F)
3019 csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]); 3032 csio_fatal(hw, "%s uncorrectable ECC data error\n", name[idx]);
3020 3033
3021 csio_wr_reg32(hw, v, addr); 3034 csio_wr_reg32(hw, v, addr);
3022 if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE)) 3035 if (v & (PERR_INT_CAUSE_F | ECC_UE_INT_CAUSE_F))
3023 csio_hw_fatal_err(hw); 3036 csio_hw_fatal_err(hw);
3024} 3037}
3025 3038
@@ -3028,18 +3041,18 @@ static void csio_mem_intr_handler(struct csio_hw *hw, int idx)
3028 */ 3041 */
3029static void csio_ma_intr_handler(struct csio_hw *hw) 3042static void csio_ma_intr_handler(struct csio_hw *hw)
3030{ 3043{
3031 uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE); 3044 uint32_t v, status = csio_rd_reg32(hw, MA_INT_CAUSE_A);
3032 3045
3033 if (status & MEM_PERR_INT_CAUSE) 3046 if (status & MEM_PERR_INT_CAUSE_F)
3034 csio_fatal(hw, "MA parity error, parity status %#x\n", 3047 csio_fatal(hw, "MA parity error, parity status %#x\n",
3035 csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS)); 3048 csio_rd_reg32(hw, MA_PARITY_ERROR_STATUS_A));
3036 if (status & MEM_WRAP_INT_CAUSE) { 3049 if (status & MEM_WRAP_INT_CAUSE_F) {
3037 v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS); 3050 v = csio_rd_reg32(hw, MA_INT_WRAP_STATUS_A);
3038 csio_fatal(hw, 3051 csio_fatal(hw,
3039 "MA address wrap-around error by client %u to address %#x\n", 3052 "MA address wrap-around error by client %u to address %#x\n",
3040 MEM_WRAP_CLIENT_NUM_GET(v), MEM_WRAP_ADDRESS_GET(v) << 4); 3053 MEM_WRAP_CLIENT_NUM_G(v), MEM_WRAP_ADDRESS_G(v) << 4);
3041 } 3054 }
3042 csio_wr_reg32(hw, status, MA_INT_CAUSE); 3055 csio_wr_reg32(hw, status, MA_INT_CAUSE_A);
3043 csio_hw_fatal_err(hw); 3056 csio_hw_fatal_err(hw);
3044} 3057}
3045 3058
@@ -3049,13 +3062,13 @@ static void csio_ma_intr_handler(struct csio_hw *hw)
3049static void csio_smb_intr_handler(struct csio_hw *hw) 3062static void csio_smb_intr_handler(struct csio_hw *hw)
3050{ 3063{
3051 static struct intr_info smb_intr_info[] = { 3064 static struct intr_info smb_intr_info[] = {
3052 { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 }, 3065 { MSTTXFIFOPARINT_F, "SMB master Tx FIFO parity error", -1, 1 },
3053 { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 }, 3066 { MSTRXFIFOPARINT_F, "SMB master Rx FIFO parity error", -1, 1 },
3054 { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 }, 3067 { SLVFIFOPARINT_F, "SMB slave FIFO parity error", -1, 1 },
3055 { 0, NULL, 0, 0 } 3068 { 0, NULL, 0, 0 }
3056 }; 3069 };
3057 3070
3058 if (csio_handle_intr_status(hw, SMB_INT_CAUSE, smb_intr_info)) 3071 if (csio_handle_intr_status(hw, SMB_INT_CAUSE_A, smb_intr_info))
3059 csio_hw_fatal_err(hw); 3072 csio_hw_fatal_err(hw);
3060} 3073}
3061 3074
@@ -3065,14 +3078,14 @@ static void csio_smb_intr_handler(struct csio_hw *hw)
3065static void csio_ncsi_intr_handler(struct csio_hw *hw) 3078static void csio_ncsi_intr_handler(struct csio_hw *hw)
3066{ 3079{
3067 static struct intr_info ncsi_intr_info[] = { 3080 static struct intr_info ncsi_intr_info[] = {
3068 { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 }, 3081 { CIM_DM_PRTY_ERR_F, "NC-SI CIM parity error", -1, 1 },
3069 { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 }, 3082 { MPS_DM_PRTY_ERR_F, "NC-SI MPS parity error", -1, 1 },
3070 { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 }, 3083 { TXFIFO_PRTY_ERR_F, "NC-SI Tx FIFO parity error", -1, 1 },
3071 { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 }, 3084 { RXFIFO_PRTY_ERR_F, "NC-SI Rx FIFO parity error", -1, 1 },
3072 { 0, NULL, 0, 0 } 3085 { 0, NULL, 0, 0 }
3073 }; 3086 };
3074 3087
3075 if (csio_handle_intr_status(hw, NCSI_INT_CAUSE, ncsi_intr_info)) 3088 if (csio_handle_intr_status(hw, NCSI_INT_CAUSE_A, ncsi_intr_info))
3076 csio_hw_fatal_err(hw); 3089 csio_hw_fatal_err(hw);
3077} 3090}
3078 3091
@@ -3081,17 +3094,17 @@ static void csio_ncsi_intr_handler(struct csio_hw *hw)
3081 */ 3094 */
3082static void csio_xgmac_intr_handler(struct csio_hw *hw, int port) 3095static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
3083{ 3096{
3084 uint32_t v = csio_rd_reg32(hw, CSIO_MAC_INT_CAUSE_REG(hw, port)); 3097 uint32_t v = csio_rd_reg32(hw, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
3085 3098
3086 v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR; 3099 v &= TXFIFO_PRTY_ERR_F | RXFIFO_PRTY_ERR_F;
3087 if (!v) 3100 if (!v)
3088 return; 3101 return;
3089 3102
3090 if (v & TXFIFO_PRTY_ERR) 3103 if (v & TXFIFO_PRTY_ERR_F)
3091 csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port); 3104 csio_fatal(hw, "XGMAC %d Tx FIFO parity error\n", port);
3092 if (v & RXFIFO_PRTY_ERR) 3105 if (v & RXFIFO_PRTY_ERR_F)
3093 csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port); 3106 csio_fatal(hw, "XGMAC %d Rx FIFO parity error\n", port);
3094 csio_wr_reg32(hw, v, CSIO_MAC_INT_CAUSE_REG(hw, port)); 3107 csio_wr_reg32(hw, v, T5_PORT_REG(port, MAC_PORT_INT_CAUSE_A));
3095 csio_hw_fatal_err(hw); 3108 csio_hw_fatal_err(hw);
3096} 3109}
3097 3110
@@ -3101,12 +3114,12 @@ static void csio_xgmac_intr_handler(struct csio_hw *hw, int port)
3101static void csio_pl_intr_handler(struct csio_hw *hw) 3114static void csio_pl_intr_handler(struct csio_hw *hw)
3102{ 3115{
3103 static struct intr_info pl_intr_info[] = { 3116 static struct intr_info pl_intr_info[] = {
3104 { FATALPERR, "T4 fatal parity error", -1, 1 }, 3117 { FATALPERR_F, "T4 fatal parity error", -1, 1 },
3105 { PERRVFID, "PL VFID_MAP parity error", -1, 1 }, 3118 { PERRVFID_F, "PL VFID_MAP parity error", -1, 1 },
3106 { 0, NULL, 0, 0 } 3119 { 0, NULL, 0, 0 }
3107 }; 3120 };
3108 3121
3109 if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE, pl_intr_info)) 3122 if (csio_handle_intr_status(hw, PL_PL_INT_CAUSE_A, pl_intr_info))
3110 csio_hw_fatal_err(hw); 3123 csio_hw_fatal_err(hw);
3111} 3124}
3112 3125
@@ -3121,7 +3134,7 @@ static void csio_pl_intr_handler(struct csio_hw *hw)
3121int 3134int
3122csio_hw_slow_intr_handler(struct csio_hw *hw) 3135csio_hw_slow_intr_handler(struct csio_hw *hw)
3123{ 3136{
3124 uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE); 3137 uint32_t cause = csio_rd_reg32(hw, PL_INT_CAUSE_A);
3125 3138
3126 if (!(cause & CSIO_GLBL_INTR_MASK)) { 3139 if (!(cause & CSIO_GLBL_INTR_MASK)) {
3127 CSIO_INC_STATS(hw, n_plint_unexp); 3140 CSIO_INC_STATS(hw, n_plint_unexp);
@@ -3132,75 +3145,75 @@ csio_hw_slow_intr_handler(struct csio_hw *hw)
3132 3145
3133 CSIO_INC_STATS(hw, n_plint_cnt); 3146 CSIO_INC_STATS(hw, n_plint_cnt);
3134 3147
3135 if (cause & CIM) 3148 if (cause & CIM_F)
3136 csio_cim_intr_handler(hw); 3149 csio_cim_intr_handler(hw);
3137 3150
3138 if (cause & MPS) 3151 if (cause & MPS_F)
3139 csio_mps_intr_handler(hw); 3152 csio_mps_intr_handler(hw);
3140 3153
3141 if (cause & NCSI) 3154 if (cause & NCSI_F)
3142 csio_ncsi_intr_handler(hw); 3155 csio_ncsi_intr_handler(hw);
3143 3156
3144 if (cause & PL) 3157 if (cause & PL_F)
3145 csio_pl_intr_handler(hw); 3158 csio_pl_intr_handler(hw);
3146 3159
3147 if (cause & SMB) 3160 if (cause & SMB_F)
3148 csio_smb_intr_handler(hw); 3161 csio_smb_intr_handler(hw);
3149 3162
3150 if (cause & XGMAC0) 3163 if (cause & XGMAC0_F)
3151 csio_xgmac_intr_handler(hw, 0); 3164 csio_xgmac_intr_handler(hw, 0);
3152 3165
3153 if (cause & XGMAC1) 3166 if (cause & XGMAC1_F)
3154 csio_xgmac_intr_handler(hw, 1); 3167 csio_xgmac_intr_handler(hw, 1);
3155 3168
3156 if (cause & XGMAC_KR0) 3169 if (cause & XGMAC_KR0_F)
3157 csio_xgmac_intr_handler(hw, 2); 3170 csio_xgmac_intr_handler(hw, 2);
3158 3171
3159 if (cause & XGMAC_KR1) 3172 if (cause & XGMAC_KR1_F)
3160 csio_xgmac_intr_handler(hw, 3); 3173 csio_xgmac_intr_handler(hw, 3);
3161 3174
3162 if (cause & PCIE) 3175 if (cause & PCIE_F)
3163 hw->chip_ops->chip_pcie_intr_handler(hw); 3176 hw->chip_ops->chip_pcie_intr_handler(hw);
3164 3177
3165 if (cause & MC) 3178 if (cause & MC_F)
3166 csio_mem_intr_handler(hw, MEM_MC); 3179 csio_mem_intr_handler(hw, MEM_MC);
3167 3180
3168 if (cause & EDC0) 3181 if (cause & EDC0_F)
3169 csio_mem_intr_handler(hw, MEM_EDC0); 3182 csio_mem_intr_handler(hw, MEM_EDC0);
3170 3183
3171 if (cause & EDC1) 3184 if (cause & EDC1_F)
3172 csio_mem_intr_handler(hw, MEM_EDC1); 3185 csio_mem_intr_handler(hw, MEM_EDC1);
3173 3186
3174 if (cause & LE) 3187 if (cause & LE_F)
3175 csio_le_intr_handler(hw); 3188 csio_le_intr_handler(hw);
3176 3189
3177 if (cause & TP) 3190 if (cause & TP_F)
3178 csio_tp_intr_handler(hw); 3191 csio_tp_intr_handler(hw);
3179 3192
3180 if (cause & MA) 3193 if (cause & MA_F)
3181 csio_ma_intr_handler(hw); 3194 csio_ma_intr_handler(hw);
3182 3195
3183 if (cause & PM_TX) 3196 if (cause & PM_TX_F)
3184 csio_pmtx_intr_handler(hw); 3197 csio_pmtx_intr_handler(hw);
3185 3198
3186 if (cause & PM_RX) 3199 if (cause & PM_RX_F)
3187 csio_pmrx_intr_handler(hw); 3200 csio_pmrx_intr_handler(hw);
3188 3201
3189 if (cause & ULP_RX) 3202 if (cause & ULP_RX_F)
3190 csio_ulprx_intr_handler(hw); 3203 csio_ulprx_intr_handler(hw);
3191 3204
3192 if (cause & CPL_SWITCH) 3205 if (cause & CPL_SWITCH_F)
3193 csio_cplsw_intr_handler(hw); 3206 csio_cplsw_intr_handler(hw);
3194 3207
3195 if (cause & SGE) 3208 if (cause & SGE_F)
3196 csio_sge_intr_handler(hw); 3209 csio_sge_intr_handler(hw);
3197 3210
3198 if (cause & ULP_TX) 3211 if (cause & ULP_TX_F)
3199 csio_ulptx_intr_handler(hw); 3212 csio_ulptx_intr_handler(hw);
3200 3213
3201 /* Clear the interrupts just processed for which we are the master. */ 3214 /* Clear the interrupts just processed for which we are the master. */
3202 csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE); 3215 csio_wr_reg32(hw, cause & CSIO_GLBL_INTR_MASK, PL_INT_CAUSE_A);
3203 csio_rd_reg32(hw, PL_INT_CAUSE); /* flush */ 3216 csio_rd_reg32(hw, PL_INT_CAUSE_A); /* flush */
3204 3217
3205 return 1; 3218 return 1;
3206} 3219}
@@ -3840,13 +3853,7 @@ csio_hw_set_description(struct csio_hw *hw, uint16_t ven_id, uint16_t dev_id)
3840 prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK); 3853 prot_type = (dev_id & CSIO_ASIC_DEVID_PROTO_MASK);
3841 adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK); 3854 adap_type = (dev_id & CSIO_ASIC_DEVID_TYPE_MASK);
3842 3855
3843 if (prot_type == CSIO_T4_FCOE_ASIC) { 3856 if (prot_type == CSIO_T5_FCOE_ASIC) {
3844 memcpy(hw->hw_ver,
3845 csio_t4_fcoe_adapters[adap_type].model_no, 16);
3846 memcpy(hw->model_desc,
3847 csio_t4_fcoe_adapters[adap_type].description,
3848 32);
3849 } else if (prot_type == CSIO_T5_FCOE_ASIC) {
3850 memcpy(hw->hw_ver, 3857 memcpy(hw->hw_ver,
3851 csio_t5_fcoe_adapters[adap_type].model_no, 16); 3858 csio_t5_fcoe_adapters[adap_type].model_no, 16);
3852 memcpy(hw->model_desc, 3859 memcpy(hw->model_desc,
@@ -3883,8 +3890,8 @@ csio_hw_init(struct csio_hw *hw)
3883 3890
3884 strcpy(hw->name, CSIO_HW_NAME); 3891 strcpy(hw->name, CSIO_HW_NAME);
3885 3892
3886 /* Initialize the HW chip ops with T4/T5 specific ops */ 3893 /* Initialize the HW chip ops T5 specific ops */
3887 hw->chip_ops = csio_is_t4(hw->chip_id) ? &t4_ops : &t5_ops; 3894 hw->chip_ops = &t5_ops;
3888 3895
3889 /* Set the model & its description */ 3896 /* Set the model & its description */
3890 3897
diff --git a/drivers/scsi/csiostor/csio_hw.h b/drivers/scsi/csiostor/csio_hw.h
index 68248da1b9af..029bef82c057 100644
--- a/drivers/scsi/csiostor/csio_hw.h
+++ b/drivers/scsi/csiostor/csio_hw.h
@@ -48,6 +48,7 @@
48#include <scsi/scsi_device.h> 48#include <scsi/scsi_device.h>
49#include <scsi/scsi_transport_fc.h> 49#include <scsi/scsi_transport_fc.h>
50 50
51#include "t4_hw.h"
51#include "csio_hw_chip.h" 52#include "csio_hw_chip.h"
52#include "csio_wr.h" 53#include "csio_wr.h"
53#include "csio_mb.h" 54#include "csio_mb.h"
@@ -117,10 +118,10 @@ extern int csio_msi;
117#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00 118#define CSIO_ASIC_DEVID_PROTO_MASK 0xFF00
118#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF 119#define CSIO_ASIC_DEVID_TYPE_MASK 0x00FF
119 120
120#define CSIO_GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \ 121#define CSIO_GLBL_INTR_MASK (CIM_F | MPS_F | PL_F | PCIE_F | MC_F | \
121 EDC1 | LE | TP | MA | PM_TX | PM_RX | \ 122 EDC0_F | EDC1_F | LE_F | TP_F | MA_F | \
122 ULP_RX | CPL_SWITCH | SGE | \ 123 PM_TX_F | PM_RX_F | ULP_RX_F | \
123 ULP_TX | SF) 124 CPL_SWITCH_F | SGE_F | ULP_TX_F | SF_F)
124 125
125/* 126/*
126 * Hard parameters used to initialize the card in the absence of a 127 * Hard parameters used to initialize the card in the absence of a
@@ -174,16 +175,12 @@ struct csio_evt_msg {
174}; 175};
175 176
176enum { 177enum {
177 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
178 SERNUM_LEN = 16, /* Serial # length */ 178 SERNUM_LEN = 16, /* Serial # length */
179 EC_LEN = 16, /* E/C length */ 179 EC_LEN = 16, /* E/C length */
180 ID_LEN = 16, /* ID length */ 180 ID_LEN = 16, /* ID length */
181 TRACE_LEN = 112, /* length of trace data and mask */
182}; 181};
183 182
184enum { 183enum {
185 SF_PAGE_SIZE = 256, /* serial flash page size */
186 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
187 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */ 184 SF_SIZE = SF_SEC_SIZE * 16, /* serial flash size */
188}; 185};
189 186
@@ -199,39 +196,8 @@ enum {
199 SF_RD_DATA_FAST = 0xb, /* read flash */ 196 SF_RD_DATA_FAST = 0xb, /* read flash */
200 SF_RD_ID = 0x9f, /* read ID */ 197 SF_RD_ID = 0x9f, /* read ID */
201 SF_ERASE_SECTOR = 0xd8, /* erase sector */ 198 SF_ERASE_SECTOR = 0xd8, /* erase sector */
202
203 FW_START_SEC = 8, /* first flash sector for FW */
204 FW_END_SEC = 15, /* last flash sector for FW */
205 FW_IMG_START = FW_START_SEC * SF_SEC_SIZE,
206 FW_MAX_SIZE = (FW_END_SEC - FW_START_SEC + 1) * SF_SEC_SIZE,
207
208 FLASH_CFG_MAX_SIZE = 0x10000 , /* max size of the flash config file*/
209 FLASH_CFG_OFFSET = 0x1f0000,
210 FLASH_CFG_START_SEC = FLASH_CFG_OFFSET / SF_SEC_SIZE,
211}; 199};
212 200
213/*
214 * Flash layout.
215 */
216#define FLASH_START(start) ((start) * SF_SEC_SIZE)
217#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
218
219enum {
220 /*
221 * Location of firmware image in FLASH.
222 */
223 FLASH_FW_START_SEC = 8,
224 FLASH_FW_NSECS = 8,
225 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
226 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
227
228 /* Location of Firmware Configuration File in FLASH. */
229 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
230};
231
232#undef FLASH_START
233#undef FLASH_MAX_SIZE
234
235/* Management module */ 201/* Management module */
236enum { 202enum {
237 CSIO_MGMT_EQ_WRSIZE = 512, 203 CSIO_MGMT_EQ_WRSIZE = 512,
@@ -482,11 +448,6 @@ struct csio_hw {
482 uint32_t tp_vers; 448 uint32_t tp_vers;
483 char chip_ver; 449 char chip_ver;
484 uint16_t chip_id; /* Tells T4/T5 chip */ 450 uint16_t chip_id; /* Tells T4/T5 chip */
485 uint32_t cfg_finiver;
486 uint32_t cfg_finicsum;
487 uint32_t cfg_cfcsum;
488 uint8_t cfg_csum_status;
489 uint8_t cfg_store;
490 enum csio_dev_state fw_state; 451 enum csio_dev_state fw_state;
491 struct csio_vpd vpd; 452 struct csio_vpd vpd;
492 453
diff --git a/drivers/scsi/csiostor/csio_hw_chip.h b/drivers/scsi/csiostor/csio_hw_chip.h
index 4752fed476df..b56a11d817be 100644
--- a/drivers/scsi/csiostor/csio_hw_chip.h
+++ b/drivers/scsi/csiostor/csio_hw_chip.h
@@ -37,24 +37,27 @@
37#include "csio_defs.h" 37#include "csio_defs.h"
38 38
39/* Define MACRO values */ 39/* Define MACRO values */
40#define CSIO_HW_T4 0x4000
41#define CSIO_T4_FCOE_ASIC 0x4600
42#define CSIO_HW_T5 0x5000 40#define CSIO_HW_T5 0x5000
43#define CSIO_T5_FCOE_ASIC 0x5600 41#define CSIO_T5_FCOE_ASIC 0x5600
44#define CSIO_HW_CHIP_MASK 0xF000 42#define CSIO_HW_CHIP_MASK 0xF000
45 43
46#define T4_REGMAP_SIZE (160 * 1024)
47#define T5_REGMAP_SIZE (332 * 1024) 44#define T5_REGMAP_SIZE (332 * 1024)
48#define FW_FNAME_T4 "cxgb4/t4fw.bin"
49#define FW_FNAME_T5 "cxgb4/t5fw.bin" 45#define FW_FNAME_T5 "cxgb4/t5fw.bin"
50#define FW_CFG_NAME_T4 "cxgb4/t4-config.txt"
51#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt" 46#define FW_CFG_NAME_T5 "cxgb4/t5-config.txt"
52 47
53/* Define static functions */ 48#define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
54static inline int csio_is_t4(uint16_t chip) 49#define CHELSIO_CHIP_FPGA 0x100
55{ 50#define CHELSIO_CHIP_VERSION(code) (((code) >> 12) & 0xf)
56 return (chip == CSIO_HW_T4); 51#define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
57} 52
53#define CHELSIO_T5 0x5
54
55enum chip_type {
56 T5_A0 = CHELSIO_CHIP_CODE(CHELSIO_T5, 0),
57 T5_A1 = CHELSIO_CHIP_CODE(CHELSIO_T5, 1),
58 T5_FIRST_REV = T5_A0,
59 T5_LAST_REV = T5_A1,
60};
58 61
59static inline int csio_is_t5(uint16_t chip) 62static inline int csio_is_t5(uint16_t chip)
60{ 63{
@@ -65,30 +68,22 @@ static inline int csio_is_t5(uint16_t chip)
65#define CSIO_DEVICE(devid, idx) \ 68#define CSIO_DEVICE(devid, idx) \
66 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) } 69 { PCI_VENDOR_ID_CHELSIO, (devid), PCI_ANY_ID, PCI_ANY_ID, 0, 0, (idx) }
67 70
68#define CSIO_HW_PIDX(hw, index) \ 71#include "t4fw_api.h"
69 (csio_is_t4(hw->chip_id) ? (PIDX(index)) : \ 72#include "t4fw_version.h"
70 (PIDX_T5(index) | DBTYPE(1U))) 73
71 74#define FW_VERSION(chip) ( \
72#define CSIO_HW_LP_INT_THRESH(hw, val) \ 75 FW_HDR_FW_VER_MAJOR_G(chip##FW_VERSION_MAJOR) | \
73 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH(val)) : \ 76 FW_HDR_FW_VER_MINOR_G(chip##FW_VERSION_MINOR) | \
74 (V_LP_INT_THRESH_T5(val))) 77 FW_HDR_FW_VER_MICRO_G(chip##FW_VERSION_MICRO) | \
75 78 FW_HDR_FW_VER_BUILD_G(chip##FW_VERSION_BUILD))
76#define CSIO_HW_M_LP_INT_THRESH(hw) \ 79#define FW_INTFVER(chip, intf) (FW_HDR_INTFVER_##intf)
77 (csio_is_t4(hw->chip_id) ? (LP_INT_THRESH_MASK) : (M_LP_INT_THRESH_T5)) 80
78 81struct fw_info {
79#define CSIO_MAC_INT_CAUSE_REG(hw, port) \ 82 u8 chip;
80 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \ 83 char *fs_name;
81 (T5_PORT_REG(port, MAC_PORT_INT_CAUSE))) 84 char *fw_mod_name;
82 85 struct fw_hdr fw_hdr;
83#define FW_VERSION_MAJOR(hw) (csio_is_t4(hw->chip_id) ? 1 : 0) 86};
84#define FW_VERSION_MINOR(hw) (csio_is_t4(hw->chip_id) ? 2 : 0)
85#define FW_VERSION_MICRO(hw) (csio_is_t4(hw->chip_id) ? 8 : 0)
86
87#define CSIO_FW_FNAME(hw) \
88 (csio_is_t4(hw->chip_id) ? FW_FNAME_T4 : FW_FNAME_T5)
89
90#define CSIO_CF_FNAME(hw) \
91 (csio_is_t4(hw->chip_id) ? FW_CFG_NAME_T4 : FW_CFG_NAME_T5)
92 87
93/* Declare ENUMS */ 88/* Declare ENUMS */
94enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 }; 89enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
@@ -96,7 +91,6 @@ enum { MEM_EDC0, MEM_EDC1, MEM_MC, MEM_MC0 = MEM_MC, MEM_MC1 };
96enum { 91enum {
97 MEMWIN_APERTURE = 2048, 92 MEMWIN_APERTURE = 2048,
98 MEMWIN_BASE = 0x1b800, 93 MEMWIN_BASE = 0x1b800,
99 MEMWIN_CSIOSTOR = 6, /* PCI-e Memory Window access */
100}; 94};
101 95
102/* Slow path handlers */ 96/* Slow path handlers */
@@ -122,7 +116,6 @@ struct csio_hw_chip_ops {
122 void (*chip_dfs_create_ext_mem)(struct csio_hw *); 116 void (*chip_dfs_create_ext_mem)(struct csio_hw *);
123}; 117};
124 118
125extern struct csio_hw_chip_ops t4_ops;
126extern struct csio_hw_chip_ops t5_ops; 119extern struct csio_hw_chip_ops t5_ops;
127 120
128#endif /* #ifndef __CSIO_HW_CHIP_H__ */ 121#endif /* #ifndef __CSIO_HW_CHIP_H__ */
diff --git a/drivers/scsi/csiostor/csio_hw_t4.c b/drivers/scsi/csiostor/csio_hw_t4.c
deleted file mode 100644
index 95d831857640..000000000000
--- a/drivers/scsi/csiostor/csio_hw_t4.c
+++ /dev/null
@@ -1,404 +0,0 @@
1/*
2 * This file is part of the Chelsio FCoE driver for Linux.
3 *
4 * Copyright (c) 2008-2013 Chelsio Communications, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 */
31
32#include "csio_hw.h"
33#include "csio_init.h"
34
35/*
36 * Return the specified PCI-E Configuration Space register from our Physical
37 * Function. We try first via a Firmware LDST Command since we prefer to let
38 * the firmware own all of these registers, but if that fails we go for it
39 * directly ourselves.
40 */
41static uint32_t
42csio_t4_read_pcie_cfg4(struct csio_hw *hw, int reg)
43{
44 u32 val = 0;
45 struct csio_mb *mbp;
46 int rv;
47 struct fw_ldst_cmd *ldst_cmd;
48
49 mbp = mempool_alloc(hw->mb_mempool, GFP_ATOMIC);
50 if (!mbp) {
51 CSIO_INC_STATS(hw, n_err_nomem);
52 pci_read_config_dword(hw->pdev, reg, &val);
53 return val;
54 }
55
56 csio_mb_ldst(hw, mbp, CSIO_MB_DEFAULT_TMO, reg);
57 rv = csio_mb_issue(hw, mbp);
58
59 /*
60 * If the LDST Command suucceeded, exctract the returned register
61 * value. Otherwise read it directly ourself.
62 */
63 if (rv == 0) {
64 ldst_cmd = (struct fw_ldst_cmd *)(mbp->mb);
65 val = ntohl(ldst_cmd->u.pcie.data[0]);
66 } else
67 pci_read_config_dword(hw->pdev, reg, &val);
68
69 mempool_free(mbp, hw->mb_mempool);
70
71 return val;
72}
73
74static int
75csio_t4_set_mem_win(struct csio_hw *hw, uint32_t win)
76{
77 u32 bar0;
78 u32 mem_win_base;
79
80 /*
81 * Truncation intentional: we only read the bottom 32-bits of the
82 * 64-bit BAR0/BAR1 ... We use the hardware backdoor mechanism to
83 * read BAR0 instead of using pci_resource_start() because we could be
84 * operating from within a Virtual Machine which is trapping our
85 * accesses to our Configuration Space and we need to set up the PCI-E
86 * Memory Window decoders with the actual addresses which will be
87 * coming across the PCI-E link.
88 */
89 bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0);
90 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
91
92 mem_win_base = bar0 + MEMWIN_BASE;
93
94 /*
95 * Set up memory window for accessing adapter memory ranges. (Read
96 * back MA register to ensure that changes propagate before we attempt
97 * to use the new values.)
98 */
99 csio_wr_reg32(hw, mem_win_base | BIR(0) |
100 WINDOW(ilog2(MEMWIN_APERTURE) - 10),
101 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
102 csio_rd_reg32(hw,
103 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
104 return 0;
105}
106
107/*
108 * Interrupt handler for the PCIE module.
109 */
110static void
111csio_t4_pcie_intr_handler(struct csio_hw *hw)
112{
113 static struct intr_info sysbus_intr_info[] = {
114 { RNPP, "RXNP array parity error", -1, 1 },
115 { RPCP, "RXPC array parity error", -1, 1 },
116 { RCIP, "RXCIF array parity error", -1, 1 },
117 { RCCP, "Rx completions control array parity error", -1, 1 },
118 { RFTP, "RXFT array parity error", -1, 1 },
119 { 0, NULL, 0, 0 }
120 };
121 static struct intr_info pcie_port_intr_info[] = {
122 { TPCP, "TXPC array parity error", -1, 1 },
123 { TNPP, "TXNP array parity error", -1, 1 },
124 { TFTP, "TXFT array parity error", -1, 1 },
125 { TCAP, "TXCA array parity error", -1, 1 },
126 { TCIP, "TXCIF array parity error", -1, 1 },
127 { RCAP, "RXCA array parity error", -1, 1 },
128 { OTDD, "outbound request TLP discarded", -1, 1 },
129 { RDPE, "Rx data parity error", -1, 1 },
130 { TDUE, "Tx uncorrectable data error", -1, 1 },
131 { 0, NULL, 0, 0 }
132 };
133
134 static struct intr_info pcie_intr_info[] = {
135 { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
136 { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
137 { MSIDATAPERR, "MSI data parity error", -1, 1 },
138 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
139 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
140 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
141 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
142 { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
143 { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
144 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
145 { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
146 { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
147 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
148 { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
149 { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
150 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
151 { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
152 { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
153 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
154 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
155 { FIDPERR, "PCI FID parity error", -1, 1 },
156 { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
157 { MATAGPERR, "PCI MA tag parity error", -1, 1 },
158 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
159 { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
160 { RXWRPERR, "PCI Rx write parity error", -1, 1 },
161 { RPLPERR, "PCI replay buffer parity error", -1, 1 },
162 { PCIESINT, "PCI core secondary fault", -1, 1 },
163 { PCIEPINT, "PCI core primary fault", -1, 1 },
164 { UNXSPLCPLERR, "PCI unexpected split completion error", -1,
165 0 },
166 { 0, NULL, 0, 0 }
167 };
168
169 int fat;
170 fat = csio_handle_intr_status(hw,
171 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
172 sysbus_intr_info) +
173 csio_handle_intr_status(hw,
174 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
175 pcie_port_intr_info) +
176 csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info);
177 if (fat)
178 csio_hw_fatal_err(hw);
179}
180
181/*
182 * csio_t4_flash_cfg_addr - return the address of the flash configuration file
183 * @hw: the HW module
184 *
185 * Return the address within the flash where the Firmware Configuration
186 * File is stored.
187 */
188static unsigned int
189csio_t4_flash_cfg_addr(struct csio_hw *hw)
190{
191 return FLASH_CFG_OFFSET;
192}
193
194/*
195 * csio_t4_mc_read - read from MC through backdoor accesses
196 * @hw: the hw module
197 * @idx: not used for T4 adapter
198 * @addr: address of first byte requested
199 * @data: 64 bytes of data containing the requested address
200 * @ecc: where to store the corresponding 64-bit ECC word
201 *
202 * Read 64 bytes of data from MC starting at a 64-byte-aligned address
203 * that covers the requested address @addr. If @parity is not %NULL it
204 * is assigned the 64-bit ECC word for the read data.
205 */
206static int
207csio_t4_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
208 uint64_t *ecc)
209{
210 int i;
211
212 if (csio_rd_reg32(hw, MC_BIST_CMD) & START_BIST)
213 return -EBUSY;
214 csio_wr_reg32(hw, addr & ~0x3fU, MC_BIST_CMD_ADDR);
215 csio_wr_reg32(hw, 64, MC_BIST_CMD_LEN);
216 csio_wr_reg32(hw, 0xc, MC_BIST_DATA_PATTERN);
217 csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1),
218 MC_BIST_CMD);
219 i = csio_hw_wait_op_done_val(hw, MC_BIST_CMD, START_BIST,
220 0, 10, 1, NULL);
221 if (i)
222 return i;
223
224#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
225
226 for (i = 15; i >= 0; i--)
227 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
228 if (ecc)
229 *ecc = csio_rd_reg64(hw, MC_DATA(16));
230#undef MC_DATA
231 return 0;
232}
233
234/*
235 * csio_t4_edc_read - read from EDC through backdoor accesses
236 * @hw: the hw module
237 * @idx: which EDC to access
238 * @addr: address of first byte requested
239 * @data: 64 bytes of data containing the requested address
240 * @ecc: where to store the corresponding 64-bit ECC word
241 *
242 * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
243 * that covers the requested address @addr. If @parity is not %NULL it
244 * is assigned the 64-bit ECC word for the read data.
245 */
246static int
247csio_t4_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
248 uint64_t *ecc)
249{
250 int i;
251
252 idx *= EDC_STRIDE;
253 if (csio_rd_reg32(hw, EDC_BIST_CMD + idx) & START_BIST)
254 return -EBUSY;
255 csio_wr_reg32(hw, addr & ~0x3fU, EDC_BIST_CMD_ADDR + idx);
256 csio_wr_reg32(hw, 64, EDC_BIST_CMD_LEN + idx);
257 csio_wr_reg32(hw, 0xc, EDC_BIST_DATA_PATTERN + idx);
258 csio_wr_reg32(hw, BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST,
259 EDC_BIST_CMD + idx);
260 i = csio_hw_wait_op_done_val(hw, EDC_BIST_CMD + idx, START_BIST,
261 0, 10, 1, NULL);
262 if (i)
263 return i;
264
265#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
266
267 for (i = 15; i >= 0; i--)
268 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
269 if (ecc)
270 *ecc = csio_rd_reg64(hw, EDC_DATA(16));
271#undef EDC_DATA
272 return 0;
273}
274
275/*
276 * csio_t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
277 * @hw: the csio_hw
278 * @win: PCI-E memory Window to use
279 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_MC0 (or MEM_MC) or MEM_MC1
280 * @addr: address within indicated memory type
281 * @len: amount of memory to transfer
282 * @buf: host memory buffer
283 * @dir: direction of transfer 1 => read, 0 => write
284 *
285 * Reads/writes an [almost] arbitrary memory region in the firmware: the
286 * firmware memory address, length and host buffer must be aligned on
287 * 32-bit boudaries. The memory is transferred as a raw byte sequence
288 * from/to the firmware's memory. If this memory contains data
289 * structures which contain multi-byte integers, it's the callers
290 * responsibility to perform appropriate byte order conversions.
291 */
292static int
293csio_t4_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
294 u32 len, uint32_t *buf, int dir)
295{
296 u32 pos, start, offset, memoffset, bar0;
297 u32 edc_size, mc_size, mem_reg, mem_aperture, mem_base;
298
299 /*
300 * Argument sanity checks ...
301 */
302 if ((addr & 0x3) || (len & 0x3))
303 return -EINVAL;
304
305 /* Offset into the region of memory which is being accessed
306 * MEM_EDC0 = 0
307 * MEM_EDC1 = 1
308 * MEM_MC = 2 -- T4
309 */
310 edc_size = EDRAM0_SIZE_G(csio_rd_reg32(hw, MA_EDRAM0_BAR_A));
311 if (mtype != MEM_MC1)
312 memoffset = (mtype * (edc_size * 1024 * 1024));
313 else {
314 mc_size = EXT_MEM_SIZE_G(csio_rd_reg32(hw,
315 MA_EXT_MEMORY_BAR_A));
316 memoffset = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
317 }
318
319 /* Determine the PCIE_MEM_ACCESS_OFFSET */
320 addr = addr + memoffset;
321
322 /*
323 * Each PCI-E Memory Window is programmed with a window size -- or
324 * "aperture" -- which controls the granularity of its mapping onto
325 * adapter memory. We need to grab that aperture in order to know
326 * how to use the specified window. The window is also programmed
327 * with the base address of the Memory Window in BAR0's address
328 * space. For T4 this is an absolute PCI-E Bus Address. For T5
329 * the address is relative to BAR0.
330 */
331 mem_reg = csio_rd_reg32(hw,
332 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win));
333 mem_aperture = 1 << (WINDOW(mem_reg) + 10);
334 mem_base = GET_PCIEOFST(mem_reg) << 10;
335
336 bar0 = csio_t4_read_pcie_cfg4(hw, PCI_BASE_ADDRESS_0);
337 bar0 &= PCI_BASE_ADDRESS_MEM_MASK;
338 mem_base -= bar0;
339
340 start = addr & ~(mem_aperture-1);
341 offset = addr - start;
342
343 csio_dbg(hw, "csio_t4_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
344 mem_reg, mem_aperture);
345 csio_dbg(hw, "csio_t4_memory_rw: mem_base: 0x%x, mem_offset: 0x%x\n",
346 mem_base, memoffset);
347 csio_dbg(hw, "csio_t4_memory_rw: bar0: 0x%x, start:0x%x, offset:0x%x\n",
348 bar0, start, offset);
349 csio_dbg(hw, "csio_t4_memory_rw: mtype: %d, addr: 0x%x, len: %d\n",
350 mtype, addr, len);
351
352 for (pos = start; len > 0; pos += mem_aperture, offset = 0) {
353 /*
354 * Move PCI-E Memory Window to our current transfer
355 * position. Read it back to ensure that changes propagate
356 * before we attempt to use the new value.
357 */
358 csio_wr_reg32(hw, pos,
359 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
360 csio_rd_reg32(hw,
361 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win));
362
363 while (offset < mem_aperture && len > 0) {
364 if (dir)
365 *buf++ = csio_rd_reg32(hw, mem_base + offset);
366 else
367 csio_wr_reg32(hw, *buf++, mem_base + offset);
368
369 offset += sizeof(__be32);
370 len -= sizeof(__be32);
371 }
372 }
373 return 0;
374}
375
376/*
377 * csio_t4_dfs_create_ext_mem - setup debugfs for MC to read the values
378 * @hw: the csio_hw
379 *
380 * This function creates files in the debugfs with external memory region MC.
381 */
382static void
383csio_t4_dfs_create_ext_mem(struct csio_hw *hw)
384{
385 u32 size;
386 int i = csio_rd_reg32(hw, MA_TARGET_MEM_ENABLE_A);
387
388 if (i & EXT_MEM_ENABLE_F) {
389 size = csio_rd_reg32(hw, MA_EXT_MEMORY_BAR_A);
390 csio_add_debugfs_mem(hw, "mc", MEM_MC,
391 EXT_MEM_SIZE_G(size));
392 }
393}
394
395/* T4 adapter specific function */
396struct csio_hw_chip_ops t4_ops = {
397 .chip_set_mem_win = csio_t4_set_mem_win,
398 .chip_pcie_intr_handler = csio_t4_pcie_intr_handler,
399 .chip_flash_cfg_addr = csio_t4_flash_cfg_addr,
400 .chip_mc_read = csio_t4_mc_read,
401 .chip_edc_read = csio_t4_edc_read,
402 .chip_memory_rw = csio_t4_memory_rw,
403 .chip_dfs_create_ext_mem = csio_t4_dfs_create_ext_mem,
404};
diff --git a/drivers/scsi/csiostor/csio_hw_t5.c b/drivers/scsi/csiostor/csio_hw_t5.c
index 66e180a58718..3267f4f627c9 100644
--- a/drivers/scsi/csiostor/csio_hw_t5.c
+++ b/drivers/scsi/csiostor/csio_hw_t5.c
@@ -56,11 +56,11 @@ csio_t5_set_mem_win(struct csio_hw *hw, uint32_t win)
56 * back MA register to ensure that changes propagate before we attempt 56 * back MA register to ensure that changes propagate before we attempt
57 * to use the new values.) 57 * to use the new values.)
58 */ 58 */
59 csio_wr_reg32(hw, mem_win_base | BIR(0) | 59 csio_wr_reg32(hw, mem_win_base | BIR_V(0) |
60 WINDOW(ilog2(MEMWIN_APERTURE) - 10), 60 WINDOW_V(ilog2(MEMWIN_APERTURE) - 10),
61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 61 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
62 csio_rd_reg32(hw, 62 csio_rd_reg32(hw,
63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 63 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
64 64
65 return 0; 65 return 0;
66} 66}
@@ -72,74 +72,74 @@ static void
72csio_t5_pcie_intr_handler(struct csio_hw *hw) 72csio_t5_pcie_intr_handler(struct csio_hw *hw)
73{ 73{
74 static struct intr_info sysbus_intr_info[] = { 74 static struct intr_info sysbus_intr_info[] = {
75 { RNPP, "RXNP array parity error", -1, 1 }, 75 { RNPP_F, "RXNP array parity error", -1, 1 },
76 { RPCP, "RXPC array parity error", -1, 1 }, 76 { RPCP_F, "RXPC array parity error", -1, 1 },
77 { RCIP, "RXCIF array parity error", -1, 1 }, 77 { RCIP_F, "RXCIF array parity error", -1, 1 },
78 { RCCP, "Rx completions control array parity error", -1, 1 }, 78 { RCCP_F, "Rx completions control array parity error", -1, 1 },
79 { RFTP, "RXFT array parity error", -1, 1 }, 79 { RFTP_F, "RXFT array parity error", -1, 1 },
80 { 0, NULL, 0, 0 } 80 { 0, NULL, 0, 0 }
81 }; 81 };
82 static struct intr_info pcie_port_intr_info[] = { 82 static struct intr_info pcie_port_intr_info[] = {
83 { TPCP, "TXPC array parity error", -1, 1 }, 83 { TPCP_F, "TXPC array parity error", -1, 1 },
84 { TNPP, "TXNP array parity error", -1, 1 }, 84 { TNPP_F, "TXNP array parity error", -1, 1 },
85 { TFTP, "TXFT array parity error", -1, 1 }, 85 { TFTP_F, "TXFT array parity error", -1, 1 },
86 { TCAP, "TXCA array parity error", -1, 1 }, 86 { TCAP_F, "TXCA array parity error", -1, 1 },
87 { TCIP, "TXCIF array parity error", -1, 1 }, 87 { TCIP_F, "TXCIF array parity error", -1, 1 },
88 { RCAP, "RXCA array parity error", -1, 1 }, 88 { RCAP_F, "RXCA array parity error", -1, 1 },
89 { OTDD, "outbound request TLP discarded", -1, 1 }, 89 { OTDD_F, "outbound request TLP discarded", -1, 1 },
90 { RDPE, "Rx data parity error", -1, 1 }, 90 { RDPE_F, "Rx data parity error", -1, 1 },
91 { TDUE, "Tx uncorrectable data error", -1, 1 }, 91 { TDUE_F, "Tx uncorrectable data error", -1, 1 },
92 { 0, NULL, 0, 0 } 92 { 0, NULL, 0, 0 }
93 }; 93 };
94 94
95 static struct intr_info pcie_intr_info[] = { 95 static struct intr_info pcie_intr_info[] = {
96 { MSTGRPPERR, "Master Response Read Queue parity error", 96 { MSTGRPPERR_F, "Master Response Read Queue parity error",
97 -1, 1 }, 97 -1, 1 },
98 { MSTTIMEOUTPERR, "Master Timeout FIFO parity error", -1, 1 }, 98 { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
99 { MSIXSTIPERR, "MSI-X STI SRAM parity error", -1, 1 }, 99 { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
100 { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 }, 100 { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
101 { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 }, 101 { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
102 { MSIXDATAPERR, "MSI-X data parity error", -1, 1 }, 102 { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
103 { MSIXDIPERR, "MSI-X DI parity error", -1, 1 }, 103 { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
104 { PIOCPLGRPPERR, "PCI PIO completion Group FIFO parity error", 104 { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
105 -1, 1 }, 105 -1, 1 },
106 { PIOREQGRPPERR, "PCI PIO request Group FIFO parity error", 106 { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
107 -1, 1 }, 107 -1, 1 },
108 { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 }, 108 { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
109 { MSTTAGQPERR, "PCI master tag queue parity error", -1, 1 }, 109 { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
110 { CREQPERR, "PCI CMD channel request parity error", -1, 1 }, 110 { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
111 { CRSPPERR, "PCI CMD channel response parity error", -1, 1 }, 111 { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
112 { DREQWRPERR, "PCI DMA channel write request parity error", 112 { DREQWRPERR_F, "PCI DMA channel write request parity error",
113 -1, 1 }, 113 -1, 1 },
114 { DREQPERR, "PCI DMA channel request parity error", -1, 1 }, 114 { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
115 { DRSPPERR, "PCI DMA channel response parity error", -1, 1 }, 115 { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
116 { HREQWRPERR, "PCI HMA channel count parity error", -1, 1 }, 116 { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
117 { HREQPERR, "PCI HMA channel request parity error", -1, 1 }, 117 { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
118 { HRSPPERR, "PCI HMA channel response parity error", -1, 1 }, 118 { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
119 { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 }, 119 { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
120 { FIDPERR, "PCI FID parity error", -1, 1 }, 120 { FIDPERR_F, "PCI FID parity error", -1, 1 },
121 { VFIDPERR, "PCI INTx clear parity error", -1, 1 }, 121 { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
122 { MAGRPPERR, "PCI MA group FIFO parity error", -1, 1 }, 122 { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
123 { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 }, 123 { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
124 { IPRXHDRGRPPERR, "PCI IP Rx header group parity error", 124 { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
125 -1, 1 }, 125 -1, 1 },
126 { IPRXDATAGRPPERR, "PCI IP Rx data group parity error", 126 { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
127 -1, 1 }, 127 -1, 1 },
128 { RPLPERR, "PCI IP replay buffer parity error", -1, 1 }, 128 { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
129 { IPSOTPERR, "PCI IP SOT buffer parity error", -1, 1 }, 129 { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
130 { TRGT1GRPPERR, "PCI TRGT1 group FIFOs parity error", -1, 1 }, 130 { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
131 { READRSPERR, "Outbound read error", -1, 0 }, 131 { READRSPERR_F, "Outbound read error", -1, 0 },
132 { 0, NULL, 0, 0 } 132 { 0, NULL, 0, 0 }
133 }; 133 };
134 134
135 int fat; 135 int fat;
136 fat = csio_handle_intr_status(hw, 136 fat = csio_handle_intr_status(hw,
137 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS, 137 PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
138 sysbus_intr_info) + 138 sysbus_intr_info) +
139 csio_handle_intr_status(hw, 139 csio_handle_intr_status(hw,
140 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS, 140 PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
141 pcie_port_intr_info) + 141 pcie_port_intr_info) +
142 csio_handle_intr_status(hw, PCIE_INT_CAUSE, pcie_intr_info); 142 csio_handle_intr_status(hw, PCIE_INT_CAUSE_A, pcie_intr_info);
143 if (fat) 143 if (fat)
144 csio_hw_fatal_err(hw); 144 csio_hw_fatal_err(hw);
145} 145}
@@ -177,25 +177,25 @@ csio_t5_mc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
177 uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg; 177 uint32_t mc_bist_cmd_reg, mc_bist_cmd_addr_reg, mc_bist_cmd_len_reg;
178 uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg; 178 uint32_t mc_bist_status_rdata_reg, mc_bist_data_pattern_reg;
179 179
180 mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD, idx); 180 mc_bist_cmd_reg = MC_REG(MC_P_BIST_CMD_A, idx);
181 mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR, idx); 181 mc_bist_cmd_addr_reg = MC_REG(MC_P_BIST_CMD_ADDR_A, idx);
182 mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN, idx); 182 mc_bist_cmd_len_reg = MC_REG(MC_P_BIST_CMD_LEN_A, idx);
183 mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA, idx); 183 mc_bist_status_rdata_reg = MC_REG(MC_P_BIST_STATUS_RDATA_A, idx);
184 mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN, idx); 184 mc_bist_data_pattern_reg = MC_REG(MC_P_BIST_DATA_PATTERN_A, idx);
185 185
186 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST) 186 if (csio_rd_reg32(hw, mc_bist_cmd_reg) & START_BIST_F)
187 return -EBUSY; 187 return -EBUSY;
188 csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg); 188 csio_wr_reg32(hw, addr & ~0x3fU, mc_bist_cmd_addr_reg);
189 csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg); 189 csio_wr_reg32(hw, 64, mc_bist_cmd_len_reg);
190 csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg); 190 csio_wr_reg32(hw, 0xc, mc_bist_data_pattern_reg);
191 csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1), 191 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
192 mc_bist_cmd_reg); 192 mc_bist_cmd_reg);
193 i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST, 193 i = csio_hw_wait_op_done_val(hw, mc_bist_cmd_reg, START_BIST_F,
194 0, 10, 1, NULL); 194 0, 10, 1, NULL);
195 if (i) 195 if (i)
196 return i; 196 return i;
197 197
198#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i) 198#define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA_A, i)
199 199
200 for (i = 15; i >= 0; i--) 200 for (i = 15; i >= 0; i--)
201 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i))); 201 *data++ = htonl(csio_rd_reg32(hw, MC_DATA(i)));
@@ -231,27 +231,27 @@ csio_t5_edc_read(struct csio_hw *hw, int idx, uint32_t addr, __be32 *data,
231#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR) 231#define EDC_STRIDE_T5 (EDC_T51_BASE_ADDR - EDC_T50_BASE_ADDR)
232#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx) 232#define EDC_REG_T5(reg, idx) (reg + EDC_STRIDE_T5 * idx)
233 233
234 edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD, idx); 234 edc_bist_cmd_reg = EDC_REG_T5(EDC_H_BIST_CMD_A, idx);
235 edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR, idx); 235 edc_bist_cmd_addr_reg = EDC_REG_T5(EDC_H_BIST_CMD_ADDR_A, idx);
236 edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN, idx); 236 edc_bist_cmd_len_reg = EDC_REG_T5(EDC_H_BIST_CMD_LEN_A, idx);
237 edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN, idx); 237 edc_bist_cmd_data_pattern = EDC_REG_T5(EDC_H_BIST_DATA_PATTERN_A, idx);
238 edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA, idx); 238 edc_bist_status_rdata_reg = EDC_REG_T5(EDC_H_BIST_STATUS_RDATA_A, idx);
239#undef EDC_REG_T5 239#undef EDC_REG_T5
240#undef EDC_STRIDE_T5 240#undef EDC_STRIDE_T5
241 241
242 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST) 242 if (csio_rd_reg32(hw, edc_bist_cmd_reg) & START_BIST_F)
243 return -EBUSY; 243 return -EBUSY;
244 csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg); 244 csio_wr_reg32(hw, addr & ~0x3fU, edc_bist_cmd_addr_reg);
245 csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg); 245 csio_wr_reg32(hw, 64, edc_bist_cmd_len_reg);
246 csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern); 246 csio_wr_reg32(hw, 0xc, edc_bist_cmd_data_pattern);
247 csio_wr_reg32(hw, BIST_OPCODE(1) | START_BIST | BIST_CMD_GAP(1), 247 csio_wr_reg32(hw, BIST_OPCODE_V(1) | START_BIST_F | BIST_CMD_GAP_V(1),
248 edc_bist_cmd_reg); 248 edc_bist_cmd_reg);
249 i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST, 249 i = csio_hw_wait_op_done_val(hw, edc_bist_cmd_reg, START_BIST_F,
250 0, 10, 1, NULL); 250 0, 10, 1, NULL);
251 if (i) 251 if (i)
252 return i; 252 return i;
253 253
254#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx) 254#define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA_A, i) + idx)
255 255
256 for (i = 15; i >= 0; i--) 256 for (i = 15; i >= 0; i--)
257 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i))); 257 *data++ = htonl(csio_rd_reg32(hw, EDC_DATA(i)));
@@ -320,13 +320,13 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
320 * the address is relative to BAR0. 320 * the address is relative to BAR0.
321 */ 321 */
322 mem_reg = csio_rd_reg32(hw, 322 mem_reg = csio_rd_reg32(hw,
323 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN, win)); 323 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, win));
324 mem_aperture = 1 << (WINDOW(mem_reg) + 10); 324 mem_aperture = 1 << (WINDOW_V(mem_reg) + 10);
325 mem_base = GET_PCIEOFST(mem_reg) << 10; 325 mem_base = PCIEOFST_G(mem_reg) << 10;
326 326
327 start = addr & ~(mem_aperture-1); 327 start = addr & ~(mem_aperture-1);
328 offset = addr - start; 328 offset = addr - start;
329 win_pf = V_PFNUM(hw->pfn); 329 win_pf = PFNUM_V(hw->pfn);
330 330
331 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n", 331 csio_dbg(hw, "csio_t5_memory_rw: mem_reg: 0x%x, mem_aperture: 0x%x\n",
332 mem_reg, mem_aperture); 332 mem_reg, mem_aperture);
@@ -344,9 +344,9 @@ csio_t5_memory_rw(struct csio_hw *hw, u32 win, int mtype, u32 addr,
344 * before we attempt to use the new value. 344 * before we attempt to use the new value.
345 */ 345 */
346 csio_wr_reg32(hw, pos | win_pf, 346 csio_wr_reg32(hw, pos | win_pf,
347 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 347 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
348 csio_rd_reg32(hw, 348 csio_rd_reg32(hw,
349 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET, win)); 349 PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
350 350
351 while (offset < mem_aperture && len > 0) { 351 while (offset < mem_aperture && len > 0) {
352 if (dir) 352 if (dir)
diff --git a/drivers/scsi/csiostor/csio_init.c b/drivers/scsi/csiostor/csio_init.c
index 34d20cc3e110..d9631e15f7b5 100644
--- a/drivers/scsi/csiostor/csio_init.c
+++ b/drivers/scsi/csiostor/csio_init.c
@@ -113,12 +113,9 @@ static const struct file_operations csio_mem_debugfs_fops = {
113void csio_add_debugfs_mem(struct csio_hw *hw, const char *name, 113void csio_add_debugfs_mem(struct csio_hw *hw, const char *name,
114 unsigned int idx, unsigned int size_mb) 114 unsigned int idx, unsigned int size_mb)
115{ 115{
116 struct dentry *de; 116 debugfs_create_file_size(name, S_IRUSR, hw->debugfs_root,
117 117 (void *)hw + idx, &csio_mem_debugfs_fops,
118 de = debugfs_create_file(name, S_IRUSR, hw->debugfs_root, 118 size_mb << 20);
119 (void *)hw + idx, &csio_mem_debugfs_fops);
120 if (de && de->d_inode)
121 de->d_inode->i_size = size_mb << 20;
122} 119}
123 120
124static int csio_setup_debugfs(struct csio_hw *hw) 121static int csio_setup_debugfs(struct csio_hw *hw)
@@ -1176,9 +1173,8 @@ static struct pci_error_handlers csio_err_handler = {
1176 */ 1173 */
1177#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \ 1174#define CH_PCI_DEVICE_ID_TABLE_DEFINE_BEGIN \
1178 static struct pci_device_id csio_pci_tbl[] = { 1175 static struct pci_device_id csio_pci_tbl[] = {
1179/* Define for iSCSI uses PF5, FCoE uses PF6 */ 1176/* Define for FCoE uses PF6 */
1180#define CH_PCI_DEVICE_ID_FUNCTION 0x5 1177#define CH_PCI_DEVICE_ID_FUNCTION 0x6
1181#define CH_PCI_DEVICE_ID_FUNCTION2 0x6
1182 1178
1183#define CH_PCI_ID_TABLE_ENTRY(devid) \ 1179#define CH_PCI_ID_TABLE_ENTRY(devid) \
1184 { PCI_VDEVICE(CHELSIO, (devid)), 0 } 1180 { PCI_VDEVICE(CHELSIO, (devid)), 0 }
@@ -1256,5 +1252,4 @@ MODULE_DESCRIPTION(CSIO_DRV_DESC);
1256MODULE_LICENSE(CSIO_DRV_LICENSE); 1252MODULE_LICENSE(CSIO_DRV_LICENSE);
1257MODULE_DEVICE_TABLE(pci, csio_pci_tbl); 1253MODULE_DEVICE_TABLE(pci, csio_pci_tbl);
1258MODULE_VERSION(CSIO_DRV_VERSION); 1254MODULE_VERSION(CSIO_DRV_VERSION);
1259MODULE_FIRMWARE(FW_FNAME_T4);
1260MODULE_FIRMWARE(FW_FNAME_T5); 1255MODULE_FIRMWARE(FW_FNAME_T5);
diff --git a/drivers/scsi/csiostor/csio_isr.c b/drivers/scsi/csiostor/csio_isr.c
index a8c748a35f9c..2fb71c6c3b37 100644
--- a/drivers/scsi/csiostor/csio_isr.c
+++ b/drivers/scsi/csiostor/csio_isr.c
@@ -317,7 +317,7 @@ csio_fcoe_isr(int irq, void *dev_id)
317 317
318 /* Disable the interrupt for this PCI function. */ 318 /* Disable the interrupt for this PCI function. */
319 if (hw->intr_mode == CSIO_IM_INTX) 319 if (hw->intr_mode == CSIO_IM_INTX)
320 csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI)); 320 csio_wr_reg32(hw, 0, MYPF_REG(PCIE_PF_CLI_A));
321 321
322 /* 322 /*
323 * The read in the following function will flush the 323 * The read in the following function will flush the
diff --git a/drivers/scsi/csiostor/csio_lnode.c b/drivers/scsi/csiostor/csio_lnode.c
index 87f9280d9b43..c00b2ff72b55 100644
--- a/drivers/scsi/csiostor/csio_lnode.c
+++ b/drivers/scsi/csiostor/csio_lnode.c
@@ -1758,7 +1758,7 @@ csio_ln_mgmt_submit_wr(struct csio_mgmtm *mgmtm, struct csio_ioreq *io_req,
1758 else { 1758 else {
1759 /* Program DSGL to dma payload */ 1759 /* Program DSGL to dma payload */
1760 dsgl.cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) | 1760 dsgl.cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) |
1761 ULPTX_MORE | ULPTX_NSGE(1)); 1761 ULPTX_MORE_F | ULPTX_NSGE_V(1));
1762 dsgl.len0 = cpu_to_be32(pld_len); 1762 dsgl.len0 = cpu_to_be32(pld_len);
1763 dsgl.addr0 = cpu_to_be64(pld->paddr); 1763 dsgl.addr0 = cpu_to_be64(pld->paddr);
1764 csio_wr_copy_to_wrp(&dsgl, &wrp, ALIGN(wr_off, 8), 1764 csio_wr_copy_to_wrp(&dsgl, &wrp, ALIGN(wr_off, 8),
diff --git a/drivers/scsi/csiostor/csio_mb.c b/drivers/scsi/csiostor/csio_mb.c
index 08c265c0f353..9451787ca7f2 100644
--- a/drivers/scsi/csiostor/csio_mb.c
+++ b/drivers/scsi/csiostor/csio_mb.c
@@ -327,7 +327,8 @@ csio_mb_caps_config(struct csio_hw *hw, struct csio_mb *mbp, uint32_t tmo,
327} 327}
328 328
329#define CSIO_ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\ 329#define CSIO_ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
330 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG) 330 FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_SPEED_40G |\
331 FW_PORT_CAP_ANEG)
331 332
332/* 333/*
333 * csio_mb_port- FW PORT command helper 334 * csio_mb_port- FW PORT command helper
@@ -1104,8 +1105,8 @@ csio_mb_process_portparams_rsp(struct csio_hw *hw,
1104void 1105void
1105csio_mb_intr_enable(struct csio_hw *hw) 1106csio_mb_intr_enable(struct csio_hw *hw)
1106{ 1107{
1107 csio_wr_reg32(hw, MBMSGRDYINTEN(1), MYPF_REG(CIM_PF_HOST_INT_ENABLE)); 1108 csio_wr_reg32(hw, MBMSGRDYINTEN_F, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
1108 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE)); 1109 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
1109} 1110}
1110 1111
1111/* 1112/*
@@ -1117,8 +1118,9 @@ csio_mb_intr_enable(struct csio_hw *hw)
1117void 1118void
1118csio_mb_intr_disable(struct csio_hw *hw) 1119csio_mb_intr_disable(struct csio_hw *hw)
1119{ 1120{
1120 csio_wr_reg32(hw, MBMSGRDYINTEN(0), MYPF_REG(CIM_PF_HOST_INT_ENABLE)); 1121 csio_wr_reg32(hw, MBMSGRDYINTEN_V(0),
1121 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE)); 1122 MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
1123 csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_ENABLE_A));
1122} 1124}
1123 1125
1124static void 1126static void
@@ -1153,8 +1155,8 @@ csio_mb_debug_cmd_handler(struct csio_hw *hw)
1153{ 1155{
1154 int i; 1156 int i;
1155 __be64 cmd[CSIO_MB_MAX_REGS]; 1157 __be64 cmd[CSIO_MB_MAX_REGS];
1156 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL); 1158 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A);
1157 uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA); 1159 uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A);
1158 int size = sizeof(struct fw_debug_cmd); 1160 int size = sizeof(struct fw_debug_cmd);
1159 1161
1160 /* Copy mailbox data */ 1162 /* Copy mailbox data */
@@ -1164,8 +1166,8 @@ csio_mb_debug_cmd_handler(struct csio_hw *hw)
1164 csio_mb_dump_fw_dbg(hw, cmd); 1166 csio_mb_dump_fw_dbg(hw, cmd);
1165 1167
1166 /* Notify FW of mailbox by setting owner as UP */ 1168 /* Notify FW of mailbox by setting owner as UP */
1167 csio_wr_reg32(hw, MBMSGVALID | MBINTREQ | MBOWNER(CSIO_MBOWNER_FW), 1169 csio_wr_reg32(hw, MBMSGVALID_F | MBINTREQ_F |
1168 ctl_reg); 1170 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg);
1169 1171
1170 csio_rd_reg32(hw, ctl_reg); 1172 csio_rd_reg32(hw, ctl_reg);
1171 wmb(); 1173 wmb();
@@ -1187,8 +1189,8 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
1187 __be64 *cmd = mbp->mb; 1189 __be64 *cmd = mbp->mb;
1188 __be64 hdr; 1190 __be64 hdr;
1189 struct csio_mbm *mbm = &hw->mbm; 1191 struct csio_mbm *mbm = &hw->mbm;
1190 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL); 1192 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A);
1191 uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA); 1193 uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A);
1192 int size = mbp->mb_size; 1194 int size = mbp->mb_size;
1193 int rv = -EINVAL; 1195 int rv = -EINVAL;
1194 struct fw_cmd_hdr *fw_hdr; 1196 struct fw_cmd_hdr *fw_hdr;
@@ -1224,12 +1226,12 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
1224 } 1226 }
1225 1227
1226 /* Now get ownership of mailbox */ 1228 /* Now get ownership of mailbox */
1227 owner = MBOWNER_GET(csio_rd_reg32(hw, ctl_reg)); 1229 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg));
1228 1230
1229 if (!csio_mb_is_host_owner(owner)) { 1231 if (!csio_mb_is_host_owner(owner)) {
1230 1232
1231 for (i = 0; (owner == CSIO_MBOWNER_NONE) && (i < 3); i++) 1233 for (i = 0; (owner == CSIO_MBOWNER_NONE) && (i < 3); i++)
1232 owner = MBOWNER_GET(csio_rd_reg32(hw, ctl_reg)); 1234 owner = MBOWNER_G(csio_rd_reg32(hw, ctl_reg));
1233 /* 1235 /*
1234 * Mailbox unavailable. In immediate mode, fail the command. 1236 * Mailbox unavailable. In immediate mode, fail the command.
1235 * In other modes, enqueue the request. 1237 * In other modes, enqueue the request.
@@ -1271,10 +1273,10 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
1271 if (mbp->mb_cbfn != NULL) { 1273 if (mbp->mb_cbfn != NULL) {
1272 mbm->mcurrent = mbp; 1274 mbm->mcurrent = mbp;
1273 mod_timer(&mbm->timer, jiffies + msecs_to_jiffies(mbp->tmo)); 1275 mod_timer(&mbm->timer, jiffies + msecs_to_jiffies(mbp->tmo));
1274 csio_wr_reg32(hw, MBMSGVALID | MBINTREQ | 1276 csio_wr_reg32(hw, MBMSGVALID_F | MBINTREQ_F |
1275 MBOWNER(CSIO_MBOWNER_FW), ctl_reg); 1277 MBOWNER_V(CSIO_MBOWNER_FW), ctl_reg);
1276 } else 1278 } else
1277 csio_wr_reg32(hw, MBMSGVALID | MBOWNER(CSIO_MBOWNER_FW), 1279 csio_wr_reg32(hw, MBMSGVALID_F | MBOWNER_V(CSIO_MBOWNER_FW),
1278 ctl_reg); 1280 ctl_reg);
1279 1281
1280 /* Flush posted writes */ 1282 /* Flush posted writes */
@@ -1294,9 +1296,9 @@ csio_mb_issue(struct csio_hw *hw, struct csio_mb *mbp)
1294 1296
1295 /* Check for response */ 1297 /* Check for response */
1296 ctl = csio_rd_reg32(hw, ctl_reg); 1298 ctl = csio_rd_reg32(hw, ctl_reg);
1297 if (csio_mb_is_host_owner(MBOWNER_GET(ctl))) { 1299 if (csio_mb_is_host_owner(MBOWNER_G(ctl))) {
1298 1300
1299 if (!(ctl & MBMSGVALID)) { 1301 if (!(ctl & MBMSGVALID_F)) {
1300 csio_wr_reg32(hw, 0, ctl_reg); 1302 csio_wr_reg32(hw, 0, ctl_reg);
1301 continue; 1303 continue;
1302 } 1304 }
@@ -1457,16 +1459,16 @@ csio_mb_isr_handler(struct csio_hw *hw)
1457 __be64 *cmd; 1459 __be64 *cmd;
1458 uint32_t ctl, cim_cause, pl_cause; 1460 uint32_t ctl, cim_cause, pl_cause;
1459 int i; 1461 int i;
1460 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL); 1462 uint32_t ctl_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_CTRL_A);
1461 uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA); 1463 uint32_t data_reg = PF_REG(hw->pfn, CIM_PF_MAILBOX_DATA_A);
1462 int size; 1464 int size;
1463 __be64 hdr; 1465 __be64 hdr;
1464 struct fw_cmd_hdr *fw_hdr; 1466 struct fw_cmd_hdr *fw_hdr;
1465 1467
1466 pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE)); 1468 pl_cause = csio_rd_reg32(hw, MYPF_REG(PL_PF_INT_CAUSE_A));
1467 cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE)); 1469 cim_cause = csio_rd_reg32(hw, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
1468 1470
1469 if (!(pl_cause & PFCIM) || !(cim_cause & MBMSGRDYINT)) { 1471 if (!(pl_cause & PFCIM_F) || !(cim_cause & MBMSGRDYINT_F)) {
1470 CSIO_INC_STATS(hw, n_mbint_unexp); 1472 CSIO_INC_STATS(hw, n_mbint_unexp);
1471 return -EINVAL; 1473 return -EINVAL;
1472 } 1474 }
@@ -1477,16 +1479,16 @@ csio_mb_isr_handler(struct csio_hw *hw)
1477 * the upper level cause register. In other words, CIM-cause 1479 * the upper level cause register. In other words, CIM-cause
1478 * first followed by PL-Cause next. 1480 * first followed by PL-Cause next.
1479 */ 1481 */
1480 csio_wr_reg32(hw, MBMSGRDYINT, MYPF_REG(CIM_PF_HOST_INT_CAUSE)); 1482 csio_wr_reg32(hw, MBMSGRDYINT_F, MYPF_REG(CIM_PF_HOST_INT_CAUSE_A));
1481 csio_wr_reg32(hw, PFCIM, MYPF_REG(PL_PF_INT_CAUSE)); 1483 csio_wr_reg32(hw, PFCIM_F, MYPF_REG(PL_PF_INT_CAUSE_A));
1482 1484
1483 ctl = csio_rd_reg32(hw, ctl_reg); 1485 ctl = csio_rd_reg32(hw, ctl_reg);
1484 1486
1485 if (csio_mb_is_host_owner(MBOWNER_GET(ctl))) { 1487 if (csio_mb_is_host_owner(MBOWNER_G(ctl))) {
1486 1488
1487 CSIO_DUMP_MB(hw, hw->pfn, data_reg); 1489 CSIO_DUMP_MB(hw, hw->pfn, data_reg);
1488 1490
1489 if (!(ctl & MBMSGVALID)) { 1491 if (!(ctl & MBMSGVALID_F)) {
1490 csio_warn(hw, 1492 csio_warn(hw,
1491 "Stray mailbox interrupt recvd," 1493 "Stray mailbox interrupt recvd,"
1492 " mailbox data not valid\n"); 1494 " mailbox data not valid\n");
diff --git a/drivers/scsi/csiostor/csio_scsi.c b/drivers/scsi/csiostor/csio_scsi.c
index 3987284e0d2a..2c4562d82dc0 100644
--- a/drivers/scsi/csiostor/csio_scsi.c
+++ b/drivers/scsi/csiostor/csio_scsi.c
@@ -298,8 +298,8 @@ csio_scsi_init_ultptx_dsgl(struct csio_hw *hw, struct csio_ioreq *req,
298 struct csio_dma_buf *dma_buf; 298 struct csio_dma_buf *dma_buf;
299 struct scsi_cmnd *scmnd = csio_scsi_cmnd(req); 299 struct scsi_cmnd *scmnd = csio_scsi_cmnd(req);
300 300
301 sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) | ULPTX_MORE | 301 sgl->cmd_nsge = htonl(ULPTX_CMD_V(ULP_TX_SC_DSGL) | ULPTX_MORE_F |
302 ULPTX_NSGE(req->nsge)); 302 ULPTX_NSGE_V(req->nsge));
303 /* Now add the data SGLs */ 303 /* Now add the data SGLs */
304 if (likely(!req->dcopy)) { 304 if (likely(!req->dcopy)) {
305 scsi_for_each_sg(scmnd, sgel, req->nsge, i) { 305 scsi_for_each_sg(scmnd, sgel, req->nsge, i) {
diff --git a/drivers/scsi/csiostor/csio_wr.c b/drivers/scsi/csiostor/csio_wr.c
index 773da14cfa14..e8f18174f2e9 100644
--- a/drivers/scsi/csiostor/csio_wr.c
+++ b/drivers/scsi/csiostor/csio_wr.c
@@ -51,12 +51,12 @@ int csio_intr_coalesce_time = 10; /* value:SGE_TIMER_VALUE_1 */
51static int csio_sge_timer_reg = 1; 51static int csio_sge_timer_reg = 1;
52 52
53#define CSIO_SET_FLBUF_SIZE(_hw, _reg, _val) \ 53#define CSIO_SET_FLBUF_SIZE(_hw, _reg, _val) \
54 csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg) 54 csio_wr_reg32((_hw), (_val), SGE_FL_BUFFER_SIZE##_reg##_A)
55 55
56static void 56static void
57csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg) 57csio_get_flbuf_size(struct csio_hw *hw, struct csio_sge *sge, uint32_t reg)
58{ 58{
59 sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0 + 59 sge->sge_fl_buf_size[reg] = csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE0_A +
60 reg * sizeof(uint32_t)); 60 reg * sizeof(uint32_t));
61} 61}
62 62
@@ -71,7 +71,7 @@ csio_wr_fl_bufsz(struct csio_sge *sge, struct csio_dma_buf *buf)
71static inline uint32_t 71static inline uint32_t
72csio_wr_qstat_pgsz(struct csio_hw *hw) 72csio_wr_qstat_pgsz(struct csio_hw *hw)
73{ 73{
74 return (hw->wrm.sge.sge_control & EGRSTATUSPAGESIZE(1)) ? 128 : 64; 74 return (hw->wrm.sge.sge_control & EGRSTATUSPAGESIZE_F) ? 128 : 64;
75} 75}
76 76
77/* Ring freelist doorbell */ 77/* Ring freelist doorbell */
@@ -84,9 +84,9 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq)
84 * 8 freelist buffer pointers (since each pointer is 8 bytes). 84 * 8 freelist buffer pointers (since each pointer is 8 bytes).
85 */ 85 */
86 if (flq->inc_idx >= 8) { 86 if (flq->inc_idx >= 8) {
87 csio_wr_reg32(hw, DBPRIO(1) | QID(flq->un.fl.flid) | 87 csio_wr_reg32(hw, DBPRIO_F | QID_V(flq->un.fl.flid) |
88 CSIO_HW_PIDX(hw, flq->inc_idx / 8), 88 PIDX_T5_V(flq->inc_idx / 8) | DBTYPE_F,
89 MYPF_REG(SGE_PF_KDOORBELL)); 89 MYPF_REG(SGE_PF_KDOORBELL_A));
90 flq->inc_idx &= 7; 90 flq->inc_idx &= 7;
91 } 91 }
92} 92}
@@ -95,10 +95,10 @@ csio_wr_ring_fldb(struct csio_hw *hw, struct csio_q *flq)
95static void 95static void
96csio_wr_sge_intr_enable(struct csio_hw *hw, uint16_t iqid) 96csio_wr_sge_intr_enable(struct csio_hw *hw, uint16_t iqid)
97{ 97{
98 csio_wr_reg32(hw, CIDXINC(0) | 98 csio_wr_reg32(hw, CIDXINC_V(0) |
99 INGRESSQID(iqid) | 99 INGRESSQID_V(iqid) |
100 TIMERREG(X_TIMERREG_RESTART_COUNTER), 100 TIMERREG_V(X_TIMERREG_RESTART_COUNTER),
101 MYPF_REG(SGE_PF_GTS)); 101 MYPF_REG(SGE_PF_GTS_A));
102} 102}
103 103
104/* 104/*
@@ -982,9 +982,9 @@ csio_wr_issue(struct csio_hw *hw, int qidx, bool prio)
982 982
983 wmb(); 983 wmb();
984 /* Ring SGE Doorbell writing q->pidx into it */ 984 /* Ring SGE Doorbell writing q->pidx into it */
985 csio_wr_reg32(hw, DBPRIO(prio) | QID(q->un.eq.physeqid) | 985 csio_wr_reg32(hw, DBPRIO_V(prio) | QID_V(q->un.eq.physeqid) |
986 CSIO_HW_PIDX(hw, q->inc_idx), 986 PIDX_T5_V(q->inc_idx) | DBTYPE_F,
987 MYPF_REG(SGE_PF_KDOORBELL)); 987 MYPF_REG(SGE_PF_KDOORBELL_A));
988 q->inc_idx = 0; 988 q->inc_idx = 0;
989 989
990 return 0; 990 return 0;
@@ -1242,10 +1242,10 @@ csio_wr_process_iq(struct csio_hw *hw, struct csio_q *q,
1242 1242
1243restart: 1243restart:
1244 /* Now inform SGE about our incremental index value */ 1244 /* Now inform SGE about our incremental index value */
1245 csio_wr_reg32(hw, CIDXINC(q->inc_idx) | 1245 csio_wr_reg32(hw, CIDXINC_V(q->inc_idx) |
1246 INGRESSQID(q->un.iq.physiqid) | 1246 INGRESSQID_V(q->un.iq.physiqid) |
1247 TIMERREG(csio_sge_timer_reg), 1247 TIMERREG_V(csio_sge_timer_reg),
1248 MYPF_REG(SGE_PF_GTS)); 1248 MYPF_REG(SGE_PF_GTS_A));
1249 q->stats.n_tot_rsps += q->inc_idx; 1249 q->stats.n_tot_rsps += q->inc_idx;
1250 1250
1251 q->inc_idx = 0; 1251 q->inc_idx = 0;
@@ -1310,22 +1310,23 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
1310 uint32_t ingpad = 0; 1310 uint32_t ingpad = 0;
1311 uint32_t stat_len = clsz > 64 ? 128 : 64; 1311 uint32_t stat_len = clsz > 64 ? 128 : 64;
1312 1312
1313 csio_wr_reg32(hw, HOSTPAGESIZEPF0(s_hps) | HOSTPAGESIZEPF1(s_hps) | 1313 csio_wr_reg32(hw, HOSTPAGESIZEPF0_V(s_hps) | HOSTPAGESIZEPF1_V(s_hps) |
1314 HOSTPAGESIZEPF2(s_hps) | HOSTPAGESIZEPF3(s_hps) | 1314 HOSTPAGESIZEPF2_V(s_hps) | HOSTPAGESIZEPF3_V(s_hps) |
1315 HOSTPAGESIZEPF4(s_hps) | HOSTPAGESIZEPF5(s_hps) | 1315 HOSTPAGESIZEPF4_V(s_hps) | HOSTPAGESIZEPF5_V(s_hps) |
1316 HOSTPAGESIZEPF6(s_hps) | HOSTPAGESIZEPF7(s_hps), 1316 HOSTPAGESIZEPF6_V(s_hps) | HOSTPAGESIZEPF7_V(s_hps),
1317 SGE_HOST_PAGE_SIZE); 1317 SGE_HOST_PAGE_SIZE_A);
1318 1318
1319 sge->csio_fl_align = clsz < 32 ? 32 : clsz; 1319 sge->csio_fl_align = clsz < 32 ? 32 : clsz;
1320 ingpad = ilog2(sge->csio_fl_align) - 5; 1320 ingpad = ilog2(sge->csio_fl_align) - 5;
1321 1321
1322 csio_set_reg_field(hw, SGE_CONTROL, INGPADBOUNDARY_MASK | 1322 csio_set_reg_field(hw, SGE_CONTROL_A,
1323 EGRSTATUSPAGESIZE(1), 1323 INGPADBOUNDARY_V(INGPADBOUNDARY_M) |
1324 INGPADBOUNDARY(ingpad) | 1324 EGRSTATUSPAGESIZE_F,
1325 EGRSTATUSPAGESIZE(stat_len != 64)); 1325 INGPADBOUNDARY_V(ingpad) |
1326 EGRSTATUSPAGESIZE_V(stat_len != 64));
1326 1327
1327 /* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */ 1328 /* FL BUFFER SIZE#0 is Page size i,e already aligned to cache line */
1328 csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0); 1329 csio_wr_reg32(hw, PAGE_SIZE, SGE_FL_BUFFER_SIZE0_A);
1329 1330
1330 /* 1331 /*
1331 * If using hard params, the following will get set correctly 1332 * If using hard params, the following will get set correctly
@@ -1333,23 +1334,24 @@ csio_wr_fixup_host_params(struct csio_hw *hw)
1333 */ 1334 */
1334 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) { 1335 if (hw->flags & CSIO_HWF_USING_SOFT_PARAMS) {
1335 csio_wr_reg32(hw, 1336 csio_wr_reg32(hw,
1336 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2) + 1337 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE2_A) +
1337 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1), 1338 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
1338 SGE_FL_BUFFER_SIZE2); 1339 SGE_FL_BUFFER_SIZE2_A);
1339 csio_wr_reg32(hw, 1340 csio_wr_reg32(hw,
1340 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3) + 1341 (csio_rd_reg32(hw, SGE_FL_BUFFER_SIZE3_A) +
1341 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1), 1342 sge->csio_fl_align - 1) & ~(sge->csio_fl_align - 1),
1342 SGE_FL_BUFFER_SIZE3); 1343 SGE_FL_BUFFER_SIZE3_A);
1343 } 1344 }
1344 1345
1345 csio_wr_reg32(hw, HPZ0(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ); 1346 csio_wr_reg32(hw, HPZ0_V(PAGE_SHIFT - 12), ULP_RX_TDDP_PSZ_A);
1346 1347
1347 /* default value of rx_dma_offset of the NIC driver */ 1348 /* default value of rx_dma_offset of the NIC driver */
1348 csio_set_reg_field(hw, SGE_CONTROL, PKTSHIFT_MASK, 1349 csio_set_reg_field(hw, SGE_CONTROL_A,
1349 PKTSHIFT(CSIO_SGE_RX_DMA_OFFSET)); 1350 PKTSHIFT_V(PKTSHIFT_M),
1351 PKTSHIFT_V(CSIO_SGE_RX_DMA_OFFSET));
1350 1352
1351 csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG, 1353 csio_hw_tp_wr_bits_indirect(hw, TP_INGRESS_CONFIG_A,
1352 CSUM_HAS_PSEUDO_HDR, 0); 1354 CSUM_HAS_PSEUDO_HDR_F, 0);
1353} 1355}
1354 1356
1355static void 1357static void
@@ -1384,9 +1386,9 @@ csio_wr_get_sge(struct csio_hw *hw)
1384 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5; 1386 u32 timer_value_0_and_1, timer_value_2_and_3, timer_value_4_and_5;
1385 u32 ingress_rx_threshold; 1387 u32 ingress_rx_threshold;
1386 1388
1387 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL); 1389 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);
1388 1390
1389 ingpad = INGPADBOUNDARY_GET(sge->sge_control); 1391 ingpad = INGPADBOUNDARY_G(sge->sge_control);
1390 1392
1391 switch (ingpad) { 1393 switch (ingpad) {
1392 case X_INGPCIEBOUNDARY_32B: 1394 case X_INGPCIEBOUNDARY_32B:
@@ -1410,28 +1412,28 @@ csio_wr_get_sge(struct csio_hw *hw)
1410 for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++) 1412 for (i = 0; i < CSIO_SGE_FL_SIZE_REGS; i++)
1411 csio_get_flbuf_size(hw, sge, i); 1413 csio_get_flbuf_size(hw, sge, i);
1412 1414
1413 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1); 1415 timer_value_0_and_1 = csio_rd_reg32(hw, SGE_TIMER_VALUE_0_AND_1_A);
1414 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3); 1416 timer_value_2_and_3 = csio_rd_reg32(hw, SGE_TIMER_VALUE_2_AND_3_A);
1415 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5); 1417 timer_value_4_and_5 = csio_rd_reg32(hw, SGE_TIMER_VALUE_4_AND_5_A);
1416 1418
1417 sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw, 1419 sge->timer_val[0] = (uint16_t)csio_core_ticks_to_us(hw,
1418 TIMERVALUE0_GET(timer_value_0_and_1)); 1420 TIMERVALUE0_G(timer_value_0_and_1));
1419 sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw, 1421 sge->timer_val[1] = (uint16_t)csio_core_ticks_to_us(hw,
1420 TIMERVALUE1_GET(timer_value_0_and_1)); 1422 TIMERVALUE1_G(timer_value_0_and_1));
1421 sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw, 1423 sge->timer_val[2] = (uint16_t)csio_core_ticks_to_us(hw,
1422 TIMERVALUE2_GET(timer_value_2_and_3)); 1424 TIMERVALUE2_G(timer_value_2_and_3));
1423 sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw, 1425 sge->timer_val[3] = (uint16_t)csio_core_ticks_to_us(hw,
1424 TIMERVALUE3_GET(timer_value_2_and_3)); 1426 TIMERVALUE3_G(timer_value_2_and_3));
1425 sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw, 1427 sge->timer_val[4] = (uint16_t)csio_core_ticks_to_us(hw,
1426 TIMERVALUE4_GET(timer_value_4_and_5)); 1428 TIMERVALUE4_G(timer_value_4_and_5));
1427 sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw, 1429 sge->timer_val[5] = (uint16_t)csio_core_ticks_to_us(hw,
1428 TIMERVALUE5_GET(timer_value_4_and_5)); 1430 TIMERVALUE5_G(timer_value_4_and_5));
1429 1431
1430 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD); 1432 ingress_rx_threshold = csio_rd_reg32(hw, SGE_INGRESS_RX_THRESHOLD_A);
1431 sge->counter_val[0] = THRESHOLD_0_GET(ingress_rx_threshold); 1433 sge->counter_val[0] = THRESHOLD_0_G(ingress_rx_threshold);
1432 sge->counter_val[1] = THRESHOLD_1_GET(ingress_rx_threshold); 1434 sge->counter_val[1] = THRESHOLD_1_G(ingress_rx_threshold);
1433 sge->counter_val[2] = THRESHOLD_2_GET(ingress_rx_threshold); 1435 sge->counter_val[2] = THRESHOLD_2_G(ingress_rx_threshold);
1434 sge->counter_val[3] = THRESHOLD_3_GET(ingress_rx_threshold); 1436 sge->counter_val[3] = THRESHOLD_3_G(ingress_rx_threshold);
1435 1437
1436 csio_init_intr_coalesce_parms(hw); 1438 csio_init_intr_coalesce_parms(hw);
1437} 1439}
@@ -1454,9 +1456,9 @@ csio_wr_set_sge(struct csio_hw *hw)
1454 * Set up our basic SGE mode to deliver CPL messages to our Ingress 1456 * Set up our basic SGE mode to deliver CPL messages to our Ingress
1455 * Queue and Packet Date to the Free List. 1457 * Queue and Packet Date to the Free List.
1456 */ 1458 */
1457 csio_set_reg_field(hw, SGE_CONTROL, RXPKTCPLMODE(1), RXPKTCPLMODE(1)); 1459 csio_set_reg_field(hw, SGE_CONTROL_A, RXPKTCPLMODE_F, RXPKTCPLMODE_F);
1458 1460
1459 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL); 1461 sge->sge_control = csio_rd_reg32(hw, SGE_CONTROL_A);
1460 1462
1461 /* sge->csio_fl_align is set up by csio_wr_fixup_host_params(). */ 1463 /* sge->csio_fl_align is set up by csio_wr_fixup_host_params(). */
1462 1464
@@ -1464,22 +1466,23 @@ csio_wr_set_sge(struct csio_hw *hw)
1464 * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows 1466 * Set up to drop DOORBELL writes when the DOORBELL FIFO overflows
1465 * and generate an interrupt when this occurs so we can recover. 1467 * and generate an interrupt when this occurs so we can recover.
1466 */ 1468 */
1467 csio_set_reg_field(hw, SGE_DBFIFO_STATUS, 1469 csio_set_reg_field(hw, SGE_DBFIFO_STATUS_A,
1468 HP_INT_THRESH(HP_INT_THRESH_MASK) | 1470 LP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
1469 CSIO_HW_LP_INT_THRESH(hw, CSIO_HW_M_LP_INT_THRESH(hw)), 1471 LP_INT_THRESH_T5_V(CSIO_SGE_DBFIFO_INT_THRESH));
1470 HP_INT_THRESH(CSIO_SGE_DBFIFO_INT_THRESH) | 1472 csio_set_reg_field(hw, SGE_DBFIFO_STATUS2_A,
1471 CSIO_HW_LP_INT_THRESH(hw, CSIO_SGE_DBFIFO_INT_THRESH)); 1473 HP_INT_THRESH_T5_V(LP_INT_THRESH_T5_M),
1474 HP_INT_THRESH_T5_V(CSIO_SGE_DBFIFO_INT_THRESH));
1472 1475
1473 csio_set_reg_field(hw, SGE_DOORBELL_CONTROL, ENABLE_DROP, 1476 csio_set_reg_field(hw, SGE_DOORBELL_CONTROL_A, ENABLE_DROP_F,
1474 ENABLE_DROP); 1477 ENABLE_DROP_F);
1475 1478
1476 /* SGE_FL_BUFFER_SIZE0 is set up by csio_wr_fixup_host_params(). */ 1479 /* SGE_FL_BUFFER_SIZE0 is set up by csio_wr_fixup_host_params(). */
1477 1480
1478 CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1); 1481 CSIO_SET_FLBUF_SIZE(hw, 1, CSIO_SGE_FLBUF_SIZE1);
1479 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE2 + sge->csio_fl_align - 1) 1482 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE2 + sge->csio_fl_align - 1)
1480 & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE2); 1483 & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE2_A);
1481 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE3 + sge->csio_fl_align - 1) 1484 csio_wr_reg32(hw, (CSIO_SGE_FLBUF_SIZE3 + sge->csio_fl_align - 1)
1482 & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE3); 1485 & ~(sge->csio_fl_align - 1), SGE_FL_BUFFER_SIZE3_A);
1483 CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4); 1486 CSIO_SET_FLBUF_SIZE(hw, 4, CSIO_SGE_FLBUF_SIZE4);
1484 CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5); 1487 CSIO_SET_FLBUF_SIZE(hw, 5, CSIO_SGE_FLBUF_SIZE5);
1485 CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6); 1488 CSIO_SET_FLBUF_SIZE(hw, 6, CSIO_SGE_FLBUF_SIZE6);
@@ -1502,26 +1505,26 @@ csio_wr_set_sge(struct csio_hw *hw)
1502 sge->counter_val[2] = CSIO_SGE_INT_CNT_VAL_2; 1505 sge->counter_val[2] = CSIO_SGE_INT_CNT_VAL_2;
1503 sge->counter_val[3] = CSIO_SGE_INT_CNT_VAL_3; 1506 sge->counter_val[3] = CSIO_SGE_INT_CNT_VAL_3;
1504 1507
1505 csio_wr_reg32(hw, THRESHOLD_0(sge->counter_val[0]) | 1508 csio_wr_reg32(hw, THRESHOLD_0_V(sge->counter_val[0]) |
1506 THRESHOLD_1(sge->counter_val[1]) | 1509 THRESHOLD_1_V(sge->counter_val[1]) |
1507 THRESHOLD_2(sge->counter_val[2]) | 1510 THRESHOLD_2_V(sge->counter_val[2]) |
1508 THRESHOLD_3(sge->counter_val[3]), 1511 THRESHOLD_3_V(sge->counter_val[3]),
1509 SGE_INGRESS_RX_THRESHOLD); 1512 SGE_INGRESS_RX_THRESHOLD_A);
1510 1513
1511 csio_wr_reg32(hw, 1514 csio_wr_reg32(hw,
1512 TIMERVALUE0(csio_us_to_core_ticks(hw, sge->timer_val[0])) | 1515 TIMERVALUE0_V(csio_us_to_core_ticks(hw, sge->timer_val[0])) |
1513 TIMERVALUE1(csio_us_to_core_ticks(hw, sge->timer_val[1])), 1516 TIMERVALUE1_V(csio_us_to_core_ticks(hw, sge->timer_val[1])),
1514 SGE_TIMER_VALUE_0_AND_1); 1517 SGE_TIMER_VALUE_0_AND_1_A);
1515 1518
1516 csio_wr_reg32(hw, 1519 csio_wr_reg32(hw,
1517 TIMERVALUE2(csio_us_to_core_ticks(hw, sge->timer_val[2])) | 1520 TIMERVALUE2_V(csio_us_to_core_ticks(hw, sge->timer_val[2])) |
1518 TIMERVALUE3(csio_us_to_core_ticks(hw, sge->timer_val[3])), 1521 TIMERVALUE3_V(csio_us_to_core_ticks(hw, sge->timer_val[3])),
1519 SGE_TIMER_VALUE_2_AND_3); 1522 SGE_TIMER_VALUE_2_AND_3_A);
1520 1523
1521 csio_wr_reg32(hw, 1524 csio_wr_reg32(hw,
1522 TIMERVALUE4(csio_us_to_core_ticks(hw, sge->timer_val[4])) | 1525 TIMERVALUE4_V(csio_us_to_core_ticks(hw, sge->timer_val[4])) |
1523 TIMERVALUE5(csio_us_to_core_ticks(hw, sge->timer_val[5])), 1526 TIMERVALUE5_V(csio_us_to_core_ticks(hw, sge->timer_val[5])),
1524 SGE_TIMER_VALUE_4_AND_5); 1527 SGE_TIMER_VALUE_4_AND_5_A);
1525 1528
1526 csio_init_intr_coalesce_parms(hw); 1529 csio_init_intr_coalesce_parms(hw);
1527} 1530}
diff --git a/drivers/scsi/cxgbi/cxgb4i/cxgb4i.c b/drivers/scsi/cxgbi/cxgb4i/cxgb4i.c
index a83d2ceded83..dd00e5fe4a5e 100644
--- a/drivers/scsi/cxgbi/cxgb4i/cxgb4i.c
+++ b/drivers/scsi/cxgbi/cxgb4i/cxgb4i.c
@@ -28,6 +28,7 @@
28#include "t4fw_api.h" 28#include "t4fw_api.h"
29#include "l2t.h" 29#include "l2t.h"
30#include "cxgb4i.h" 30#include "cxgb4i.h"
31#include "clip_tbl.h"
31 32
32static unsigned int dbg_level; 33static unsigned int dbg_level;
33 34
@@ -704,7 +705,7 @@ static void do_act_establish(struct cxgbi_device *cdev, struct sk_buff *skb)
704 struct cpl_act_establish *req = (struct cpl_act_establish *)skb->data; 705 struct cpl_act_establish *req = (struct cpl_act_establish *)skb->data;
705 unsigned short tcp_opt = ntohs(req->tcp_opt); 706 unsigned short tcp_opt = ntohs(req->tcp_opt);
706 unsigned int tid = GET_TID(req); 707 unsigned int tid = GET_TID(req);
707 unsigned int atid = GET_TID_TID(ntohl(req->tos_atid)); 708 unsigned int atid = TID_TID_G(ntohl(req->tos_atid));
708 struct cxgb4_lld_info *lldi = cxgbi_cdev_priv(cdev); 709 struct cxgb4_lld_info *lldi = cxgbi_cdev_priv(cdev);
709 struct tid_info *t = lldi->tids; 710 struct tid_info *t = lldi->tids;
710 u32 rcv_isn = be32_to_cpu(req->rcv_isn); 711 u32 rcv_isn = be32_to_cpu(req->rcv_isn);
@@ -752,15 +753,15 @@ static void do_act_establish(struct cxgbi_device *cdev, struct sk_buff *skb)
752 if (cxgb4i_rcv_win > (RCV_BUFSIZ_MASK << 10)) 753 if (cxgb4i_rcv_win > (RCV_BUFSIZ_MASK << 10))
753 csk->rcv_wup -= cxgb4i_rcv_win - (RCV_BUFSIZ_MASK << 10); 754 csk->rcv_wup -= cxgb4i_rcv_win - (RCV_BUFSIZ_MASK << 10);
754 755
755 csk->advmss = lldi->mtus[GET_TCPOPT_MSS(tcp_opt)] - 40; 756 csk->advmss = lldi->mtus[TCPOPT_MSS_G(tcp_opt)] - 40;
756 if (GET_TCPOPT_TSTAMP(tcp_opt)) 757 if (TCPOPT_TSTAMP_G(tcp_opt))
757 csk->advmss -= 12; 758 csk->advmss -= 12;
758 if (csk->advmss < 128) 759 if (csk->advmss < 128)
759 csk->advmss = 128; 760 csk->advmss = 128;
760 761
761 log_debug(1 << CXGBI_DBG_TOE | 1 << CXGBI_DBG_SOCK, 762 log_debug(1 << CXGBI_DBG_TOE | 1 << CXGBI_DBG_SOCK,
762 "csk 0x%p, mss_idx %u, advmss %u.\n", 763 "csk 0x%p, mss_idx %u, advmss %u.\n",
763 csk, GET_TCPOPT_MSS(tcp_opt), csk->advmss); 764 csk, TCPOPT_MSS_G(tcp_opt), csk->advmss);
764 765
765 cxgbi_sock_established(csk, ntohl(req->snd_isn), ntohs(req->tcp_opt)); 766 cxgbi_sock_established(csk, ntohl(req->snd_isn), ntohs(req->tcp_opt));
766 767
@@ -856,8 +857,8 @@ static void do_act_open_rpl(struct cxgbi_device *cdev, struct sk_buff *skb)
856 struct cpl_act_open_rpl *rpl = (struct cpl_act_open_rpl *)skb->data; 857 struct cpl_act_open_rpl *rpl = (struct cpl_act_open_rpl *)skb->data;
857 unsigned int tid = GET_TID(rpl); 858 unsigned int tid = GET_TID(rpl);
858 unsigned int atid = 859 unsigned int atid =
859 GET_TID_TID(GET_AOPEN_ATID(be32_to_cpu(rpl->atid_status))); 860 TID_TID_G(AOPEN_ATID_G(be32_to_cpu(rpl->atid_status)));
860 unsigned int status = GET_AOPEN_STATUS(be32_to_cpu(rpl->atid_status)); 861 unsigned int status = AOPEN_STATUS_G(be32_to_cpu(rpl->atid_status));
861 struct cxgb4_lld_info *lldi = cxgbi_cdev_priv(cdev); 862 struct cxgb4_lld_info *lldi = cxgbi_cdev_priv(cdev);
862 struct tid_info *t = lldi->tids; 863 struct tid_info *t = lldi->tids;
863 864
@@ -1112,7 +1113,7 @@ static void do_rx_iscsi_hdr(struct cxgbi_device *cdev, struct sk_buff *skb)
1112 hlen = ntohs(cpl->len); 1113 hlen = ntohs(cpl->len);
1113 dlen = ntohl(*(unsigned int *)(bhs + 4)) & 0xFFFFFF; 1114 dlen = ntohl(*(unsigned int *)(bhs + 4)) & 0xFFFFFF;
1114 1115
1115 plen = ISCSI_PDU_LEN(pdu_len_ddp); 1116 plen = ISCSI_PDU_LEN_G(pdu_len_ddp);
1116 if (is_t4(lldi->adapter_type)) 1117 if (is_t4(lldi->adapter_type))
1117 plen -= 40; 1118 plen -= 40;
1118 1119
@@ -1322,6 +1323,9 @@ static inline void l2t_put(struct cxgbi_sock *csk)
1322static void release_offload_resources(struct cxgbi_sock *csk) 1323static void release_offload_resources(struct cxgbi_sock *csk)
1323{ 1324{
1324 struct cxgb4_lld_info *lldi; 1325 struct cxgb4_lld_info *lldi;
1326#if IS_ENABLED(CONFIG_IPV6)
1327 struct net_device *ndev = csk->cdev->ports[csk->port_id];
1328#endif
1325 1329
1326 log_debug(1 << CXGBI_DBG_TOE | 1 << CXGBI_DBG_SOCK, 1330 log_debug(1 << CXGBI_DBG_TOE | 1 << CXGBI_DBG_SOCK,
1327 "csk 0x%p,%u,0x%lx,%u.\n", 1331 "csk 0x%p,%u,0x%lx,%u.\n",
@@ -1334,6 +1338,12 @@ static void release_offload_resources(struct cxgbi_sock *csk)
1334 } 1338 }
1335 1339
1336 l2t_put(csk); 1340 l2t_put(csk);
1341#if IS_ENABLED(CONFIG_IPV6)
1342 if (csk->csk_family == AF_INET6)
1343 cxgb4_clip_release(ndev,
1344 (const u32 *)&csk->saddr6.sin6_addr, 1);
1345#endif
1346
1337 if (cxgbi_sock_flag(csk, CTPF_HAS_ATID)) 1347 if (cxgbi_sock_flag(csk, CTPF_HAS_ATID))
1338 free_atid(csk); 1348 free_atid(csk);
1339 else if (cxgbi_sock_flag(csk, CTPF_HAS_TID)) { 1349 else if (cxgbi_sock_flag(csk, CTPF_HAS_TID)) {
@@ -1391,10 +1401,15 @@ static int init_act_open(struct cxgbi_sock *csk)
1391 csk->l2t = cxgb4_l2t_get(lldi->l2t, n, ndev, 0); 1401 csk->l2t = cxgb4_l2t_get(lldi->l2t, n, ndev, 0);
1392 if (!csk->l2t) { 1402 if (!csk->l2t) {
1393 pr_err("%s, cannot alloc l2t.\n", ndev->name); 1403 pr_err("%s, cannot alloc l2t.\n", ndev->name);
1394 goto rel_resource; 1404 goto rel_resource_without_clip;
1395 } 1405 }
1396 cxgbi_sock_get(csk); 1406 cxgbi_sock_get(csk);
1397 1407
1408#if IS_ENABLED(CONFIG_IPV6)
1409 if (csk->csk_family == AF_INET6)
1410 cxgb4_clip_get(ndev, (const u32 *)&csk->saddr6.sin6_addr, 1);
1411#endif
1412
1398 if (t4) { 1413 if (t4) {
1399 size = sizeof(struct cpl_act_open_req); 1414 size = sizeof(struct cpl_act_open_req);
1400 size6 = sizeof(struct cpl_act_open_req6); 1415 size6 = sizeof(struct cpl_act_open_req6);
@@ -1451,6 +1466,12 @@ static int init_act_open(struct cxgbi_sock *csk)
1451 return 0; 1466 return 0;
1452 1467
1453rel_resource: 1468rel_resource:
1469#if IS_ENABLED(CONFIG_IPV6)
1470 if (csk->csk_family == AF_INET6)
1471 cxgb4_clip_release(ndev,
1472 (const u32 *)&csk->saddr6.sin6_addr, 1);
1473#endif
1474rel_resource_without_clip:
1454 if (n) 1475 if (n)
1455 neigh_release(n); 1476 neigh_release(n);
1456 if (skb) 1477 if (skb)
@@ -1619,7 +1640,7 @@ static int ddp_setup_conn_pgidx(struct cxgbi_sock *csk, unsigned int tid,
1619 req = (struct cpl_set_tcb_field *)skb->head; 1640 req = (struct cpl_set_tcb_field *)skb->head;
1620 INIT_TP_WR(req, csk->tid); 1641 INIT_TP_WR(req, csk->tid);
1621 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, csk->tid)); 1642 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, csk->tid));
1622 req->reply_ctrl = htons(NO_REPLY(reply) | QUEUENO(csk->rss_qid)); 1643 req->reply_ctrl = htons(NO_REPLY_V(reply) | QUEUENO_V(csk->rss_qid));
1623 req->word_cookie = htons(0); 1644 req->word_cookie = htons(0);
1624 req->mask = cpu_to_be64(0x3 << 8); 1645 req->mask = cpu_to_be64(0x3 << 8);
1625 req->val = cpu_to_be64(pg_idx << 8); 1646 req->val = cpu_to_be64(pg_idx << 8);
@@ -1651,7 +1672,7 @@ static int ddp_setup_conn_digest(struct cxgbi_sock *csk, unsigned int tid,
1651 req = (struct cpl_set_tcb_field *)skb->head; 1672 req = (struct cpl_set_tcb_field *)skb->head;
1652 INIT_TP_WR(req, tid); 1673 INIT_TP_WR(req, tid);
1653 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid)); 1674 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, tid));
1654 req->reply_ctrl = htons(NO_REPLY(reply) | QUEUENO(csk->rss_qid)); 1675 req->reply_ctrl = htons(NO_REPLY_V(reply) | QUEUENO_V(csk->rss_qid));
1655 req->word_cookie = htons(0); 1676 req->word_cookie = htons(0);
1656 req->mask = cpu_to_be64(0x3 << 4); 1677 req->mask = cpu_to_be64(0x3 << 4);
1657 req->val = cpu_to_be64(((hcrc ? ULP_CRC_HEADER : 0) | 1678 req->val = cpu_to_be64(((hcrc ? ULP_CRC_HEADER : 0) |
diff --git a/drivers/scsi/device_handler/scsi_dh.c b/drivers/scsi/device_handler/scsi_dh.c
index 1dba62c5cf6a..1efebc9eedfb 100644
--- a/drivers/scsi/device_handler/scsi_dh.c
+++ b/drivers/scsi/device_handler/scsi_dh.c
@@ -136,11 +136,12 @@ static void __detach_handler (struct kref *kref)
136 struct scsi_device_handler *scsi_dh = scsi_dh_data->scsi_dh; 136 struct scsi_device_handler *scsi_dh = scsi_dh_data->scsi_dh;
137 struct scsi_device *sdev = scsi_dh_data->sdev; 137 struct scsi_device *sdev = scsi_dh_data->sdev;
138 138
139 scsi_dh->detach(sdev);
140
139 spin_lock_irq(sdev->request_queue->queue_lock); 141 spin_lock_irq(sdev->request_queue->queue_lock);
140 sdev->scsi_dh_data = NULL; 142 sdev->scsi_dh_data = NULL;
141 spin_unlock_irq(sdev->request_queue->queue_lock); 143 spin_unlock_irq(sdev->request_queue->queue_lock);
142 144
143 scsi_dh->detach(sdev);
144 sdev_printk(KERN_NOTICE, sdev, "%s: Detached\n", scsi_dh->name); 145 sdev_printk(KERN_NOTICE, sdev, "%s: Detached\n", scsi_dh->name);
145 module_put(scsi_dh->module); 146 module_put(scsi_dh->module);
146} 147}
diff --git a/drivers/scsi/esas2r/esas2r_init.c b/drivers/scsi/esas2r/esas2r_init.c
index 6776931e25d4..78ce4d61a69b 100644
--- a/drivers/scsi/esas2r/esas2r_init.c
+++ b/drivers/scsi/esas2r/esas2r_init.c
@@ -813,12 +813,13 @@ static void esas2r_init_pci_cfg_space(struct esas2r_adapter *a)
813 pci_read_config_word(a->pcid, pcie_cap_reg + PCI_EXP_DEVCTL, 813 pci_read_config_word(a->pcid, pcie_cap_reg + PCI_EXP_DEVCTL,
814 &devcontrol); 814 &devcontrol);
815 815
816 if ((devcontrol & PCI_EXP_DEVCTL_READRQ) > 0x2000) { 816 if ((devcontrol & PCI_EXP_DEVCTL_READRQ) >
817 PCI_EXP_DEVCTL_READRQ_512B) {
817 esas2r_log(ESAS2R_LOG_INFO, 818 esas2r_log(ESAS2R_LOG_INFO,
818 "max read request size > 512B"); 819 "max read request size > 512B");
819 820
820 devcontrol &= ~PCI_EXP_DEVCTL_READRQ; 821 devcontrol &= ~PCI_EXP_DEVCTL_READRQ;
821 devcontrol |= 0x2000; 822 devcontrol |= PCI_EXP_DEVCTL_READRQ_512B;
822 pci_write_config_word(a->pcid, 823 pci_write_config_word(a->pcid,
823 pcie_cap_reg + PCI_EXP_DEVCTL, 824 pcie_cap_reg + PCI_EXP_DEVCTL,
824 devcontrol); 825 devcontrol);
diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c
index df4e27cd996a..9219953ee949 100644
--- a/drivers/scsi/ipr.c
+++ b/drivers/scsi/ipr.c
@@ -683,6 +683,7 @@ static void ipr_init_ipr_cmnd(struct ipr_cmnd *ipr_cmd,
683 ipr_reinit_ipr_cmnd(ipr_cmd); 683 ipr_reinit_ipr_cmnd(ipr_cmd);
684 ipr_cmd->u.scratch = 0; 684 ipr_cmd->u.scratch = 0;
685 ipr_cmd->sibling = NULL; 685 ipr_cmd->sibling = NULL;
686 ipr_cmd->eh_comp = NULL;
686 ipr_cmd->fast_done = fast_done; 687 ipr_cmd->fast_done = fast_done;
687 init_timer(&ipr_cmd->timer); 688 init_timer(&ipr_cmd->timer);
688} 689}
@@ -848,6 +849,8 @@ static void ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
848 849
849 scsi_dma_unmap(ipr_cmd->scsi_cmd); 850 scsi_dma_unmap(ipr_cmd->scsi_cmd);
850 scsi_cmd->scsi_done(scsi_cmd); 851 scsi_cmd->scsi_done(scsi_cmd);
852 if (ipr_cmd->eh_comp)
853 complete(ipr_cmd->eh_comp);
851 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q); 854 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
852} 855}
853 856
@@ -4811,6 +4814,84 @@ static int ipr_slave_alloc(struct scsi_device *sdev)
4811 return rc; 4814 return rc;
4812} 4815}
4813 4816
4817/**
4818 * ipr_match_lun - Match function for specified LUN
4819 * @ipr_cmd: ipr command struct
4820 * @device: device to match (sdev)
4821 *
4822 * Returns:
4823 * 1 if command matches sdev / 0 if command does not match sdev
4824 **/
4825static int ipr_match_lun(struct ipr_cmnd *ipr_cmd, void *device)
4826{
4827 if (ipr_cmd->scsi_cmd && ipr_cmd->scsi_cmd->device == device)
4828 return 1;
4829 return 0;
4830}
4831
4832/**
4833 * ipr_wait_for_ops - Wait for matching commands to complete
4834 * @ipr_cmd: ipr command struct
4835 * @device: device to match (sdev)
4836 * @match: match function to use
4837 *
4838 * Returns:
4839 * SUCCESS / FAILED
4840 **/
4841static int ipr_wait_for_ops(struct ipr_ioa_cfg *ioa_cfg, void *device,
4842 int (*match)(struct ipr_cmnd *, void *))
4843{
4844 struct ipr_cmnd *ipr_cmd;
4845 int wait;
4846 unsigned long flags;
4847 struct ipr_hrr_queue *hrrq;
4848 signed long timeout = IPR_ABORT_TASK_TIMEOUT;
4849 DECLARE_COMPLETION_ONSTACK(comp);
4850
4851 ENTER;
4852 do {
4853 wait = 0;
4854
4855 for_each_hrrq(hrrq, ioa_cfg) {
4856 spin_lock_irqsave(hrrq->lock, flags);
4857 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
4858 if (match(ipr_cmd, device)) {
4859 ipr_cmd->eh_comp = &comp;
4860 wait++;
4861 }
4862 }
4863 spin_unlock_irqrestore(hrrq->lock, flags);
4864 }
4865
4866 if (wait) {
4867 timeout = wait_for_completion_timeout(&comp, timeout);
4868
4869 if (!timeout) {
4870 wait = 0;
4871
4872 for_each_hrrq(hrrq, ioa_cfg) {
4873 spin_lock_irqsave(hrrq->lock, flags);
4874 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
4875 if (match(ipr_cmd, device)) {
4876 ipr_cmd->eh_comp = NULL;
4877 wait++;
4878 }
4879 }
4880 spin_unlock_irqrestore(hrrq->lock, flags);
4881 }
4882
4883 if (wait)
4884 dev_err(&ioa_cfg->pdev->dev, "Timed out waiting for aborted commands\n");
4885 LEAVE;
4886 return wait ? FAILED : SUCCESS;
4887 }
4888 }
4889 } while (wait);
4890
4891 LEAVE;
4892 return SUCCESS;
4893}
4894
4814static int ipr_eh_host_reset(struct scsi_cmnd *cmd) 4895static int ipr_eh_host_reset(struct scsi_cmnd *cmd)
4815{ 4896{
4816 struct ipr_ioa_cfg *ioa_cfg; 4897 struct ipr_ioa_cfg *ioa_cfg;
@@ -5030,11 +5111,17 @@ static int __ipr_eh_dev_reset(struct scsi_cmnd *scsi_cmd)
5030static int ipr_eh_dev_reset(struct scsi_cmnd *cmd) 5111static int ipr_eh_dev_reset(struct scsi_cmnd *cmd)
5031{ 5112{
5032 int rc; 5113 int rc;
5114 struct ipr_ioa_cfg *ioa_cfg;
5115
5116 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
5033 5117
5034 spin_lock_irq(cmd->device->host->host_lock); 5118 spin_lock_irq(cmd->device->host->host_lock);
5035 rc = __ipr_eh_dev_reset(cmd); 5119 rc = __ipr_eh_dev_reset(cmd);
5036 spin_unlock_irq(cmd->device->host->host_lock); 5120 spin_unlock_irq(cmd->device->host->host_lock);
5037 5121
5122 if (rc == SUCCESS)
5123 rc = ipr_wait_for_ops(ioa_cfg, cmd->device, ipr_match_lun);
5124
5038 return rc; 5125 return rc;
5039} 5126}
5040 5127
@@ -5234,13 +5321,18 @@ static int ipr_eh_abort(struct scsi_cmnd *scsi_cmd)
5234{ 5321{
5235 unsigned long flags; 5322 unsigned long flags;
5236 int rc; 5323 int rc;
5324 struct ipr_ioa_cfg *ioa_cfg;
5237 5325
5238 ENTER; 5326 ENTER;
5239 5327
5328 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
5329
5240 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags); 5330 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
5241 rc = ipr_cancel_op(scsi_cmd); 5331 rc = ipr_cancel_op(scsi_cmd);
5242 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags); 5332 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
5243 5333
5334 if (rc == SUCCESS)
5335 rc = ipr_wait_for_ops(ioa_cfg, scsi_cmd->device, ipr_match_lun);
5244 LEAVE; 5336 LEAVE;
5245 return rc; 5337 return rc;
5246} 5338}
diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h
index b4f3eec51bc9..ec03b42fa2b9 100644
--- a/drivers/scsi/ipr.h
+++ b/drivers/scsi/ipr.h
@@ -1606,6 +1606,7 @@ struct ipr_cmnd {
1606 struct scsi_device *sdev; 1606 struct scsi_device *sdev;
1607 } u; 1607 } u;
1608 1608
1609 struct completion *eh_comp;
1609 struct ipr_hrr_queue *hrrq; 1610 struct ipr_hrr_queue *hrrq;
1610 struct ipr_ioa_cfg *ioa_cfg; 1611 struct ipr_ioa_cfg *ioa_cfg;
1611}; 1612};
diff --git a/drivers/scsi/pmcraid.c b/drivers/scsi/pmcraid.c
index 8c27b6a77ec4..ed31d8cc6266 100644
--- a/drivers/scsi/pmcraid.c
+++ b/drivers/scsi/pmcraid.c
@@ -1473,13 +1473,7 @@ static int pmcraid_notify_aen(
1473 } 1473 }
1474 1474
1475 /* send genetlink multicast message to notify appplications */ 1475 /* send genetlink multicast message to notify appplications */
1476 result = genlmsg_end(skb, msg_header); 1476 genlmsg_end(skb, msg_header);
1477
1478 if (result < 0) {
1479 pmcraid_err("genlmsg_end failed\n");
1480 nlmsg_free(skb);
1481 return result;
1482 }
1483 1477
1484 result = genlmsg_multicast(&pmcraid_event_family, skb, 1478 result = genlmsg_multicast(&pmcraid_event_family, skb,
1485 0, 0, GFP_ATOMIC); 1479 0, 0, GFP_ATOMIC);
@@ -4223,7 +4217,7 @@ static ssize_t pmcraid_show_adapter_id(
4223static struct device_attribute pmcraid_adapter_id_attr = { 4217static struct device_attribute pmcraid_adapter_id_attr = {
4224 .attr = { 4218 .attr = {
4225 .name = "adapter_id", 4219 .name = "adapter_id",
4226 .mode = S_IRUGO | S_IWUSR, 4220 .mode = S_IRUGO,
4227 }, 4221 },
4228 .show = pmcraid_show_adapter_id, 4222 .show = pmcraid_show_adapter_id,
4229}; 4223};
diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c
index 73f9feecda72..99f43b7fc9ab 100644
--- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c
+++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c
@@ -1570,9 +1570,7 @@ static int tcm_qla2xxx_check_initiator_node_acl(
1570 * match the format by tcm_qla2xxx explict ConfigFS NodeACLs. 1570 * match the format by tcm_qla2xxx explict ConfigFS NodeACLs.
1571 */ 1571 */
1572 memset(&port_name, 0, 36); 1572 memset(&port_name, 0, 36);
1573 snprintf(port_name, 36, "%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x", 1573 snprintf(port_name, sizeof(port_name), "%8phC", fc_wwpn);
1574 fc_wwpn[0], fc_wwpn[1], fc_wwpn[2], fc_wwpn[3], fc_wwpn[4],
1575 fc_wwpn[5], fc_wwpn[6], fc_wwpn[7]);
1576 /* 1574 /*
1577 * Locate our struct se_node_acl either from an explict NodeACL created 1575 * Locate our struct se_node_acl either from an explict NodeACL created
1578 * via ConfigFS, or via running in TPG demo mode. 1576 * via ConfigFS, or via running in TPG demo mode.
diff --git a/drivers/scsi/scsi.c b/drivers/scsi/scsi.c
index 08c90a711556..c9c3b579eece 100644
--- a/drivers/scsi/scsi.c
+++ b/drivers/scsi/scsi.c
@@ -979,9 +979,9 @@ int scsi_device_get(struct scsi_device *sdev)
979 return -ENXIO; 979 return -ENXIO;
980 if (!get_device(&sdev->sdev_gendev)) 980 if (!get_device(&sdev->sdev_gendev))
981 return -ENXIO; 981 return -ENXIO;
982 /* We can fail this if we're doing SCSI operations 982 /* We can fail try_module_get if we're doing SCSI operations
983 * from module exit (like cache flush) */ 983 * from module exit (like cache flush) */
984 try_module_get(sdev->host->hostt->module); 984 __module_get(sdev->host->hostt->module);
985 985
986 return 0; 986 return 0;
987} 987}
@@ -997,14 +997,7 @@ EXPORT_SYMBOL(scsi_device_get);
997 */ 997 */
998void scsi_device_put(struct scsi_device *sdev) 998void scsi_device_put(struct scsi_device *sdev)
999{ 999{
1000#ifdef CONFIG_MODULE_UNLOAD 1000 module_put(sdev->host->hostt->module);
1001 struct module *module = sdev->host->hostt->module;
1002
1003 /* The module refcount will be zero if scsi_device_get()
1004 * was called from a module removal routine */
1005 if (module && module_refcount(module) != 0)
1006 module_put(module);
1007#endif
1008 put_device(&sdev->sdev_gendev); 1001 put_device(&sdev->sdev_gendev);
1009} 1002}
1010EXPORT_SYMBOL(scsi_device_put); 1003EXPORT_SYMBOL(scsi_device_put);
diff --git a/drivers/scsi/scsi_debug.c b/drivers/scsi/scsi_debug.c
index 8bcf6ad0d765..1f8e2dc9c616 100644
--- a/drivers/scsi/scsi_debug.c
+++ b/drivers/scsi/scsi_debug.c
@@ -1678,7 +1678,7 @@ resp_rsup_opcodes(struct scsi_cmnd *scp, struct sdebug_dev_info *devip)
1678 req_opcode = cmd[3]; 1678 req_opcode = cmd[3];
1679 req_sa = get_unaligned_be16(cmd + 4); 1679 req_sa = get_unaligned_be16(cmd + 4);
1680 alloc_len = get_unaligned_be32(cmd + 6); 1680 alloc_len = get_unaligned_be32(cmd + 6);
1681 if (alloc_len < 4 && alloc_len > 0xffff) { 1681 if (alloc_len < 4 || alloc_len > 0xffff) {
1682 mk_sense_invalid_fld(scp, SDEB_IN_CDB, 6, -1); 1682 mk_sense_invalid_fld(scp, SDEB_IN_CDB, 6, -1);
1683 return check_condition_result; 1683 return check_condition_result;
1684 } 1684 }
@@ -1686,7 +1686,7 @@ resp_rsup_opcodes(struct scsi_cmnd *scp, struct sdebug_dev_info *devip)
1686 a_len = 8192; 1686 a_len = 8192;
1687 else 1687 else
1688 a_len = alloc_len; 1688 a_len = alloc_len;
1689 arr = kzalloc((a_len < 256) ? 320 : a_len + 64, GFP_KERNEL); 1689 arr = kzalloc((a_len < 256) ? 320 : a_len + 64, GFP_ATOMIC);
1690 if (NULL == arr) { 1690 if (NULL == arr) {
1691 mk_sense_buffer(scp, ILLEGAL_REQUEST, INSUFF_RES_ASC, 1691 mk_sense_buffer(scp, ILLEGAL_REQUEST, INSUFF_RES_ASC,
1692 INSUFF_RES_ASCQ); 1692 INSUFF_RES_ASCQ);
@@ -4658,10 +4658,10 @@ static ssize_t map_show(struct device_driver *ddp, char *buf)
4658 return scnprintf(buf, PAGE_SIZE, "0-%u\n", 4658 return scnprintf(buf, PAGE_SIZE, "0-%u\n",
4659 sdebug_store_sectors); 4659 sdebug_store_sectors);
4660 4660
4661 count = bitmap_scnlistprintf(buf, PAGE_SIZE, map_storep, map_size); 4661 count = scnprintf(buf, PAGE_SIZE - 1, "%*pbl",
4662 4662 (int)map_size, map_storep);
4663 buf[count++] = '\n'; 4663 buf[count++] = '\n';
4664 buf[count++] = 0; 4664 buf[count] = '\0';
4665 4665
4666 return count; 4666 return count;
4667} 4667}
diff --git a/drivers/scsi/scsi_lib.c b/drivers/scsi/scsi_lib.c
index 6d5c0b8cb0bb..54d7a6cbb98a 100644
--- a/drivers/scsi/scsi_lib.c
+++ b/drivers/scsi/scsi_lib.c
@@ -1143,7 +1143,17 @@ int scsi_init_io(struct scsi_cmnd *cmd)
1143 struct scsi_data_buffer *prot_sdb = cmd->prot_sdb; 1143 struct scsi_data_buffer *prot_sdb = cmd->prot_sdb;
1144 int ivecs, count; 1144 int ivecs, count;
1145 1145
1146 BUG_ON(prot_sdb == NULL); 1146 if (prot_sdb == NULL) {
1147 /*
1148 * This can happen if someone (e.g. multipath)
1149 * queues a command to a device on an adapter
1150 * that does not support DIX.
1151 */
1152 WARN_ON_ONCE(1);
1153 error = BLKPREP_KILL;
1154 goto err_exit;
1155 }
1156
1147 ivecs = blk_rq_count_integrity_sg(rq->q, rq->bio); 1157 ivecs = blk_rq_count_integrity_sg(rq->q, rq->bio);
1148 1158
1149 if (scsi_alloc_sgtable(prot_sdb, ivecs, is_mq)) { 1159 if (scsi_alloc_sgtable(prot_sdb, ivecs, is_mq)) {
@@ -2187,6 +2197,8 @@ int scsi_mq_setup_tags(struct Scsi_Host *shost)
2187 shost->tag_set.cmd_size = cmd_size; 2197 shost->tag_set.cmd_size = cmd_size;
2188 shost->tag_set.numa_node = NUMA_NO_NODE; 2198 shost->tag_set.numa_node = NUMA_NO_NODE;
2189 shost->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_SG_MERGE; 2199 shost->tag_set.flags = BLK_MQ_F_SHOULD_MERGE | BLK_MQ_F_SG_MERGE;
2200 shost->tag_set.flags |=
2201 BLK_ALLOC_POLICY_TO_MQ_FLAG(shost->hostt->tag_alloc_policy);
2190 shost->tag_set.driver_data = shost; 2202 shost->tag_set.driver_data = shost;
2191 2203
2192 return blk_mq_alloc_tag_set(&shost->tag_set); 2204 return blk_mq_alloc_tag_set(&shost->tag_set);
diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c
index 0deb385ad4d6..9c0a520d933c 100644
--- a/drivers/scsi/scsi_scan.c
+++ b/drivers/scsi/scsi_scan.c
@@ -277,7 +277,8 @@ static struct scsi_device *scsi_alloc_sdev(struct scsi_target *starget,
277 if (!shost_use_blk_mq(sdev->host) && 277 if (!shost_use_blk_mq(sdev->host) &&
278 (shost->bqt || shost->hostt->use_blk_tags)) { 278 (shost->bqt || shost->hostt->use_blk_tags)) {
279 blk_queue_init_tags(sdev->request_queue, 279 blk_queue_init_tags(sdev->request_queue,
280 sdev->host->cmd_per_lun, shost->bqt); 280 sdev->host->cmd_per_lun, shost->bqt,
281 shost->hostt->tag_alloc_policy);
281 } 282 }
282 scsi_change_queue_depth(sdev, sdev->host->cmd_per_lun); 283 scsi_change_queue_depth(sdev, sdev->host->cmd_per_lun);
283 284
diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c
index ebf35cb64216..6b78476d04bb 100644
--- a/drivers/scsi/sd.c
+++ b/drivers/scsi/sd.c
@@ -2800,9 +2800,11 @@ static int sd_revalidate_disk(struct gendisk *disk)
2800 */ 2800 */
2801 sd_set_flush_flag(sdkp); 2801 sd_set_flush_flag(sdkp);
2802 2802
2803 max_xfer = min_not_zero(queue_max_hw_sectors(sdkp->disk->queue), 2803 max_xfer = sdkp->max_xfer_blocks;
2804 sdkp->max_xfer_blocks);
2805 max_xfer <<= ilog2(sdp->sector_size) - 9; 2804 max_xfer <<= ilog2(sdp->sector_size) - 9;
2805
2806 max_xfer = min_not_zero(queue_max_hw_sectors(sdkp->disk->queue),
2807 max_xfer);
2806 blk_queue_max_hw_sectors(sdkp->disk->queue, max_xfer); 2808 blk_queue_max_hw_sectors(sdkp->disk->queue, max_xfer);
2807 set_capacity(disk, sdkp->capacity); 2809 set_capacity(disk, sdkp->capacity);
2808 sd_config_write_same(sdkp); 2810 sd_config_write_same(sdkp);
diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index 5cb2a5e80b2b..2270bd51f9c2 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1745,22 +1745,19 @@ sg_start_req(Sg_request *srp, unsigned char *cmd)
1745 } 1745 }
1746 1746
1747 if (iov_count) { 1747 if (iov_count) {
1748 int len, size = sizeof(struct sg_iovec) * iov_count; 1748 int size = sizeof(struct iovec) * iov_count;
1749 struct iovec *iov; 1749 struct iovec *iov;
1750 struct iov_iter i;
1750 1751
1751 iov = memdup_user(hp->dxferp, size); 1752 iov = memdup_user(hp->dxferp, size);
1752 if (IS_ERR(iov)) 1753 if (IS_ERR(iov))
1753 return PTR_ERR(iov); 1754 return PTR_ERR(iov);
1754 1755
1755 len = iov_length(iov, iov_count); 1756 iov_iter_init(&i, rw, iov, iov_count,
1756 if (hp->dxfer_len < len) { 1757 min_t(size_t, hp->dxfer_len,
1757 iov_count = iov_shorten(iov, iov_count, hp->dxfer_len); 1758 iov_length(iov, iov_count)));
1758 len = hp->dxfer_len;
1759 }
1760 1759
1761 res = blk_rq_map_user_iov(q, rq, md, (struct sg_iovec *)iov, 1760 res = blk_rq_map_user_iov(q, rq, md, &i, GFP_ATOMIC);
1762 iov_count,
1763 len, GFP_ATOMIC);
1764 kfree(iov); 1761 kfree(iov);
1765 } else 1762 } else
1766 res = blk_rq_map_user(q, rq, md, hp->dxferp, 1763 res = blk_rq_map_user(q, rq, md, hp->dxferp,
diff --git a/drivers/scsi/st.c b/drivers/scsi/st.c
index 128d3b55bdd9..9a1c34205254 100644
--- a/drivers/scsi/st.c
+++ b/drivers/scsi/st.c
@@ -4551,18 +4551,15 @@ static int sgl_map_user_pages(struct st_buffer *STbp,
4551 return -ENOMEM; 4551 return -ENOMEM;
4552 4552
4553 /* Try to fault in all of the necessary pages */ 4553 /* Try to fault in all of the necessary pages */
4554 down_read(&current->mm->mmap_sem);
4555 /* rw==READ means read from drive, write into memory area */ 4554 /* rw==READ means read from drive, write into memory area */
4556 res = get_user_pages( 4555 res = get_user_pages_unlocked(
4557 current, 4556 current,
4558 current->mm, 4557 current->mm,
4559 uaddr, 4558 uaddr,
4560 nr_pages, 4559 nr_pages,
4561 rw == READ, 4560 rw == READ,
4562 0, /* don't force */ 4561 0, /* don't force */
4563 pages, 4562 pages);
4564 NULL);
4565 up_read(&current->mm->mmap_sem);
4566 4563
4567 /* Errors and no page mapped should return here */ 4564 /* Errors and no page mapped should return here */
4568 if (res < nr_pages) 4565 if (res < nr_pages)
diff --git a/drivers/scsi/virtio_scsi.c b/drivers/scsi/virtio_scsi.c
index c52bb5dfaedb..f164f24a4a55 100644
--- a/drivers/scsi/virtio_scsi.c
+++ b/drivers/scsi/virtio_scsi.c
@@ -950,6 +950,12 @@ static int virtscsi_probe(struct virtio_device *vdev)
950 u32 num_queues; 950 u32 num_queues;
951 struct scsi_host_template *hostt; 951 struct scsi_host_template *hostt;
952 952
953 if (!vdev->config->get) {
954 dev_err(&vdev->dev, "%s failure: config access disabled\n",
955 __func__);
956 return -EINVAL;
957 }
958
953 /* We need to know how many queues before we allocate. */ 959 /* We need to know how many queues before we allocate. */
954 num_queues = virtscsi_config_get(vdev, num_queues) ? : 1; 960 num_queues = virtscsi_config_get(vdev, num_queues) ? : 1;
955 961
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 17:06:29 -0500