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path: root/drivers/pci/quirks.c
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-rw-r--r--drivers/pci/quirks.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 194b243a2817..9478f7276512 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2143,9 +2143,9 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2143DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2144 quirk_unhide_mch_dev6); 2144 quirk_unhide_mch_dev6);
2145 2145
2146#ifdef CONFIG_TILE 2146#ifdef CONFIG_TILEPRO
2147/* 2147/*
2148 * The Tilera TILEmpower platform needs to set the link speed 2148 * The Tilera TILEmpower tilepro platform needs to set the link speed
2149 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed 2149 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2150 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe 2150 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2151 * capability register of the PEX8624 PCIe switch. The switch 2151 * capability register of the PEX8624 PCIe switch. The switch
@@ -2160,7 +2160,7 @@ static void __devinit quirk_tile_plx_gen1(struct pci_dev *dev)
2160 } 2160 }
2161} 2161}
2162DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1); 2162DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
2163#endif /* CONFIG_TILE */ 2163#endif /* CONFIG_TILEPRO */
2164 2164
2165#ifdef CONFIG_PCI_MSI 2165#ifdef CONFIG_PCI_MSI
2166/* Some chipsets do not support MSI. We cannot easily rely on setting 2166/* Some chipsets do not support MSI. We cannot easily rely on setting