8 files changed, 505 insertions, 74 deletions

diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 9b5d46c03eed..6a17f92153b3 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -71,6 +71,12 @@ config BCM63XX_PHY
         ---help---
           Currently supports the 6348 and 6358 PHYs.
 
+config BCM7XXX_PHY
+        tristate "Drivers for Broadcom 7xxx SOCs internal PHYs"
+        ---help---
+          Currently supports the BCM7366, BCM7439, BCM7445, and
+          40nm and 65nm generation of BCM7xxx Set Top Box SoCs.
+
 config BCM87XX_PHY
         tristate "Driver for Broadcom BCM8706 and BCM8727 PHYs"
         help
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 9013dfa12aa3..07d24024863e 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SMSC_PHY)		+= smsc.o
 obj-$(CONFIG_VITESSE_PHY)       += vitesse.o
 obj-$(CONFIG_BROADCOM_PHY)      += broadcom.o
 obj-$(CONFIG_BCM63XX_PHY)       += bcm63xx.o
+obj-$(CONFIG_BCM7XXX_PHY)       += bcm7xxx.o
 obj-$(CONFIG_BCM87XX_PHY)       += bcm87xx.o
 obj-$(CONFIG_ICPLUS_PHY)        += icplus.o
 obj-$(CONFIG_REALTEK_PHY)       += realtek.o
diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c
new file mode 100644
index 000000000000..697337220016
--- /dev/null
+++ b/drivers/net/phy/bcm7xxx.c
@@ -0,0 +1,343 @@
+/*
+ * Broadcom BCM7xxx internal transceivers support.
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/phy.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/brcmphy.h>
+
+/* Broadcom BCM7xxx internal PHY registers */
+#define MII_BCM7XXX_CHANNEL_WIDTH       0x2000
+
+/* 40nm only register definitions */
+#define MII_BCM7XXX_100TX_AUX_CTL       0x10
+#define MII_BCM7XXX_100TX_FALSE_CAR     0x13
+#define MII_BCM7XXX_100TX_DISC          0x14
+#define MII_BCM7XXX_AUX_MODE            0x1d
+#define  MII_BCM7XX_64CLK_MDIO          BIT(12)
+#define MII_BCM7XXX_CORE_BASE1E         0x1e
+#define MII_BCM7XXX_TEST                0x1f
+#define  MII_BCM7XXX_SHD_MODE_2         BIT(2)
+
+static int bcm7445_config_init(struct phy_device *phydev)
+{
+        int ret;
+        const struct bcm7445_regs {
+                int reg;
+                u16 value;
+        } bcm7445_regs_cfg[] = {
+                /* increases ADC latency by 24ns */
+                { MII_BCM54XX_EXP_SEL, 0x0038 },
+                { MII_BCM54XX_EXP_DATA, 0xAB95 },
+                /* increases internal 1V LDO voltage by 5% */
+                { MII_BCM54XX_EXP_SEL, 0x2038 },
+                { MII_BCM54XX_EXP_DATA, 0xBB22 },
+                /* reduce RX low pass filter corner frequency */
+                { MII_BCM54XX_EXP_SEL, 0x6038 },
+                { MII_BCM54XX_EXP_DATA, 0xFFC5 },
+                /* reduce RX high pass filter corner frequency */
+                { MII_BCM54XX_EXP_SEL, 0x003a },
+                { MII_BCM54XX_EXP_DATA, 0x2002 },
+        };
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(bcm7445_regs_cfg); i++) {
+                ret = phy_write(phydev,
+                                bcm7445_regs_cfg[i].reg,
+                                bcm7445_regs_cfg[i].value);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static void phy_write_exp(struct phy_device *phydev,
+                                        u16 reg, u16 value)
+{
+        phy_write(phydev, MII_BCM54XX_EXP_SEL, MII_BCM54XX_EXP_SEL_ER | reg);
+        phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
+}
+
+static void phy_write_misc(struct phy_device *phydev,
+                                        u16 reg, u16 chl, u16 value)
+{
+        int tmp;
+
+        phy_write(phydev, MII_BCM54XX_AUX_CTL, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
+
+        tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
+        tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
+        phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
+
+        tmp = (chl * MII_BCM7XXX_CHANNEL_WIDTH) | reg;
+        phy_write(phydev, MII_BCM54XX_EXP_SEL, tmp);
+
+        phy_write(phydev, MII_BCM54XX_EXP_DATA, value);
+}
+
+static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
+{
+        /* write AFE_RXCONFIG_0 */
+        phy_write_misc(phydev, 0x38, 0x0000, 0xeb19);
+
+        /* write AFE_RXCONFIG_1 */
+        phy_write_misc(phydev, 0x38, 0x0001, 0x9a3f);
+
+        /* write AFE_RX_LP_COUNTER */
+        phy_write_misc(phydev, 0x38, 0x0003, 0x7fc7);
+
+        /* write AFE_HPF_TRIM_OTHERS */
+        phy_write_misc(phydev, 0x3A, 0x0000, 0x000b);
+
+        /* write AFTE_TX_CONFIG */
+        phy_write_misc(phydev, 0x39, 0x0000, 0x0800);
+
+        /* Increase VCO range to prevent unlocking problem of PLL at low
+         * temp
+         */
+        phy_write_misc(phydev, 0x0032, 0x0001, 0x0048);
+
+        /* Change Ki to 011 */
+        phy_write_misc(phydev, 0x0032, 0x0002, 0x021b);
+
+        /* Disable loading of TVCO buffer to bandgap, set bandgap trim
+         * to 111
+         */
+        phy_write_misc(phydev, 0x0033, 0x0000, 0x0e20);
+
+        /* Adjust bias current trim by -3 */
+        phy_write_misc(phydev, 0x000a, 0x0000, 0x690b);
+
+        /* Switch to CORE_BASE1E */
+        phy_write(phydev, MII_BCM7XXX_CORE_BASE1E, 0xd);
+
+        /* Reset R_CAL/RC_CAL Engine */
+        phy_write_exp(phydev, 0x00b0, 0x0010);
+
+        /* Disable Reset R_CAL/RC_CAL Engine */
+        phy_write_exp(phydev, 0x00b0, 0x0000);
+
+        return 0;
+}
+
+static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
+{
+        int ret;
+
+        ret = bcm7445_config_init(phydev);
+        if (ret)
+                return ret;
+
+        return bcm7xxx_28nm_afe_config_init(phydev);
+}
+
+static int phy_set_clr_bits(struct phy_device *dev, int location,
+                                        int set_mask, int clr_mask)
+{
+        int v, ret;
+
+        v = phy_read(dev, location);
+        if (v < 0)
+                return v;
+
+        v &= ~clr_mask;
+        v |= set_mask;
+
+        ret = phy_write(dev, location, v);
+        if (ret < 0)
+                return ret;
+
+        return v;
+}
+
+static int bcm7xxx_config_init(struct phy_device *phydev)
+{
+        int ret;
+
+        /* Enable 64 clock MDIO */
+        phy_write(phydev, MII_BCM7XXX_AUX_MODE, MII_BCM7XX_64CLK_MDIO);
+        phy_read(phydev, MII_BCM7XXX_AUX_MODE);
+
+        /* Workaround only required for 100Mbits/sec */
+        if (!(phydev->dev_flags & PHY_BRCM_100MBPS_WAR))
+                return 0;
+
+        /* set shadow mode 2 */
+        ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST,
+                        MII_BCM7XXX_SHD_MODE_2, MII_BCM7XXX_SHD_MODE_2);
+        if (ret < 0)
+                return ret;
+
+        /* set iddq_clkbias */
+        phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0F00);
+        udelay(10);
+
+        /* reset iddq_clkbias */
+        phy_write(phydev, MII_BCM7XXX_100TX_DISC, 0x0C00);
+
+        phy_write(phydev, MII_BCM7XXX_100TX_FALSE_CAR, 0x7555);
+
+        /* reset shadow mode 2 */
+        ret = phy_set_clr_bits(phydev, MII_BCM7XXX_TEST, MII_BCM7XXX_SHD_MODE_2, 0);
+        if (ret < 0)
+                return ret;
+
+        return 0;
+}
+
+/* Workaround for putting the PHY in IDDQ mode, required
+ * for all BCM7XXX PHYs
+ */
+static int bcm7xxx_suspend(struct phy_device *phydev)
+{
+        int ret;
+        const struct bcm7xxx_regs {
+                int reg;
+                u16 value;
+        } bcm7xxx_suspend_cfg[] = {
+                { MII_BCM7XXX_TEST, 0x008b },
+                { MII_BCM7XXX_100TX_AUX_CTL, 0x01c0 },
+                { MII_BCM7XXX_100TX_DISC, 0x7000 },
+                { MII_BCM7XXX_TEST, 0x000f },
+                { MII_BCM7XXX_100TX_AUX_CTL, 0x20d0 },
+                { MII_BCM7XXX_TEST, 0x000b },
+        };
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(bcm7xxx_suspend_cfg); i++) {
+                ret = phy_write(phydev,
+                                bcm7xxx_suspend_cfg[i].reg,
+                                bcm7xxx_suspend_cfg[i].value);
+                if (ret)
+                        return ret;
+        }
+
+        return 0;
+}
+
+static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
+{
+        return 0;
+}
+
+static struct phy_driver bcm7xxx_driver[] = {
+{
+        .phy_id         = PHY_ID_BCM7366,
+        .phy_id_mask    = 0xfffffff0,
+        .name           = "Broadcom BCM7366",
+        .features       = PHY_GBIT_FEATURES |
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+        .flags          = PHY_IS_INTERNAL,
+        .config_init    = bcm7xxx_28nm_afe_config_init,
+        .config_aneg    = genphy_config_aneg,
+        .read_status    = genphy_read_status,
+        .suspend        = bcm7xxx_suspend,
+        .resume         = bcm7xxx_28nm_afe_config_init,
+        .driver         = { .owner = THIS_MODULE },
+}, {
+        .phy_id         = PHY_ID_BCM7439,
+        .phy_id_mask    = 0xfffffff0,
+        .name           = "Broadcom BCM7439",
+        .features       = PHY_GBIT_FEATURES |
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+        .flags          = PHY_IS_INTERNAL,
+        .config_init    = bcm7xxx_28nm_afe_config_init,
+        .config_aneg    = genphy_config_aneg,
+        .read_status    = genphy_read_status,
+        .suspend        = bcm7xxx_suspend,
+        .resume         = bcm7xxx_28nm_afe_config_init,
+        .driver         = { .owner = THIS_MODULE },
+}, {
+        .phy_id         = PHY_ID_BCM7445,
+        .phy_id_mask    = 0xfffffff0,
+        .name           = "Broadcom BCM7445",
+        .features       = PHY_GBIT_FEATURES |
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+        .flags          = PHY_IS_INTERNAL,
+        .config_init    = bcm7xxx_28nm_config_init,
+        .config_aneg    = genphy_config_aneg,
+        .read_status    = genphy_read_status,
+        .suspend        = bcm7xxx_suspend,
+        .resume         = bcm7xxx_28nm_config_init,
+        .driver         = { .owner = THIS_MODULE },
+}, {
+        .name           = "Broadcom BCM7XXX 28nm",
+        .phy_id         = PHY_ID_BCM7XXX_28,
+        .phy_id_mask    = PHY_BCM_OUI_MASK,
+        .features       = PHY_GBIT_FEATURES |
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+        .flags          = PHY_IS_INTERNAL,
+        .config_init    = bcm7xxx_28nm_config_init,
+        .config_aneg    = genphy_config_aneg,
+        .read_status    = genphy_read_status,
+        .suspend        = bcm7xxx_suspend,
+        .resume         = bcm7xxx_28nm_config_init,
+        .driver         = { .owner = THIS_MODULE },
+}, {
+        .phy_id         = PHY_BCM_OUI_4,
+        .phy_id_mask    = 0xffff0000,
+        .name           = "Broadcom BCM7XXX 40nm",
+        .features       = PHY_GBIT_FEATURES |
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+        .flags          = PHY_IS_INTERNAL,
+        .config_init    = bcm7xxx_config_init,
+        .config_aneg    = genphy_config_aneg,
+        .read_status    = genphy_read_status,
+        .suspend        = bcm7xxx_suspend,
+        .resume         = bcm7xxx_config_init,
+        .driver         = { .owner = THIS_MODULE },
+}, {
+        .phy_id         = PHY_BCM_OUI_5,
+        .phy_id_mask    = 0xffffff00,
+        .name           = "Broadcom BCM7XXX 65nm",
+        .features       = PHY_BASIC_FEATURES |
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+        .flags          = PHY_IS_INTERNAL,
+        .config_init    = bcm7xxx_dummy_config_init,
+        .config_aneg    = genphy_config_aneg,
+        .read_status    = genphy_read_status,
+        .suspend        = bcm7xxx_suspend,
+        .resume         = bcm7xxx_config_init,
+        .driver         = { .owner = THIS_MODULE },
+} };
+
+static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
+        { PHY_ID_BCM7366, 0xfffffff0, },
+        { PHY_ID_BCM7439, 0xfffffff0, },
+        { PHY_ID_BCM7445, 0xfffffff0, },
+        { PHY_ID_BCM7XXX_28, 0xfffffc00 },
+        { PHY_BCM_OUI_4, 0xffff0000 },
+        { PHY_BCM_OUI_5, 0xffffff00 },
+        { }
+};
+
+static int __init bcm7xxx_phy_init(void)
+{
+        return phy_drivers_register(bcm7xxx_driver,
+                        ARRAY_SIZE(bcm7xxx_driver));
+}
+
+static void __exit bcm7xxx_phy_exit(void)
+{
+        phy_drivers_unregister(bcm7xxx_driver,
+                        ARRAY_SIZE(bcm7xxx_driver));
+}
+
+module_init(bcm7xxx_phy_init);
+module_exit(bcm7xxx_phy_exit);
+
+MODULE_DEVICE_TABLE(mdio, bcm7xxx_tbl);
+
+MODULE_DESCRIPTION("Broadcom BCM7xxx internal PHY driver");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Broadcom Corporation");
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index f8c90ea75108..34088d60da74 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -25,58 +25,6 @@
 #define BRCM_PHY_REV(phydev) \
         ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
 
-
-#define MII_BCM54XX_ECR         0x10    /* BCM54xx extended control register */
-#define MII_BCM54XX_ECR_IM      0x1000  /* Interrupt mask */
-#define MII_BCM54XX_ECR_IF      0x0800  /* Interrupt force */
-
-#define MII_BCM54XX_ESR         0x11    /* BCM54xx extended status register */
-#define MII_BCM54XX_ESR_IS      0x1000  /* Interrupt status */
-
-#define MII_BCM54XX_EXP_DATA    0x15    /* Expansion register data */
-#define MII_BCM54XX_EXP_SEL     0x17    /* Expansion register select */
-#define MII_BCM54XX_EXP_SEL_SSD 0x0e00  /* Secondary SerDes select */
-#define MII_BCM54XX_EXP_SEL_ER  0x0f00  /* Expansion register select */
-
-#define MII_BCM54XX_AUX_CTL     0x18    /* Auxiliary control register */
-#define MII_BCM54XX_ISR         0x1a    /* BCM54xx interrupt status register */
-#define MII_BCM54XX_IMR         0x1b    /* BCM54xx interrupt mask register */
-#define MII_BCM54XX_INT_CRCERR  0x0001  /* CRC error */
-#define MII_BCM54XX_INT_LINK    0x0002  /* Link status changed */
-#define MII_BCM54XX_INT_SPEED   0x0004  /* Link speed change */
-#define MII_BCM54XX_INT_DUPLEX  0x0008  /* Duplex mode changed */
-#define MII_BCM54XX_INT_LRS     0x0010  /* Local receiver status changed */
-#define MII_BCM54XX_INT_RRS     0x0020  /* Remote receiver status changed */
-#define MII_BCM54XX_INT_SSERR   0x0040  /* Scrambler synchronization error */
-#define MII_BCM54XX_INT_UHCD    0x0080  /* Unsupported HCD negotiated */
-#define MII_BCM54XX_INT_NHCD    0x0100  /* No HCD */
-#define MII_BCM54XX_INT_NHCDL   0x0200  /* No HCD link */
-#define MII_BCM54XX_INT_ANPR    0x0400  /* Auto-negotiation page received */
-#define MII_BCM54XX_INT_LC      0x0800  /* All counters below 128 */
-#define MII_BCM54XX_INT_HC      0x1000  /* Counter above 32768 */
-#define MII_BCM54XX_INT_MDIX    0x2000  /* MDIX status change */
-#define MII_BCM54XX_INT_PSERR   0x4000  /* Pair swap error */
-
-#define MII_BCM54XX_SHD         0x1c    /* 0x1c shadow registers */
-#define MII_BCM54XX_SHD_WRITE   0x8000
-#define MII_BCM54XX_SHD_VAL(x)  ((x & 0x1f) << 10)
-#define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0)
-
-/*
- * AUXILIARY CONTROL SHADOW ACCESS REGISTERS.  (PHY REG 0x18)
- */
-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL       0x0000
-#define MII_BCM54XX_AUXCTL_ACTL_TX_6DB          0x0400
-#define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA       0x0800
-
-#define MII_BCM54XX_AUXCTL_MISC_WREN    0x8000
-#define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX     0x0200
-#define MII_BCM54XX_AUXCTL_MISC_RDSEL_MISC      0x7000
-#define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x0007
-
-#define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL       0x0000
-
-
 /*
  * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
  * BCM5482, and possibly some others.
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 71e49000fbf3..76f54b32a120 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -432,8 +432,28 @@ phy_id_show(struct device *dev, struct device_attribute *attr, char *buf)
 }
 static DEVICE_ATTR_RO(phy_id);
 
+static ssize_t
+phy_interface_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        struct phy_device *phydev = to_phy_device(dev);
+
+        return sprintf(buf, "%s\n", phy_modes(phydev->interface));
+}
+static DEVICE_ATTR_RO(phy_interface);
+
+static ssize_t
+phy_has_fixups_show(struct device *dev, struct device_attribute *attr, char *buf)
+{
+        struct phy_device *phydev = to_phy_device(dev);
+
+        return sprintf(buf, "%d\n", phydev->has_fixups);
+}
+static DEVICE_ATTR_RO(phy_has_fixups);
+
 static struct attribute *mdio_dev_attrs[] = {
         &dev_attr_phy_id.attr,
+        &dev_attr_phy_interface.attr,
+        &dev_attr_phy_has_fixups.attr,
         NULL,
 };
 ATTRIBUTE_GROUPS(mdio_dev);
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index 5a8993b0cafc..0c9e4342f11d 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -148,15 +148,52 @@ static int ks8737_config_intr(struct phy_device *phydev)
         return rc < 0 ? rc : 0;
 }
 
+static int kszphy_setup_led(struct phy_device *phydev,
+                            unsigned int reg, unsigned int shift)
+{
+
+        struct device *dev = &phydev->dev;
+        struct device_node *of_node = dev->of_node;
+        int rc, temp;
+        u32 val;
+
+        if (!of_node && dev->parent->of_node)
+                of_node = dev->parent->of_node;
+
+        if (of_property_read_u32(of_node, "micrel,led-mode", &val))
+                return 0;
+
+        temp = phy_read(phydev, reg);
+        if (temp < 0)
+                return temp;
+
+        temp &= 3 << shift;
+        temp |= val << shift;
+        rc = phy_write(phydev, reg, temp);
+
+        return rc < 0 ? rc : 0;
+}
+
 static int kszphy_config_init(struct phy_device *phydev)
 {
         return 0;
 }
 
+static int kszphy_config_init_led8041(struct phy_device *phydev)
+{
+        /* single led control, register 0x1e bits 15..14 */
+        return kszphy_setup_led(phydev, 0x1e, 14);
+}
+
 static int ksz8021_config_init(struct phy_device *phydev)
 {
-        int rc;
         const u16 val = KSZPHY_OMSO_B_CAST_OFF | KSZPHY_OMSO_RMII_OVERRIDE;
+        int rc;
+
+        rc = kszphy_setup_led(phydev, 0x1f, 4);
+        if (rc)
+                dev_err(&phydev->dev, "failed to set led mode\n");
+
         phy_write(phydev, MII_KSZPHY_OMSO, val);
         rc = ksz_config_flags(phydev);
         return rc < 0 ? rc : 0;
@@ -166,6 +203,10 @@ static int ks8051_config_init(struct phy_device *phydev)
 {
         int rc;
 
+        rc = kszphy_setup_led(phydev, 0x1f, 4);
+        if (rc)
+                dev_err(&phydev->dev, "failed to set led mode\n");
+
         rc = ksz_config_flags(phydev);
         return rc < 0 ? rc : 0;
 }
@@ -327,7 +368,7 @@ static struct phy_driver ksphy_driver[] = {
         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause
                                 | SUPPORTED_Asym_Pause),
         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
-        .config_init    = kszphy_config_init,
+        .config_init    = kszphy_config_init_led8041,
         .config_aneg    = genphy_config_aneg,
         .read_status    = genphy_read_status,
         .ack_interrupt  = kszphy_ack_interrupt,
@@ -342,7 +383,7 @@ static struct phy_driver ksphy_driver[] = {
         .features       = PHY_BASIC_FEATURES |
                           SUPPORTED_Pause | SUPPORTED_Asym_Pause,
         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
-        .config_init    = kszphy_config_init,
+        .config_init    = kszphy_config_init_led8041,
         .config_aneg    = genphy_config_aneg,
         .read_status    = genphy_read_status,
         .ack_interrupt  = kszphy_ack_interrupt,
@@ -371,7 +412,7 @@ static struct phy_driver ksphy_driver[] = {
         .phy_id_mask    = 0x00ffffff,
         .features       = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
         .flags          = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
-        .config_init    = kszphy_config_init,
+        .config_init    = kszphy_config_init_led8041,
         .config_aneg    = genphy_config_aneg,
         .read_status    = genphy_read_status,
         .ack_interrupt  = kszphy_ack_interrupt,
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 19c9eca0ef26..643b5d665f41 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -38,6 +38,26 @@
 
 #include <asm/irq.h>
 
+static const char *phy_speed_to_str(int speed)
+{
+        switch (speed) {
+        case SPEED_10:
+                return "10Mbps";
+        case SPEED_100:
+                return "100Mbps";
+        case SPEED_1000:
+                return "1Gbps";
+        case SPEED_2500:
+                return "2.5Gbps";
+        case SPEED_10000:
+                return "10Gbps";
+        case SPEED_UNKNOWN:
+                return "Unknown";
+        default:
+                return "Unsupported (update phy.c)";
+        }
+}
+
 /**
  * phy_print_status - Convenience function to print out the current phy status
  * @phydev: the phy_device struct
@@ -45,12 +65,13 @@
 void phy_print_status(struct phy_device *phydev)
 {
         if (phydev->link) {
-                pr_info("%s - Link is Up - %d/%s\n",
-                        dev_name(&phydev->dev),
-                        phydev->speed,
-                        DUPLEX_FULL == phydev->duplex ? "Full" : "Half");
+                netdev_info(phydev->attached_dev,
+                        "Link is Up - %s/%s - flow control %s\n",
+                        phy_speed_to_str(phydev->speed),
+                        DUPLEX_FULL == phydev->duplex ? "Full" : "Half",
+                        phydev->pause ? "rx/tx" : "off");
         } else  {
-                pr_info("%s - Link is Down\n", dev_name(&phydev->dev));
+                netdev_info(phydev->attached_dev, "Link is Down\n");
         }
 }
 EXPORT_SYMBOL(phy_print_status);
@@ -62,7 +83,7 @@ EXPORT_SYMBOL(phy_print_status);
  * If the @phydev driver has an ack_interrupt function, call it to
  * ack and clear the phy device's interrupt.
  *
- * Returns 0 on success on < 0 on error.
+ * Returns 0 on success or < 0 on error.
  */
 static int phy_clear_interrupt(struct phy_device *phydev)
 {
@@ -77,7 +98,7 @@ static int phy_clear_interrupt(struct phy_device *phydev)
  * @phydev: the phy_device struct
  * @interrupts: interrupt flags to configure for this @phydev
  *
- * Returns 0 on success on < 0 on error.
+ * Returns 0 on success or < 0 on error.
  */
 static int phy_config_interrupt(struct phy_device *phydev, u32 interrupts)
 {
@@ -93,15 +114,16 @@ static int phy_config_interrupt(struct phy_device *phydev, u32 interrupts)
  * phy_aneg_done - return auto-negotiation status
  * @phydev: target phy_device struct
  *
- * Description: Reads the status register and returns 0 either if
- *   auto-negotiation is incomplete, or if there was an error.
- *   Returns BMSR_ANEGCOMPLETE if auto-negotiation is done.
+ * Description: Return the auto-negotiation status from this @phydev
+ * Returns > 0 on success or < 0 on error. 0 means that auto-negotiation
+ * is still pending.
  */
 static inline int phy_aneg_done(struct phy_device *phydev)
 {
-        int retval = phy_read(phydev, MII_BMSR);
+        if (phydev->drv->aneg_done)
+                return phydev->drv->aneg_done(phydev);
 
-        return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
+        return genphy_aneg_done(phydev);
 }
 
 /* A structure for mapping a particular speed and duplex
@@ -283,7 +305,10 @@ int phy_ethtool_gset(struct phy_device *phydev, struct ethtool_cmd *cmd)
 
         ethtool_cmd_speed_set(cmd, phydev->speed);
         cmd->duplex = phydev->duplex;
-        cmd->port = PORT_MII;
+        if (phydev->interface == PHY_INTERFACE_MODE_MOCA)
+                cmd->port = PORT_BNC;
+        else
+                cmd->port = PORT_MII;
         cmd->phy_address = phydev->addr;
         cmd->transceiver = phy_is_internal(phydev) ?
                 XCVR_INTERNAL : XCVR_EXTERNAL;
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 4b970f7624c0..a2fbb3e1db9a 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -139,6 +139,7 @@ static int phy_scan_fixups(struct phy_device *phydev)
                                 mutex_unlock(&phy_fixup_lock);
                                 return err;
                         }
+                        phydev->has_fixups = true;
                 }
         }
         mutex_unlock(&phy_fixup_lock);
@@ -534,16 +535,16 @@ static int phy_poll_reset(struct phy_device *phydev)
 
 int phy_init_hw(struct phy_device *phydev)
 {
-        int ret;
+        int ret = 0;
 
         if (!phydev->drv || !phydev->drv->config_init)
                 return 0;
 
-        ret = phy_write(phydev, MII_BMCR, BMCR_RESET);
-        if (ret < 0)
-                return ret;
+        if (phydev->drv->soft_reset)
+                ret = phydev->drv->soft_reset(phydev);
+        else
+                ret = genphy_soft_reset(phydev);
 
-        ret = phy_poll_reset(phydev);
         if (ret < 0)
                 return ret;
 
@@ -865,6 +866,22 @@ int genphy_config_aneg(struct phy_device *phydev)
 }
 EXPORT_SYMBOL(genphy_config_aneg);
 
+/**
+ * genphy_aneg_done - return auto-negotiation status
+ * @phydev: target phy_device struct
+ *
+ * Description: Reads the status register and returns 0 either if
+ *   auto-negotiation is incomplete, or if there was an error.
+ *   Returns BMSR_ANEGCOMPLETE if auto-negotiation is done.
+ */
+int genphy_aneg_done(struct phy_device *phydev)
+{
+        int retval = phy_read(phydev, MII_BMSR);
+
+        return (retval < 0) ? retval : (retval & BMSR_ANEGCOMPLETE);
+}
+EXPORT_SYMBOL(genphy_aneg_done);
+
 static int gen10g_config_aneg(struct phy_device *phydev)
 {
         return 0;
@@ -1030,6 +1047,27 @@ static int gen10g_read_status(struct phy_device *phydev)
         return 0;
 }
 
+/**
+ * genphy_soft_reset - software reset the PHY via BMCR_RESET bit
+ * @phydev: target phy_device struct
+ *
+ * Description: Perform a software PHY reset using the standard
+ * BMCR_RESET bit and poll for the reset bit to be cleared.
+ *
+ * Returns: 0 on success, < 0 on failure
+ */
+int genphy_soft_reset(struct phy_device *phydev)
+{
+        int ret;
+
+        ret = phy_write(phydev, MII_BMCR, BMCR_RESET);
+        if (ret < 0)
+                return ret;
+
+        return phy_poll_reset(phydev);
+}
+EXPORT_SYMBOL(genphy_soft_reset);
+
 static int genphy_config_init(struct phy_device *phydev)
 {
         int val;
@@ -1076,6 +1114,12 @@ static int genphy_config_init(struct phy_device *phydev)
         return 0;
 }
 
+static int gen10g_soft_reset(struct phy_device *phydev)
+{
+        /* Do nothing for now */
+        return 0;
+}
+
 static int gen10g_config_init(struct phy_device *phydev)
 {
         /* Temporarily just say we support everything */
@@ -1250,9 +1294,11 @@ static struct phy_driver genphy_driver[] = {
         .phy_id         = 0xffffffff,
         .phy_id_mask    = 0xffffffff,
         .name           = "Generic PHY",
+        .soft_reset     = genphy_soft_reset,
         .config_init    = genphy_config_init,
         .features       = 0,
         .config_aneg    = genphy_config_aneg,
+        .aneg_done      = genphy_aneg_done,
         .read_status    = genphy_read_status,
         .suspend        = genphy_suspend,
         .resume         = genphy_resume,
@@ -1261,6 +1307,7 @@ static struct phy_driver genphy_driver[] = {
         .phy_id         = 0xffffffff,
         .phy_id_mask    = 0xffffffff,
         .name           = "Generic 10G PHY",
+        .soft_reset     = gen10g_soft_reset,
         .config_init    = gen10g_config_init,
         .features       = 0,
         .config_aneg    = gen10g_config_aneg,