4 files changed, 203 insertions, 95 deletions

diff --git a/drivers/net/ethernet/realtek/8139cp.c b/drivers/net/ethernet/realtek/8139cp.c
index b62a32484f6a..7d1fb9ad1296 100644
--- a/drivers/net/ethernet/realtek/8139cp.c
+++ b/drivers/net/ethernet/realtek/8139cp.c
@@ -431,7 +431,7 @@ static inline void cp_rx_skb (struct cp_private *cp, struct sk_buff *skb,
         cp->dev->stats.rx_bytes += skb->len;
 
         if (opts2 & RxVlanTagged)
-                __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
+                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
 
         napi_gro_receive(&cp->napi, skb);
 }
@@ -1438,7 +1438,7 @@ static int cp_set_features(struct net_device *dev, netdev_features_t features)
         else
                 cp->cpcmd &= ~RxChkSum;
 
-        if (features & NETIF_F_HW_VLAN_RX)
+        if (features & NETIF_F_HW_VLAN_CTAG_RX)
                 cp->cpcmd |= RxVlanOn;
         else
                 cp->cpcmd &= ~RxVlanOn;
@@ -1955,14 +1955,14 @@ static int cp_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
         dev->ethtool_ops = &cp_ethtool_ops;
         dev->watchdog_timeo = TX_TIMEOUT;
 
-        dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+        dev->features |= NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
 
         if (pci_using_dac)
                 dev->features |= NETIF_F_HIGHDMA;
 
         /* disabled by default until verified */
         dev->hw_features |= NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
-                NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+                NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
                 NETIF_F_HIGHDMA;
 
diff --git a/drivers/net/ethernet/realtek/8139too.c b/drivers/net/ethernet/realtek/8139too.c
index 1276ac71353a..3ccedeb8aba0 100644
--- a/drivers/net/ethernet/realtek/8139too.c
+++ b/drivers/net/ethernet/realtek/8139too.c
@@ -2041,8 +2041,6 @@ keep_pkt:
 
                         netif_receive_skb (skb);
                 } else {
-                        if (net_ratelimit())
-                                netdev_warn(dev, "Memory squeeze, dropping packet\n");
                         dev->stats.rx_dropped++;
                 }
                 received++;
diff --git a/drivers/net/ethernet/realtek/atp.c b/drivers/net/ethernet/realtek/atp.c
index 9f2d416de750..d77d60ea8202 100644
--- a/drivers/net/ethernet/realtek/atp.c
+++ b/drivers/net/ethernet/realtek/atp.c
@@ -782,8 +782,6 @@ static void net_rx(struct net_device *dev)
 
                 skb = netdev_alloc_skb(dev, pkt_len + 2);
                 if (skb == NULL) {
-                        printk(KERN_ERR "%s: Memory squeeze, dropping packet.\n",
-                                   dev->name);
                         dev->stats.rx_dropped++;
                         goto done;
                 }
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 4ecbe64a758d..c6dac38fd9cc 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -47,7 +47,9 @@
 #define FIRMWARE_8402_1         "rtl_nic/rtl8402-1.fw"
 #define FIRMWARE_8411_1         "rtl_nic/rtl8411-1.fw"
 #define FIRMWARE_8106E_1        "rtl_nic/rtl8106e-1.fw"
-#define FIRMWARE_8168G_1        "rtl_nic/rtl8168g-1.fw"
+#define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
+#define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
+#define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
 
 #ifdef RTL8169_DEBUG
 #define assert(expr) \
@@ -140,6 +142,8 @@ enum mac_version {
         RTL_GIGA_MAC_VER_39,
         RTL_GIGA_MAC_VER_40,
         RTL_GIGA_MAC_VER_41,
+        RTL_GIGA_MAC_VER_42,
+        RTL_GIGA_MAC_VER_43,
         RTL_GIGA_MAC_NONE   = 0xff,
 };
 
@@ -262,10 +266,16 @@ static const struct {
                 _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_1,
                                                         JUMBO_1K, true),
         [RTL_GIGA_MAC_VER_40] =
-                _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_1,
+                _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_2,
                                                         JUMBO_9K, false),
         [RTL_GIGA_MAC_VER_41] =
                 _R("RTL8168g/8111g",    RTL_TD_1, NULL, JUMBO_9K, false),
+        [RTL_GIGA_MAC_VER_42] =
+                _R("RTL8168g/8111g",    RTL_TD_1, FIRMWARE_8168G_3,
+                                                        JUMBO_9K, false),
+        [RTL_GIGA_MAC_VER_43] =
+                _R("RTL8106e",          RTL_TD_1, FIRMWARE_8106E_2,
+                                                        JUMBO_1K, true),
 };
 #undef _R
 
@@ -329,6 +339,7 @@ enum rtl_registers {
 #define RXCFG_FIFO_SHIFT                13
                                         /* No threshold before first PCI xfer */
 #define RX_FIFO_THRESH                  (7 << RXCFG_FIFO_SHIFT)
+#define RX_EARLY_OFF                    (1 << 11)
 #define RXCFG_DMA_SHIFT                 8
                                         /* Unlimited maximum PCI burst. */
 #define RX_DMA_BURST                    (7 << RXCFG_DMA_SHIFT)
@@ -513,6 +524,7 @@ enum rtl_register_content {
         PMEnable        = (1 << 0),     /* Power Management Enable */
 
         /* Config2 register p. 25 */
+        ClkReqEn        = (1 << 7),     /* Clock Request Enable */
         MSIEnable       = (1 << 5),     /* 8169 only. Reserved in the 8168. */
         PCI_Clock_66MHz = 0x01,
         PCI_Clock_33MHz = 0x00,
@@ -533,6 +545,7 @@ enum rtl_register_content {
         Spi_en          = (1 << 3),
         LanWake         = (1 << 1),     /* LanWake enable/disable */
         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
+        ASPM_en         = (1 << 0),     /* ASPM enable */
 
         /* TBICSR p.28 */
         TBIReset        = 0x80000000,
@@ -814,7 +827,9 @@ MODULE_FIRMWARE(FIRMWARE_8168F_2);
 MODULE_FIRMWARE(FIRMWARE_8402_1);
 MODULE_FIRMWARE(FIRMWARE_8411_1);
 MODULE_FIRMWARE(FIRMWARE_8106E_1);
-MODULE_FIRMWARE(FIRMWARE_8168G_1);
+MODULE_FIRMWARE(FIRMWARE_8106E_2);
+MODULE_FIRMWARE(FIRMWARE_8168G_2);
+MODULE_FIRMWARE(FIRMWARE_8168G_3);
 
 static void rtl_lock_work(struct rtl8169_private *tp)
 {
@@ -1024,14 +1039,6 @@ static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
                 (RTL_R32(GPHY_OCP) & 0xffff) : ~0;
 }
 
-static void rtl_w1w0_phy_ocp(struct rtl8169_private *tp, int reg, int p, int m)
-{
-        int val;
-
-        val = r8168_phy_ocp_read(tp, reg);
-        r8168_phy_ocp_write(tp, reg, (val | p) & ~m);
-}
-
 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
 {
         void __iomem *ioaddr = tp->mmio_addr;
@@ -1077,6 +1084,21 @@ static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
         return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
 }
 
+static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
+{
+        if (reg == 0x1f) {
+                tp->ocp_base = value << 4;
+                return;
+        }
+
+        r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
+}
+
+static int mac_mcu_read(struct rtl8169_private *tp, int reg)
+{
+        return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
+}
+
 DECLARE_RTL_COND(rtl_phyar_cond)
 {
         void __iomem *ioaddr = tp->mmio_addr;
@@ -1771,16 +1793,17 @@ static void __rtl8169_set_features(struct net_device *dev,
         netdev_features_t changed = features ^ dev->features;
         void __iomem *ioaddr = tp->mmio_addr;
 
-        if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)))
+        if (!(changed & (NETIF_F_RXALL | NETIF_F_RXCSUM |
+                         NETIF_F_HW_VLAN_CTAG_RX)))
                 return;
 
-        if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_RX)) {
+        if (changed & (NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_RX)) {
                 if (features & NETIF_F_RXCSUM)
                         tp->cp_cmd |= RxChkSum;
                 else
                         tp->cp_cmd &= ~RxChkSum;
 
-                if (dev->features & NETIF_F_HW_VLAN_RX)
+                if (dev->features & NETIF_F_HW_VLAN_CTAG_RX)
                         tp->cp_cmd |= RxVlan;
                 else
                         tp->cp_cmd &= ~RxVlan;
@@ -1820,7 +1843,7 @@ static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
         u32 opts2 = le32_to_cpu(desc->opts2);
 
         if (opts2 & RxVlanTag)
-                __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
+                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
 }
 
 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
@@ -2028,6 +2051,7 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
                 int mac_version;
         } mac_info[] = {
                 /* 8168G family. */
+                { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
                 { 0x7cf00000, 0x4c100000,       RTL_GIGA_MAC_VER_41 },
                 { 0x7cf00000, 0x4c000000,       RTL_GIGA_MAC_VER_40 },
 
@@ -2116,6 +2140,10 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
                 netif_notice(tp, probe, dev,
                              "unknown MAC, using family default\n");
                 tp->mac_version = default_version;
+        } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
+                tp->mac_version = tp->mii.supports_gmii ?
+                                  RTL_GIGA_MAC_VER_42 :
+                                  RTL_GIGA_MAC_VER_43;
         }
 }
 
@@ -2142,9 +2170,7 @@ static void rtl_writephy_batch(struct rtl8169_private *tp,
 #define PHY_DATA_OR             0x10000000
 #define PHY_DATA_AND            0x20000000
 #define PHY_BJMPN               0x30000000
-#define PHY_READ_EFUSE          0x40000000
-#define PHY_READ_MAC_BYTE       0x50000000
-#define PHY_WRITE_MAC_BYTE      0x60000000
+#define PHY_MDIO_CHG            0x40000000
 #define PHY_CLEAR_READCOUNT     0x70000000
 #define PHY_WRITE               0x80000000
 #define PHY_READCOUNT_EQ_SKIP   0x90000000
@@ -2153,7 +2179,6 @@ static void rtl_writephy_batch(struct rtl8169_private *tp,
 #define PHY_WRITE_PREVIOUS      0xc0000000
 #define PHY_SKIPN               0xd0000000
 #define PHY_DELAY_MS            0xe0000000
-#define PHY_WRITE_ERI_WORD      0xf0000000
 
 struct fw_info {
         u32     magic;
@@ -2230,7 +2255,7 @@ static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
                 case PHY_READ:
                 case PHY_DATA_OR:
                 case PHY_DATA_AND:
-                case PHY_READ_EFUSE:
+                case PHY_MDIO_CHG:
                 case PHY_CLEAR_READCOUNT:
                 case PHY_WRITE:
                 case PHY_WRITE_PREVIOUS:
@@ -2261,9 +2286,6 @@ static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
                         }
                         break;
 
-                case PHY_READ_MAC_BYTE:
-                case PHY_WRITE_MAC_BYTE:
-                case PHY_WRITE_ERI_WORD:
                 default:
                         netif_err(tp, ifup, tp->dev,
                                   "Invalid action 0x%08x\n", action);
@@ -2294,10 +2316,13 @@ out:
 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
 {
         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
+        struct mdio_ops org, *ops = &tp->mdio_ops;
         u32 predata, count;
         size_t index;
 
         predata = count = 0;
+        org.write = ops->write;
+        org.read = ops->read;
 
         for (index = 0; index < pa->size; ) {
                 u32 action = le32_to_cpu(pa->code[index]);
@@ -2324,8 +2349,15 @@ static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
                 case PHY_BJMPN:
                         index -= regno;
                         break;
-                case PHY_READ_EFUSE:
-                        predata = rtl8168d_efuse_read(tp, regno);
+                case PHY_MDIO_CHG:
+                        if (data == 0) {
+                                ops->write = org.write;
+                                ops->read = org.read;
+                        } else if (data == 1) {
+                                ops->write = mac_mcu_write;
+                                ops->read = mac_mcu_read;
+                        }
+
                         index++;
                         break;
                 case PHY_CLEAR_READCOUNT:
@@ -2361,13 +2393,13 @@ static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
                         index++;
                         break;
 
-                case PHY_READ_MAC_BYTE:
-                case PHY_WRITE_MAC_BYTE:
-                case PHY_WRITE_ERI_WORD:
                 default:
                         BUG();
                 }
         }
+
+        ops->write = org.write;
+        ops->read = org.read;
 }
 
 static void rtl_release_firmware(struct rtl8169_private *tp)
@@ -3368,51 +3400,68 @@ static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
 
 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
 {
-        static const u16 mac_ocp_patch[] = {
-                0xe008, 0xe01b, 0xe01d, 0xe01f,
-                0xe021, 0xe023, 0xe025, 0xe027,
-                0x49d2, 0xf10d, 0x766c, 0x49e2,
-                0xf00a, 0x1ec0, 0x8ee1, 0xc60a,
-
-                0x77c0, 0x4870, 0x9fc0, 0x1ea0,
-                0xc707, 0x8ee1, 0x9d6c, 0xc603,
-                0xbe00, 0xb416, 0x0076, 0xe86c,
-                0xc602, 0xbe00, 0x0000, 0xc602,
-
-                0xbe00, 0x0000, 0xc602, 0xbe00,
-                0x0000, 0xc602, 0xbe00, 0x0000,
-                0xc602, 0xbe00, 0x0000, 0xc602,
-                0xbe00, 0x0000, 0xc602, 0xbe00,
-
-                0x0000, 0x0000, 0x0000, 0x0000
-        };
-        u32 i;
+        rtl_apply_firmware(tp);
 
-        /* Patch code for GPHY reset */
-        for (i = 0; i < ARRAY_SIZE(mac_ocp_patch); i++)
-                r8168_mac_ocp_write(tp, 0xf800 + 2*i, mac_ocp_patch[i]);
-        r8168_mac_ocp_write(tp, 0xfc26, 0x8000);
-        r8168_mac_ocp_write(tp, 0xfc28, 0x0075);
+        rtl_writephy(tp, 0x1f, 0x0a46);
+        if (rtl_readphy(tp, 0x10) & 0x0100) {
+                rtl_writephy(tp, 0x1f, 0x0bcc);
+                rtl_w1w0_phy(tp, 0x12, 0x0000, 0x8000);
+        } else {
+                rtl_writephy(tp, 0x1f, 0x0bcc);
+                rtl_w1w0_phy(tp, 0x12, 0x8000, 0x0000);
+        }
 
-        rtl_apply_firmware(tp);
+        rtl_writephy(tp, 0x1f, 0x0a46);
+        if (rtl_readphy(tp, 0x13) & 0x0100) {
+                rtl_writephy(tp, 0x1f, 0x0c41);
+                rtl_w1w0_phy(tp, 0x15, 0x0002, 0x0000);
+        } else {
+                rtl_writephy(tp, 0x1f, 0x0c41);
+                rtl_w1w0_phy(tp, 0x15, 0x0000, 0x0002);
+        }
 
-        if (r8168_phy_ocp_read(tp, 0xa460) & 0x0100)
-                rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x8000);
-        else
-                rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x8000, 0x0000);
+        /* Enable PHY auto speed down */
+        rtl_writephy(tp, 0x1f, 0x0a44);
+        rtl_w1w0_phy(tp, 0x11, 0x000c, 0x0000);
+
+        rtl_writephy(tp, 0x1f, 0x0bcc);
+        rtl_w1w0_phy(tp, 0x14, 0x0100, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0a44);
+        rtl_w1w0_phy(tp, 0x11, 0x00c0, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x8084);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x6000);
+        rtl_w1w0_phy(tp, 0x10, 0x1003, 0x0000);
+
+        /* EEE auto-fallback function */
+        rtl_writephy(tp, 0x1f, 0x0a4b);
+        rtl_w1w0_phy(tp, 0x11, 0x0004, 0x0000);
+
+        /* Enable UC LPF tune function */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x8012);
+        rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
 
-        if (r8168_phy_ocp_read(tp, 0xa466) & 0x0100)
-                rtl_w1w0_phy_ocp(tp, 0xc41a, 0x0002, 0x0000);
-        else
-                rtl_w1w0_phy_ocp(tp, 0xbcc4, 0x0000, 0x0002);
+        rtl_writephy(tp, 0x1f, 0x0c42);
+        rtl_w1w0_phy(tp, 0x11, 0x4000, 0x2000);
 
-        rtl_w1w0_phy_ocp(tp, 0xa442, 0x000c, 0x0000);
-        rtl_w1w0_phy_ocp(tp, 0xa4b2, 0x0004, 0x0000);
+        /* Improve SWR Efficiency */
+        rtl_writephy(tp, 0x1f, 0x0bcd);
+        rtl_writephy(tp, 0x14, 0x5065);
+        rtl_writephy(tp, 0x14, 0xd065);
+        rtl_writephy(tp, 0x1f, 0x0bc8);
+        rtl_writephy(tp, 0x11, 0x5655);
+        rtl_writephy(tp, 0x1f, 0x0bcd);
+        rtl_writephy(tp, 0x14, 0x1065);
+        rtl_writephy(tp, 0x14, 0x9065);
+        rtl_writephy(tp, 0x14, 0x1065);
 
-        r8168_phy_ocp_write(tp, 0xa436, 0x8012);
-        rtl_w1w0_phy_ocp(tp, 0xa438, 0x8000, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0000);
+}
 
-        rtl_w1w0_phy_ocp(tp, 0xc422, 0x4000, 0x2000);
+static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
+{
+        rtl_apply_firmware(tp);
 }
 
 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
@@ -3600,6 +3649,10 @@ static void rtl_hw_phy_config(struct net_device *dev)
         case RTL_GIGA_MAC_VER_40:
                 rtl8168g_1_hw_phy_config(tp);
                 break;
+        case RTL_GIGA_MAC_VER_42:
+        case RTL_GIGA_MAC_VER_43:
+                rtl8168g_2_hw_phy_config(tp);
+                break;
 
         case RTL_GIGA_MAC_VER_41:
         default:
@@ -3808,6 +3861,8 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp)
                 break;
         case RTL_GIGA_MAC_VER_40:
         case RTL_GIGA_MAC_VER_41:
+        case RTL_GIGA_MAC_VER_42:
+        case RTL_GIGA_MAC_VER_43:
                 ops->write      = r8168g_mdio_write;
                 ops->read       = r8168g_mdio_read;
                 break;
@@ -3859,6 +3914,8 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_39:
         case RTL_GIGA_MAC_VER_40:
         case RTL_GIGA_MAC_VER_41:
+        case RTL_GIGA_MAC_VER_42:
+        case RTL_GIGA_MAC_VER_43:
                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
                 break;
@@ -3966,6 +4023,8 @@ static void r8168_phy_power_down(struct rtl8169_private *tp)
         switch (tp->mac_version) {
         case RTL_GIGA_MAC_VER_32:
         case RTL_GIGA_MAC_VER_33:
+        case RTL_GIGA_MAC_VER_40:
+        case RTL_GIGA_MAC_VER_41:
                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
                 break;
 
@@ -4027,6 +4086,11 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_33:
                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
                 break;
+        case RTL_GIGA_MAC_VER_40:
+        case RTL_GIGA_MAC_VER_41:
+                rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
+                             0xfc000000, ERIAR_EXGMAC);
+                break;
         }
 }
 
@@ -4044,6 +4108,11 @@ static void r8168_pll_power_up(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_33:
                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
                 break;
+        case RTL_GIGA_MAC_VER_40:
+        case RTL_GIGA_MAC_VER_41:
+                rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
+                             0x00000000, ERIAR_EXGMAC);
+                break;
         }
 
         r8168_phy_power_up(tp);
@@ -4080,6 +4149,7 @@ static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_30:
         case RTL_GIGA_MAC_VER_37:
         case RTL_GIGA_MAC_VER_39:
+        case RTL_GIGA_MAC_VER_43:
                 ops->down       = r810x_pll_power_down;
                 ops->up         = r810x_pll_power_up;
                 break;
@@ -4107,6 +4177,7 @@ static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_38:
         case RTL_GIGA_MAC_VER_40:
         case RTL_GIGA_MAC_VER_41:
+        case RTL_GIGA_MAC_VER_42:
                 ops->down       = r8168_pll_power_down;
                 ops->up         = r8168_pll_power_up;
                 break;
@@ -4149,6 +4220,12 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_34:
                 RTL_W32(RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
                 break;
+        case RTL_GIGA_MAC_VER_40:
+        case RTL_GIGA_MAC_VER_41:
+        case RTL_GIGA_MAC_VER_42:
+        case RTL_GIGA_MAC_VER_43:
+                RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
+                break;
         default:
                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST);
                 break;
@@ -4305,6 +4382,8 @@ static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
          */
         case RTL_GIGA_MAC_VER_40:
         case RTL_GIGA_MAC_VER_41:
+        case RTL_GIGA_MAC_VER_42:
+        case RTL_GIGA_MAC_VER_43:
         default:
                 ops->disable    = NULL;
                 ops->enable     = NULL;
@@ -4412,6 +4491,8 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
                    tp->mac_version == RTL_GIGA_MAC_VER_37 ||
                    tp->mac_version == RTL_GIGA_MAC_VER_40 ||
                    tp->mac_version == RTL_GIGA_MAC_VER_41 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_42 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_43 ||
                    tp->mac_version == RTL_GIGA_MAC_VER_38) {
                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
@@ -5127,6 +5208,8 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
         void __iomem *ioaddr = tp->mmio_addr;
         struct pci_dev *pdev = tp->pci_dev;
 
+        RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
+
         rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
         rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
         rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
@@ -5138,6 +5221,7 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
 
         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
         rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
+        rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
 
         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
         RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
@@ -5149,7 +5233,26 @@ static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
         /* Adjust EEE LED frequency */
         RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
 
-        rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x02, ERIAR_EXGMAC);
+        rtl_w1w0_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
+        rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
+}
+
+static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+        static const struct ephy_info e_info_8168g_2[] = {
+                { 0x00, 0x0000, 0x0008 },
+                { 0x0c, 0x3df0, 0x0200 },
+                { 0x19, 0xffff, 0xfc00 },
+                { 0x1e, 0xffff, 0x20eb }
+        };
+
+        rtl_hw_start_8168g_1(tp);
+
+        /* disable aspm and clock request before access ephy */
+        RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
+        RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
+        rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
 }
 
 static void rtl_hw_start_8168(struct net_device *dev)
@@ -5177,10 +5280,7 @@ static void rtl_hw_start_8168(struct net_device *dev)
 
         rtl_set_rx_tx_desc_registers(tp, ioaddr);
 
-        rtl_set_rx_mode(dev);
-
-        RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
-                (InterFrameGap << TxInterFrameGapShift));
+        rtl_set_rx_tx_config_registers(tp);
 
         RTL_R8(IntrMask);
 
@@ -5257,6 +5357,9 @@ static void rtl_hw_start_8168(struct net_device *dev)
         case RTL_GIGA_MAC_VER_41:
                 rtl_hw_start_8168g_1(tp);
                 break;
+        case RTL_GIGA_MAC_VER_42:
+                rtl_hw_start_8168g_2(tp);
+                break;
 
         default:
                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
@@ -5264,9 +5367,11 @@ static void rtl_hw_start_8168(struct net_device *dev)
                 break;
         }
 
+        RTL_W8(Cfg9346, Cfg9346_Lock);
+
         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
 
-        RTL_W8(Cfg9346, Cfg9346_Lock);
+        rtl_set_rx_mode(dev);
 
         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
 }
@@ -5424,6 +5529,17 @@ static void rtl_hw_start_8101(struct net_device *dev)
 
         RTL_W8(Cfg9346, Cfg9346_Unlock);
 
+        RTL_W8(MaxTxPacketSize, TxPacketMax);
+
+        rtl_set_rx_max_size(ioaddr, rx_buf_sz);
+
+        tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
+        RTL_W16(CPlusCmd, tp->cp_cmd);
+
+        rtl_set_rx_tx_desc_registers(tp, ioaddr);
+
+        rtl_set_rx_tx_config_registers(tp);
+
         switch (tp->mac_version) {
         case RTL_GIGA_MAC_VER_07:
                 rtl_hw_start_8102e_1(tp);
@@ -5451,28 +5567,21 @@ static void rtl_hw_start_8101(struct net_device *dev)
         case RTL_GIGA_MAC_VER_39:
                 rtl_hw_start_8106(tp);
                 break;
+        case RTL_GIGA_MAC_VER_43:
+                rtl_hw_start_8168g_2(tp);
+                break;
         }
 
         RTL_W8(Cfg9346, Cfg9346_Lock);
 
-        RTL_W8(MaxTxPacketSize, TxPacketMax);
-
-        rtl_set_rx_max_size(ioaddr, rx_buf_sz);
-
-        tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
-        RTL_W16(CPlusCmd, tp->cp_cmd);
-
         RTL_W16(IntrMitigate, 0x0000);
 
-        rtl_set_rx_tx_desc_registers(tp, ioaddr);
-
         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
-        rtl_set_rx_tx_config_registers(tp);
-
-        RTL_R8(IntrMask);
 
         rtl_set_rx_mode(dev);
 
+        RTL_R8(IntrMask);
+
         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
 }
 
@@ -6744,6 +6853,8 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
         switch (tp->mac_version) {
         case RTL_GIGA_MAC_VER_40:
         case RTL_GIGA_MAC_VER_41:
+        case RTL_GIGA_MAC_VER_42:
+        case RTL_GIGA_MAC_VER_43:
                 rtl_hw_init_8168g(tp);
                 break;
 
@@ -6926,16 +7037,17 @@ rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         /* don't enable SG, IP_CSUM and TSO by default - it might not work
          * properly for all devices */
         dev->features |= NETIF_F_RXCSUM |
-                NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+                NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
 
         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
-                NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
+                NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
+                NETIF_F_HW_VLAN_CTAG_RX;
         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
                 NETIF_F_HIGHDMA;
 
         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
-                dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
+                dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
 
         dev->hw_features |= NETIF_F_RXALL;
         dev->hw_features |= NETIF_F_RXFCS;