diff options
Diffstat (limited to 'drivers/net/ethernet/oki-semi')
-rw-r--r-- | drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h | 1 | ||||
-rw-r--r-- | drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | 64 |
2 files changed, 36 insertions, 29 deletions
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h index ba781747d174..b07311eaa693 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h | |||
@@ -658,6 +658,7 @@ extern u32 pch_src_uuid_lo_read(struct pci_dev *pdev); | |||
658 | extern u32 pch_src_uuid_hi_read(struct pci_dev *pdev); | 658 | extern u32 pch_src_uuid_hi_read(struct pci_dev *pdev); |
659 | extern u64 pch_rx_snap_read(struct pci_dev *pdev); | 659 | extern u64 pch_rx_snap_read(struct pci_dev *pdev); |
660 | extern u64 pch_tx_snap_read(struct pci_dev *pdev); | 660 | extern u64 pch_tx_snap_read(struct pci_dev *pdev); |
661 | extern int pch_set_station_address(u8 *addr, struct pci_dev *pdev); | ||
661 | #endif | 662 | #endif |
662 | 663 | ||
663 | /* pch_gbe_param.c */ | 664 | /* pch_gbe_param.c */ |
diff --git a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c index 1e38d502a062..3787c64ee71c 100644 --- a/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c +++ b/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe_main.c | |||
@@ -79,7 +79,6 @@ const char pch_driver_version[] = DRV_VERSION; | |||
79 | #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888 | 79 | #define PCH_GBE_PAUSE_PKT4_VALUE 0x01000888 |
80 | #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF | 80 | #define PCH_GBE_PAUSE_PKT5_VALUE 0x0000FFFF |
81 | 81 | ||
82 | #define PCH_GBE_ETH_ALEN 6 | ||
83 | 82 | ||
84 | /* This defines the bits that are set in the Interrupt Mask | 83 | /* This defines the bits that are set in the Interrupt Mask |
85 | * Set/Read Register. Each bit is documented below: | 84 | * Set/Read Register. Each bit is documented below: |
@@ -101,18 +100,19 @@ const char pch_driver_version[] = DRV_VERSION; | |||
101 | 100 | ||
102 | #ifdef CONFIG_PCH_PTP | 101 | #ifdef CONFIG_PCH_PTP |
103 | /* Macros for ieee1588 */ | 102 | /* Macros for ieee1588 */ |
104 | #define TICKS_NS_SHIFT 5 | ||
105 | |||
106 | /* 0x40 Time Synchronization Channel Control Register Bits */ | 103 | /* 0x40 Time Synchronization Channel Control Register Bits */ |
107 | #define MASTER_MODE (1<<0) | 104 | #define MASTER_MODE (1<<0) |
108 | #define SLAVE_MODE (0<<0) | 105 | #define SLAVE_MODE (0) |
109 | #define V2_MODE (1<<31) | 106 | #define V2_MODE (1<<31) |
110 | #define CAP_MODE0 (0<<16) | 107 | #define CAP_MODE0 (0) |
111 | #define CAP_MODE2 (1<<17) | 108 | #define CAP_MODE2 (1<<17) |
112 | 109 | ||
113 | /* 0x44 Time Synchronization Channel Event Register Bits */ | 110 | /* 0x44 Time Synchronization Channel Event Register Bits */ |
114 | #define TX_SNAPSHOT_LOCKED (1<<0) | 111 | #define TX_SNAPSHOT_LOCKED (1<<0) |
115 | #define RX_SNAPSHOT_LOCKED (1<<1) | 112 | #define RX_SNAPSHOT_LOCKED (1<<1) |
113 | |||
114 | #define PTP_L4_MULTICAST_SA "01:00:5e:00:01:81" | ||
115 | #define PTP_L2_MULTICAST_SA "01:1b:19:00:00:00" | ||
116 | #endif | 116 | #endif |
117 | 117 | ||
118 | static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; | 118 | static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; |
@@ -120,6 +120,7 @@ static unsigned int copybreak __read_mostly = PCH_GBE_COPYBREAK_DEFAULT; | |||
120 | static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg); | 120 | static int pch_gbe_mdio_read(struct net_device *netdev, int addr, int reg); |
121 | static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg, | 121 | static void pch_gbe_mdio_write(struct net_device *netdev, int addr, int reg, |
122 | int data); | 122 | int data); |
123 | static void pch_gbe_set_multi(struct net_device *netdev); | ||
123 | 124 | ||
124 | #ifdef CONFIG_PCH_PTP | 125 | #ifdef CONFIG_PCH_PTP |
125 | static struct sock_filter ptp_filter[] = { | 126 | static struct sock_filter ptp_filter[] = { |
@@ -133,10 +134,8 @@ static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) | |||
133 | u16 *hi, *id; | 134 | u16 *hi, *id; |
134 | u32 lo; | 135 | u32 lo; |
135 | 136 | ||
136 | if ((sk_run_filter(skb, ptp_filter) != PTP_CLASS_V2_IPV4) && | 137 | if (sk_run_filter(skb, ptp_filter) == PTP_CLASS_NONE) |
137 | (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)) { | ||
138 | return 0; | 138 | return 0; |
139 | } | ||
140 | 139 | ||
141 | offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; | 140 | offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN; |
142 | 141 | ||
@@ -153,8 +152,8 @@ static int pch_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid) | |||
153 | seqid == *id); | 152 | seqid == *id); |
154 | } | 153 | } |
155 | 154 | ||
156 | static void pch_rx_timestamp( | 155 | static void |
157 | struct pch_gbe_adapter *adapter, struct sk_buff *skb) | 156 | pch_rx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) |
158 | { | 157 | { |
159 | struct skb_shared_hwtstamps *shhwtstamps; | 158 | struct skb_shared_hwtstamps *shhwtstamps; |
160 | struct pci_dev *pdev; | 159 | struct pci_dev *pdev; |
@@ -183,7 +182,6 @@ static void pch_rx_timestamp( | |||
183 | goto out; | 182 | goto out; |
184 | 183 | ||
185 | ns = pch_rx_snap_read(pdev); | 184 | ns = pch_rx_snap_read(pdev); |
186 | ns <<= TICKS_NS_SHIFT; | ||
187 | 185 | ||
188 | shhwtstamps = skb_hwtstamps(skb); | 186 | shhwtstamps = skb_hwtstamps(skb); |
189 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); | 187 | memset(shhwtstamps, 0, sizeof(*shhwtstamps)); |
@@ -192,8 +190,8 @@ out: | |||
192 | pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED); | 190 | pch_ch_event_write(pdev, RX_SNAPSHOT_LOCKED); |
193 | } | 191 | } |
194 | 192 | ||
195 | static void pch_tx_timestamp( | 193 | static void |
196 | struct pch_gbe_adapter *adapter, struct sk_buff *skb) | 194 | pch_tx_timestamp(struct pch_gbe_adapter *adapter, struct sk_buff *skb) |
197 | { | 195 | { |
198 | struct skb_shared_hwtstamps shhwtstamps; | 196 | struct skb_shared_hwtstamps shhwtstamps; |
199 | struct pci_dev *pdev; | 197 | struct pci_dev *pdev; |
@@ -202,17 +200,16 @@ static void pch_tx_timestamp( | |||
202 | u32 cnt, val; | 200 | u32 cnt, val; |
203 | 201 | ||
204 | shtx = skb_shinfo(skb); | 202 | shtx = skb_shinfo(skb); |
205 | if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en)) | 203 | if (likely(!(shtx->tx_flags & SKBTX_HW_TSTAMP && adapter->hwts_tx_en))) |
206 | shtx->tx_flags |= SKBTX_IN_PROGRESS; | ||
207 | else | ||
208 | return; | 204 | return; |
209 | 205 | ||
206 | shtx->tx_flags |= SKBTX_IN_PROGRESS; | ||
207 | |||
210 | /* Get ieee1588's dev information */ | 208 | /* Get ieee1588's dev information */ |
211 | pdev = adapter->ptp_pdev; | 209 | pdev = adapter->ptp_pdev; |
212 | 210 | ||
213 | /* | 211 | /* |
214 | * This really stinks, but we have to poll for the Tx time stamp. | 212 | * This really stinks, but we have to poll for the Tx time stamp. |
215 | * Usually, the time stamp is ready after 4 to 6 microseconds. | ||
216 | */ | 213 | */ |
217 | for (cnt = 0; cnt < 100; cnt++) { | 214 | for (cnt = 0; cnt < 100; cnt++) { |
218 | val = pch_ch_event_read(pdev); | 215 | val = pch_ch_event_read(pdev); |
@@ -226,7 +223,6 @@ static void pch_tx_timestamp( | |||
226 | } | 223 | } |
227 | 224 | ||
228 | ns = pch_tx_snap_read(pdev); | 225 | ns = pch_tx_snap_read(pdev); |
229 | ns <<= TICKS_NS_SHIFT; | ||
230 | 226 | ||
231 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); | 227 | memset(&shhwtstamps, 0, sizeof(shhwtstamps)); |
232 | shhwtstamps.hwtstamp = ns_to_ktime(ns); | 228 | shhwtstamps.hwtstamp = ns_to_ktime(ns); |
@@ -240,6 +236,7 @@ static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |||
240 | struct hwtstamp_config cfg; | 236 | struct hwtstamp_config cfg; |
241 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); | 237 | struct pch_gbe_adapter *adapter = netdev_priv(netdev); |
242 | struct pci_dev *pdev; | 238 | struct pci_dev *pdev; |
239 | u8 station[20]; | ||
243 | 240 | ||
244 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) | 241 | if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) |
245 | return -EFAULT; | 242 | return -EFAULT; |
@@ -267,15 +264,23 @@ static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) | |||
267 | break; | 264 | break; |
268 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: | 265 | case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: |
269 | adapter->hwts_rx_en = 0; | 266 | adapter->hwts_rx_en = 0; |
270 | pch_ch_control_write(pdev, (SLAVE_MODE | CAP_MODE0)); | 267 | pch_ch_control_write(pdev, SLAVE_MODE | CAP_MODE0); |
271 | break; | 268 | break; |
272 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: | 269 | case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: |
273 | adapter->hwts_rx_en = 1; | 270 | adapter->hwts_rx_en = 1; |
274 | pch_ch_control_write(pdev, (MASTER_MODE | CAP_MODE0)); | 271 | pch_ch_control_write(pdev, MASTER_MODE | CAP_MODE0); |
272 | break; | ||
273 | case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: | ||
274 | adapter->hwts_rx_en = 1; | ||
275 | pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); | ||
276 | strcpy(station, PTP_L4_MULTICAST_SA); | ||
277 | pch_set_station_address(station, pdev); | ||
275 | break; | 278 | break; |
276 | case HWTSTAMP_FILTER_PTP_V2_EVENT: | 279 | case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: |
277 | adapter->hwts_rx_en = 1; | 280 | adapter->hwts_rx_en = 1; |
278 | pch_ch_control_write(pdev, (V2_MODE | CAP_MODE2)); | 281 | pch_ch_control_write(pdev, V2_MODE | CAP_MODE2); |
282 | strcpy(station, PTP_L2_MULTICAST_SA); | ||
283 | pch_set_station_address(station, pdev); | ||
279 | break; | 284 | break; |
280 | default: | 285 | default: |
281 | return -ERANGE; | 286 | return -ERANGE; |
@@ -399,18 +404,18 @@ static void pch_gbe_mac_reset_hw(struct pch_gbe_hw *hw) | |||
399 | iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); | 404 | iowrite32(PCH_GBE_MODE_GMII_ETHER, &hw->reg->MODE); |
400 | #endif | 405 | #endif |
401 | pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); | 406 | pch_gbe_wait_clr_bit(&hw->reg->RESET, PCH_GBE_ALL_RST); |
402 | /* Setup the receive address */ | 407 | /* Setup the receive addresses */ |
403 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); | 408 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); |
404 | return; | 409 | return; |
405 | } | 410 | } |
406 | 411 | ||
407 | static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw) | 412 | static void pch_gbe_mac_reset_rx(struct pch_gbe_hw *hw) |
408 | { | 413 | { |
409 | /* Read the MAC address. and store to the private data */ | 414 | /* Read the MAC addresses. and store to the private data */ |
410 | pch_gbe_mac_read_mac_addr(hw); | 415 | pch_gbe_mac_read_mac_addr(hw); |
411 | iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET); | 416 | iowrite32(PCH_GBE_RX_RST, &hw->reg->RESET); |
412 | pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST); | 417 | pch_gbe_wait_clr_bit_irq(&hw->reg->RESET, PCH_GBE_RX_RST); |
413 | /* Setup the MAC address */ | 418 | /* Setup the MAC addresses */ |
414 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); | 419 | pch_gbe_mac_mar_set(hw, hw->mac.addr, 0); |
415 | return; | 420 | return; |
416 | } | 421 | } |
@@ -460,7 +465,7 @@ static void pch_gbe_mac_mc_addr_list_update(struct pch_gbe_hw *hw, | |||
460 | if (mc_addr_count) { | 465 | if (mc_addr_count) { |
461 | pch_gbe_mac_mar_set(hw, mc_addr_list, i); | 466 | pch_gbe_mac_mar_set(hw, mc_addr_list, i); |
462 | mc_addr_count--; | 467 | mc_addr_count--; |
463 | mc_addr_list += PCH_GBE_ETH_ALEN; | 468 | mc_addr_list += ETH_ALEN; |
464 | } else { | 469 | } else { |
465 | /* Clear MAC address mask */ | 470 | /* Clear MAC address mask */ |
466 | adrmask = ioread32(&hw->reg->ADDR_MASK); | 471 | adrmask = ioread32(&hw->reg->ADDR_MASK); |
@@ -775,6 +780,8 @@ void pch_gbe_reinit_locked(struct pch_gbe_adapter *adapter) | |||
775 | void pch_gbe_reset(struct pch_gbe_adapter *adapter) | 780 | void pch_gbe_reset(struct pch_gbe_adapter *adapter) |
776 | { | 781 | { |
777 | pch_gbe_mac_reset_hw(&adapter->hw); | 782 | pch_gbe_mac_reset_hw(&adapter->hw); |
783 | /* reprogram multicast address register after reset */ | ||
784 | pch_gbe_set_multi(adapter->netdev); | ||
778 | /* Setup the receive address. */ | 785 | /* Setup the receive address. */ |
779 | pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES); | 786 | pch_gbe_mac_init_rx_addrs(&adapter->hw, PCH_GBE_MAR_ENTRIES); |
780 | if (pch_gbe_hal_init_hw(&adapter->hw)) | 787 | if (pch_gbe_hal_init_hw(&adapter->hw)) |
@@ -1178,8 +1185,6 @@ static void pch_gbe_tx_queue(struct pch_gbe_adapter *adapter, | |||
1178 | if (skb->protocol == htons(ETH_P_IP)) { | 1185 | if (skb->protocol == htons(ETH_P_IP)) { |
1179 | struct iphdr *iph = ip_hdr(skb); | 1186 | struct iphdr *iph = ip_hdr(skb); |
1180 | unsigned int offset; | 1187 | unsigned int offset; |
1181 | iph->check = 0; | ||
1182 | iph->check = ip_fast_csum((u8 *) iph, iph->ihl); | ||
1183 | offset = skb_transport_offset(skb); | 1188 | offset = skb_transport_offset(skb); |
1184 | if (iph->protocol == IPPROTO_TCP) { | 1189 | if (iph->protocol == IPPROTO_TCP) { |
1185 | skb->csum = 0; | 1190 | skb->csum = 0; |
@@ -1338,6 +1343,8 @@ static void pch_gbe_stop_receive(struct pch_gbe_adapter *adapter) | |||
1338 | /* Stop Receive */ | 1343 | /* Stop Receive */ |
1339 | pch_gbe_mac_reset_rx(hw); | 1344 | pch_gbe_mac_reset_rx(hw); |
1340 | } | 1345 | } |
1346 | /* reprogram multicast address register after reset */ | ||
1347 | pch_gbe_set_multi(adapter->netdev); | ||
1341 | } | 1348 | } |
1342 | 1349 | ||
1343 | static void pch_gbe_start_receive(struct pch_gbe_hw *hw) | 1350 | static void pch_gbe_start_receive(struct pch_gbe_hw *hw) |
@@ -1922,7 +1929,6 @@ static int pch_gbe_request_irq(struct pch_gbe_adapter *adapter) | |||
1922 | } | 1929 | } |
1923 | 1930 | ||
1924 | 1931 | ||
1925 | static void pch_gbe_set_multi(struct net_device *netdev); | ||
1926 | /** | 1932 | /** |
1927 | * pch_gbe_up - Up GbE network device | 1933 | * pch_gbe_up - Up GbE network device |
1928 | * @adapter: Board private structure | 1934 | * @adapter: Board private structure |