diff options
Diffstat (limited to 'drivers/net/ethernet/intel/e1000e/ich8lan.h')
-rw-r--r-- | drivers/net/ethernet/intel/e1000e/ich8lan.h | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/ich8lan.h b/drivers/net/ethernet/intel/e1000e/ich8lan.h index 8bf4655c2e17..80034a2b297c 100644 --- a/drivers/net/ethernet/intel/e1000e/ich8lan.h +++ b/drivers/net/ethernet/intel/e1000e/ich8lan.h | |||
@@ -211,7 +211,8 @@ | |||
211 | #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ | 211 | #define I82579_MSE_THRESHOLD 0x084F /* 82579 Mean Square Error Threshold */ |
212 | #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ | 212 | #define I82577_MSE_THRESHOLD 0x0887 /* 82577 Mean Square Error Threshold */ |
213 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ | 213 | #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ |
214 | #define I82579_EEE_PCS_STATUS 0x182D /* IEEE MMD Register 3.1 >> 8 */ | 214 | #define I82579_RX_CONFIG 0x3412 /* Receive configuration */ |
215 | #define I82579_EEE_PCS_STATUS 0x182E /* IEEE MMD Register 3.1 >> 8 */ | ||
215 | #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ | 216 | #define I82579_EEE_CAPABILITY 0x0410 /* IEEE MMD Register 3.20 */ |
216 | #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ | 217 | #define I82579_EEE_ADVERTISEMENT 0x040E /* IEEE MMD Register 7.60 */ |
217 | #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ | 218 | #define I82579_EEE_LP_ABILITY 0x040F /* IEEE MMD Register 7.61 */ |
@@ -249,13 +250,6 @@ | |||
249 | /* Proprietary Latency Tolerance Reporting PCI Capability */ | 250 | /* Proprietary Latency Tolerance Reporting PCI Capability */ |
250 | #define E1000_PCI_LTR_CAP_LPT 0xA8 | 251 | #define E1000_PCI_LTR_CAP_LPT 0xA8 |
251 | 252 | ||
252 | /* OBFF Control & Threshold Defines */ | ||
253 | #define E1000_SVCR_OFF_EN 0x00000001 | ||
254 | #define E1000_SVCR_OFF_MASKINT 0x00001000 | ||
255 | #define E1000_SVCR_OFF_TIMER_MASK 0xFFFF0000 | ||
256 | #define E1000_SVCR_OFF_TIMER_SHIFT 16 | ||
257 | #define E1000_SVT_OFF_HWM_MASK 0x0000001F | ||
258 | |||
259 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); | 253 | void e1000e_write_protect_nvm_ich8lan(struct e1000_hw *hw); |
260 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, | 254 | void e1000e_set_kmrn_lock_loss_workaround_ich8lan(struct e1000_hw *hw, |
261 | bool state); | 255 | bool state); |
@@ -267,4 +261,5 @@ s32 e1000_configure_k1_ich8lan(struct e1000_hw *hw, bool k1_enable); | |||
267 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); | 261 | void e1000_copy_rx_addrs_to_phy_ich8lan(struct e1000_hw *hw); |
268 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); | 262 | s32 e1000_lv_jumbo_workaround_ich8lan(struct e1000_hw *hw, bool enable); |
269 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); | 263 | s32 e1000_read_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 *data); |
264 | s32 e1000_write_emi_reg_locked(struct e1000_hw *hw, u16 addr, u16 data); | ||
270 | #endif /* _E1000E_ICH8LAN_H_ */ | 265 | #endif /* _E1000E_ICH8LAN_H_ */ |