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path: root/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
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Diffstat (limited to 'drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c')
-rw-r--r--drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c96
1 files changed, 80 insertions, 16 deletions
diff --git a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
index 116c49736763..47b70949bf3a 100644
--- a/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
+++ b/drivers/gpu/drm/vmwgfx/vmwgfx_ioctl.c
@@ -29,12 +29,18 @@
29#include <drm/vmwgfx_drm.h> 29#include <drm/vmwgfx_drm.h>
30#include "vmwgfx_kms.h" 30#include "vmwgfx_kms.h"
31 31
32struct svga_3d_compat_cap {
33 SVGA3dCapsRecordHeader header;
34 SVGA3dCapPair pairs[SVGA3D_DEVCAP_MAX];
35};
36
32int vmw_getparam_ioctl(struct drm_device *dev, void *data, 37int vmw_getparam_ioctl(struct drm_device *dev, void *data,
33 struct drm_file *file_priv) 38 struct drm_file *file_priv)
34{ 39{
35 struct vmw_private *dev_priv = vmw_priv(dev); 40 struct vmw_private *dev_priv = vmw_priv(dev);
36 struct drm_vmw_getparam_arg *param = 41 struct drm_vmw_getparam_arg *param =
37 (struct drm_vmw_getparam_arg *)data; 42 (struct drm_vmw_getparam_arg *)data;
43 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
38 44
39 switch (param->param) { 45 switch (param->param) {
40 case DRM_VMW_PARAM_NUM_STREAMS: 46 case DRM_VMW_PARAM_NUM_STREAMS:
@@ -60,6 +66,11 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
60 __le32 __iomem *fifo_mem = dev_priv->mmio_virt; 66 __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
61 const struct vmw_fifo_state *fifo = &dev_priv->fifo; 67 const struct vmw_fifo_state *fifo = &dev_priv->fifo;
62 68
69 if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS)) {
70 param->value = SVGA3D_HWVERSION_WS8_B1;
71 break;
72 }
73
63 param->value = 74 param->value =
64 ioread32(fifo_mem + 75 ioread32(fifo_mem +
65 ((fifo->capabilities & 76 ((fifo->capabilities &
@@ -69,19 +80,31 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
69 break; 80 break;
70 } 81 }
71 case DRM_VMW_PARAM_MAX_SURF_MEMORY: 82 case DRM_VMW_PARAM_MAX_SURF_MEMORY:
72 param->value = dev_priv->memory_size; 83 if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS) &&
84 !vmw_fp->gb_aware)
85 param->value = dev_priv->max_mob_pages * PAGE_SIZE / 2;
86 else
87 param->value = dev_priv->memory_size;
73 break; 88 break;
74 case DRM_VMW_PARAM_3D_CAPS_SIZE: 89 case DRM_VMW_PARAM_3D_CAPS_SIZE:
75 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 90 if ((dev_priv->capabilities & SVGA_CAP_GBOBJECTS) &&
76 param->value = SVGA3D_DEVCAP_MAX; 91 vmw_fp->gb_aware)
92 param->value = SVGA3D_DEVCAP_MAX * sizeof(uint32_t);
93 else if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS)
94 param->value = sizeof(struct svga_3d_compat_cap) +
95 sizeof(uint32_t);
77 else 96 else
78 param->value = (SVGA_FIFO_3D_CAPS_LAST - 97 param->value = (SVGA_FIFO_3D_CAPS_LAST -
79 SVGA_FIFO_3D_CAPS + 1); 98 SVGA_FIFO_3D_CAPS + 1) *
80 param->value *= sizeof(uint32_t); 99 sizeof(uint32_t);
81 break; 100 break;
82 case DRM_VMW_PARAM_MAX_MOB_MEMORY: 101 case DRM_VMW_PARAM_MAX_MOB_MEMORY:
102 vmw_fp->gb_aware = true;
83 param->value = dev_priv->max_mob_pages * PAGE_SIZE; 103 param->value = dev_priv->max_mob_pages * PAGE_SIZE;
84 break; 104 break;
105 case DRM_VMW_PARAM_MAX_MOB_SIZE:
106 param->value = dev_priv->max_mob_size;
107 break;
85 default: 108 default:
86 DRM_ERROR("Illegal vmwgfx get param request: %d\n", 109 DRM_ERROR("Illegal vmwgfx get param request: %d\n",
87 param->param); 110 param->param);
@@ -91,6 +114,38 @@ int vmw_getparam_ioctl(struct drm_device *dev, void *data,
91 return 0; 114 return 0;
92} 115}
93 116
117static int vmw_fill_compat_cap(struct vmw_private *dev_priv, void *bounce,
118 size_t size)
119{
120 struct svga_3d_compat_cap *compat_cap =
121 (struct svga_3d_compat_cap *) bounce;
122 unsigned int i;
123 size_t pair_offset = offsetof(struct svga_3d_compat_cap, pairs);
124 unsigned int max_size;
125
126 if (size < pair_offset)
127 return -EINVAL;
128
129 max_size = (size - pair_offset) / sizeof(SVGA3dCapPair);
130
131 if (max_size > SVGA3D_DEVCAP_MAX)
132 max_size = SVGA3D_DEVCAP_MAX;
133
134 compat_cap->header.length =
135 (pair_offset + max_size * sizeof(SVGA3dCapPair)) / sizeof(u32);
136 compat_cap->header.type = SVGA3DCAPS_RECORD_DEVCAPS;
137
138 mutex_lock(&dev_priv->hw_mutex);
139 for (i = 0; i < max_size; ++i) {
140 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);
141 compat_cap->pairs[i][0] = i;
142 compat_cap->pairs[i][1] = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
143 }
144 mutex_unlock(&dev_priv->hw_mutex);
145
146 return 0;
147}
148
94 149
95int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data, 150int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv) 151 struct drm_file *file_priv)
@@ -104,41 +159,49 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data,
104 void *bounce; 159 void *bounce;
105 int ret; 160 int ret;
106 bool gb_objects = !!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS); 161 bool gb_objects = !!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS);
162 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv);
107 163
108 if (unlikely(arg->pad64 != 0)) { 164 if (unlikely(arg->pad64 != 0)) {
109 DRM_ERROR("Illegal GET_3D_CAP argument.\n"); 165 DRM_ERROR("Illegal GET_3D_CAP argument.\n");
110 return -EINVAL; 166 return -EINVAL;
111 } 167 }
112 168
113 if (gb_objects) 169 if (gb_objects && vmw_fp->gb_aware)
114 size = SVGA3D_DEVCAP_MAX; 170 size = SVGA3D_DEVCAP_MAX * sizeof(uint32_t);
171 else if (gb_objects)
172 size = sizeof(struct svga_3d_compat_cap) + sizeof(uint32_t);
115 else 173 else
116 size = (SVGA_FIFO_3D_CAPS_LAST - SVGA_FIFO_3D_CAPS + 1); 174 size = (SVGA_FIFO_3D_CAPS_LAST - SVGA_FIFO_3D_CAPS + 1) *
117 175 sizeof(uint32_t);
118 size *= sizeof(uint32_t);
119 176
120 if (arg->max_size < size) 177 if (arg->max_size < size)
121 size = arg->max_size; 178 size = arg->max_size;
122 179
123 bounce = vmalloc(size); 180 bounce = vzalloc(size);
124 if (unlikely(bounce == NULL)) { 181 if (unlikely(bounce == NULL)) {
125 DRM_ERROR("Failed to allocate bounce buffer for 3D caps.\n"); 182 DRM_ERROR("Failed to allocate bounce buffer for 3D caps.\n");
126 return -ENOMEM; 183 return -ENOMEM;
127 } 184 }
128 185
129 if (gb_objects) { 186 if (gb_objects && vmw_fp->gb_aware) {
130 int i; 187 int i, num;
131 uint32_t *bounce32 = (uint32_t *) bounce; 188 uint32_t *bounce32 = (uint32_t *) bounce;
132 189
190 num = size / sizeof(uint32_t);
191 if (num > SVGA3D_DEVCAP_MAX)
192 num = SVGA3D_DEVCAP_MAX;
193
133 mutex_lock(&dev_priv->hw_mutex); 194 mutex_lock(&dev_priv->hw_mutex);
134 for (i = 0; i < SVGA3D_DEVCAP_MAX; ++i) { 195 for (i = 0; i < num; ++i) {
135 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); 196 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i);
136 *bounce32++ = vmw_read(dev_priv, SVGA_REG_DEV_CAP); 197 *bounce32++ = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
137 } 198 }
138 mutex_unlock(&dev_priv->hw_mutex); 199 mutex_unlock(&dev_priv->hw_mutex);
139 200 } else if (gb_objects) {
201 ret = vmw_fill_compat_cap(dev_priv, bounce, size);
202 if (unlikely(ret != 0))
203 goto out_err;
140 } else { 204 } else {
141
142 fifo_mem = dev_priv->mmio_virt; 205 fifo_mem = dev_priv->mmio_virt;
143 memcpy_fromio(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size); 206 memcpy_fromio(bounce, &fifo_mem[SVGA_FIFO_3D_CAPS], size);
144 } 207 }
@@ -146,6 +209,7 @@ int vmw_get_cap_3d_ioctl(struct drm_device *dev, void *data,
146 ret = copy_to_user(buffer, bounce, size); 209 ret = copy_to_user(buffer, bounce, size);
147 if (ret) 210 if (ret)
148 ret = -EFAULT; 211 ret = -EFAULT;
212out_err:
149 vfree(bounce); 213 vfree(bounce);
150 214
151 if (unlikely(ret != 0)) 215 if (unlikely(ret != 0))