diff options
Diffstat (limited to 'drivers/gpio/gpio-omap.c')
-rw-r--r-- | drivers/gpio/gpio-omap.c | 74 |
1 files changed, 30 insertions, 44 deletions
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 6afca28a8c67..e5667baf5004 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c | |||
@@ -877,45 +877,8 @@ static struct irq_chip gpio_irq_chip = { | |||
877 | 877 | ||
878 | #ifdef CONFIG_ARCH_OMAP1 | 878 | #ifdef CONFIG_ARCH_OMAP1 |
879 | 879 | ||
880 | /* MPUIO uses the always-on 32k clock */ | ||
881 | |||
882 | static void mpuio_ack_irq(struct irq_data *d) | ||
883 | { | ||
884 | /* The ISR is reset automatically, so do nothing here. */ | ||
885 | } | ||
886 | |||
887 | static void mpuio_mask_irq(struct irq_data *d) | ||
888 | { | ||
889 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | ||
890 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | ||
891 | |||
892 | _set_gpio_irqenable(bank, gpio, 0); | ||
893 | } | ||
894 | |||
895 | static void mpuio_unmask_irq(struct irq_data *d) | ||
896 | { | ||
897 | unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); | ||
898 | struct gpio_bank *bank = irq_data_get_irq_chip_data(d); | ||
899 | |||
900 | _set_gpio_irqenable(bank, gpio, 1); | ||
901 | } | ||
902 | |||
903 | static struct irq_chip mpuio_irq_chip = { | ||
904 | .name = "MPUIO", | ||
905 | .irq_ack = mpuio_ack_irq, | ||
906 | .irq_mask = mpuio_mask_irq, | ||
907 | .irq_unmask = mpuio_unmask_irq, | ||
908 | .irq_set_type = gpio_irq_type, | ||
909 | #ifdef CONFIG_ARCH_OMAP16XX | ||
910 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | ||
911 | .irq_set_wake = gpio_wake_enable, | ||
912 | #endif | ||
913 | }; | ||
914 | |||
915 | |||
916 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) | 880 | #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) |
917 | 881 | ||
918 | |||
919 | #ifdef CONFIG_ARCH_OMAP16XX | 882 | #ifdef CONFIG_ARCH_OMAP16XX |
920 | 883 | ||
921 | #include <linux/platform_device.h> | 884 | #include <linux/platform_device.h> |
@@ -988,8 +951,6 @@ static inline void mpuio_init(void) {} | |||
988 | 951 | ||
989 | #else | 952 | #else |
990 | 953 | ||
991 | extern struct irq_chip mpuio_irq_chip; | ||
992 | |||
993 | #define bank_is_mpuio(bank) 0 | 954 | #define bank_is_mpuio(bank) 0 |
994 | static inline void mpuio_init(void) {} | 955 | static inline void mpuio_init(void) {} |
995 | 956 | ||
@@ -1189,6 +1150,30 @@ static void omap_gpio_mod_init(struct gpio_bank *bank, int id) | |||
1189 | } | 1150 | } |
1190 | } | 1151 | } |
1191 | 1152 | ||
1153 | static __init void | ||
1154 | omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, | ||
1155 | unsigned int num) | ||
1156 | { | ||
1157 | struct irq_chip_generic *gc; | ||
1158 | struct irq_chip_type *ct; | ||
1159 | |||
1160 | gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, | ||
1161 | handle_simple_irq); | ||
1162 | ct = gc->chip_types; | ||
1163 | |||
1164 | /* NOTE: No ack required, reading IRQ status clears it. */ | ||
1165 | ct->chip.irq_mask = irq_gc_mask_set_bit; | ||
1166 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | ||
1167 | ct->chip.irq_set_type = gpio_irq_type; | ||
1168 | /* REVISIT: assuming only 16xx supports MPUIO wake events */ | ||
1169 | if (cpu_is_omap16xx()) | ||
1170 | ct->chip.irq_set_wake = gpio_wake_enable, | ||
1171 | |||
1172 | ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; | ||
1173 | irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, | ||
1174 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | ||
1175 | } | ||
1176 | |||
1192 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) | 1177 | static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) |
1193 | { | 1178 | { |
1194 | int j; | 1179 | int j; |
@@ -1226,12 +1211,13 @@ static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) | |||
1226 | j < bank->virtual_irq_start + bank->width; j++) { | 1211 | j < bank->virtual_irq_start + bank->width; j++) { |
1227 | irq_set_lockdep_class(j, &gpio_lock_class); | 1212 | irq_set_lockdep_class(j, &gpio_lock_class); |
1228 | irq_set_chip_data(j, bank); | 1213 | irq_set_chip_data(j, bank); |
1229 | if (bank_is_mpuio(bank)) | 1214 | if (bank_is_mpuio(bank)) { |
1230 | irq_set_chip(j, &mpuio_irq_chip); | 1215 | omap_mpuio_alloc_gc(bank, j, bank->width); |
1231 | else | 1216 | } else { |
1232 | irq_set_chip(j, &gpio_irq_chip); | 1217 | irq_set_chip(j, &gpio_irq_chip); |
1233 | irq_set_handler(j, handle_simple_irq); | 1218 | irq_set_handler(j, handle_simple_irq); |
1234 | set_irq_flags(j, IRQF_VALID); | 1219 | set_irq_flags(j, IRQF_VALID); |
1220 | } | ||
1235 | } | 1221 | } |
1236 | irq_set_chained_handler(bank->irq, gpio_irq_handler); | 1222 | irq_set_chained_handler(bank->irq, gpio_irq_handler); |
1237 | irq_set_handler_data(bank->irq, bank); | 1223 | irq_set_handler_data(bank->irq, bank); |