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path: root/drivers/clk/sunxi
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-rw-r--r--drivers/clk/sunxi/clk-sunxi.c11
1 files changed, 9 insertions, 2 deletions
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index 46d98e3b98ba..d46949372762 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -906,6 +906,7 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
906 906
907struct divs_data { 907struct divs_data {
908 const struct factors_data *factors; /* data for the factor clock */ 908 const struct factors_data *factors; /* data for the factor clock */
909 int ndivs; /* number of children */
909 struct { 910 struct {
910 u8 fixed; /* is it a fixed divisor? if not... */ 911 u8 fixed; /* is it a fixed divisor? if not... */
911 struct clk_div_table *table; /* is it a table based divisor? */ 912 struct clk_div_table *table; /* is it a table based divisor? */
@@ -925,6 +926,7 @@ static struct clk_div_table pll6_sata_tbl[] = {
925 926
926static const struct divs_data pll5_divs_data __initconst = { 927static const struct divs_data pll5_divs_data __initconst = {
927 .factors = &sun4i_pll5_data, 928 .factors = &sun4i_pll5_data,
929 .ndivs = 2,
928 .div = { 930 .div = {
929 { .shift = 0, .pow = 0, }, /* M, DDR */ 931 { .shift = 0, .pow = 0, }, /* M, DDR */
930 { .shift = 16, .pow = 1, }, /* P, other */ 932 { .shift = 16, .pow = 1, }, /* P, other */
@@ -933,6 +935,7 @@ static const struct divs_data pll5_divs_data __initconst = {
933 935
934static const struct divs_data pll6_divs_data __initconst = { 936static const struct divs_data pll6_divs_data __initconst = {
935 .factors = &sun4i_pll6_data, 937 .factors = &sun4i_pll6_data,
938 .ndivs = 2,
936 .div = { 939 .div = {
937 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */ 940 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
938 { .fixed = 2 }, /* P, other */ 941 { .fixed = 2 }, /* P, other */
@@ -963,7 +966,7 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
963 struct clk_fixed_factor *fix_factor; 966 struct clk_fixed_factor *fix_factor;
964 struct clk_divider *divider; 967 struct clk_divider *divider;
965 void __iomem *reg; 968 void __iomem *reg;
966 int i = 0; 969 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
967 int flags, clkflags; 970 int flags, clkflags;
968 971
969 /* Set up factor clock that we will be dividing */ 972 /* Set up factor clock that we will be dividing */
@@ -986,7 +989,11 @@ static void __init sunxi_divs_clk_setup(struct device_node *node,
986 * our RAM clock! */ 989 * our RAM clock! */
987 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT; 990 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
988 991
989 for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) { 992 /* if number of children known, use it */
993 if (data->ndivs)
994 ndivs = data->ndivs;
995
996 for (i = 0; i < ndivs; i++) {
990 if (of_property_read_string_index(node, "clock-output-names", 997 if (of_property_read_string_index(node, "clock-output-names",
991 i, &clk_name) != 0) 998 i, &clk_name) != 0)
992 break; 999 break;