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-rw-r--r--arch/mips/alchemy/pb1200/Makefile8
-rw-r--r--arch/mips/alchemy/pb1200/board_setup.c162
-rw-r--r--arch/mips/alchemy/pb1200/init.c58
-rw-r--r--arch/mips/alchemy/pb1200/irqmap.c160
-rw-r--r--arch/mips/alchemy/pb1200/platform.c85
5 files changed, 473 insertions, 0 deletions
diff --git a/arch/mips/alchemy/pb1200/Makefile b/arch/mips/alchemy/pb1200/Makefile
new file mode 100644
index 000000000000..d678adf7ce85
--- /dev/null
+++ b/arch/mips/alchemy/pb1200/Makefile
@@ -0,0 +1,8 @@
1#
2# Makefile for the Alchemy Semiconductor Pb1200/DBAu1200 boards.
3#
4
5lib-y := init.o board_setup.o irqmap.o
6obj-y += platform.o
7
8EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/alchemy/pb1200/board_setup.c b/arch/mips/alchemy/pb1200/board_setup.c
new file mode 100644
index 000000000000..6cb2115059ad
--- /dev/null
+++ b/arch/mips/alchemy/pb1200/board_setup.c
@@ -0,0 +1,162 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Alchemy Pb1200/Db1200 board setup.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27#include <linux/init.h>
28#include <linux/sched.h>
29
30#include <prom.h>
31#include <au1xxx.h>
32
33extern void _board_init_irq(void);
34extern void (*board_init_irq)(void);
35
36void board_reset(void)
37{
38 bcsr->resets = 0;
39 bcsr->system = 0;
40}
41
42void __init board_setup(void)
43{
44 char *argptr = NULL;
45
46#if 0
47 {
48 u32 pin_func;
49
50 /*
51 * Enable PSC1 SYNC for AC97. Normaly done in audio driver,
52 * but it is board specific code, so put it here.
53 */
54 pin_func = au_readl(SYS_PINFUNC);
55 au_sync();
56 pin_func |= SYS_PF_MUST_BE_SET | SYS_PF_PSC1_S1;
57 au_writel(pin_func, SYS_PINFUNC);
58
59 au_writel(0, (u32)bcsr | 0x10); /* turn off PCMCIA power */
60 au_sync();
61 }
62#endif
63
64#if defined(CONFIG_I2C_AU1550)
65 {
66 u32 freq0, clksrc;
67 u32 pin_func;
68
69 /* Select SMBus in CPLD */
70 bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
71
72 pin_func = au_readl(SYS_PINFUNC);
73 au_sync();
74 pin_func &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B);
75 /* Set GPIOs correctly */
76 pin_func |= 2 << 17;
77 au_writel(pin_func, SYS_PINFUNC);
78 au_sync();
79
80 /* The I2C driver depends on 50 MHz clock */
81 freq0 = au_readl(SYS_FREQCTRL0);
82 au_sync();
83 freq0 &= ~(SYS_FC_FRDIV1_MASK | SYS_FC_FS1 | SYS_FC_FE1);
84 freq0 |= 3 << SYS_FC_FRDIV1_BIT;
85 /* 396 MHz / (3 + 1) * 2 == 49.5 MHz */
86 au_writel(freq0, SYS_FREQCTRL0);
87 au_sync();
88 freq0 |= SYS_FC_FE1;
89 au_writel(freq0, SYS_FREQCTRL0);
90 au_sync();
91
92 clksrc = au_readl(SYS_CLKSRC);
93 au_sync();
94 clksrc &= ~(SYS_CS_CE0 | SYS_CS_DE0 | SYS_CS_ME0_MASK);
95 /* Bit 22 is EXTCLK0 for PSC0 */
96 clksrc |= SYS_CS_MUX_FQ1 << SYS_CS_ME0_BIT;
97 au_writel(clksrc, SYS_CLKSRC);
98 au_sync();
99 }
100#endif
101
102#ifdef CONFIG_FB_AU1200
103 argptr = prom_getcmdline();
104#ifdef CONFIG_MIPS_PB1200
105 strcat(argptr, " video=au1200fb:panel:bs");
106#endif
107#ifdef CONFIG_MIPS_DB1200
108 strcat(argptr, " video=au1200fb:panel:bs");
109#endif
110#endif
111
112 /*
113 * The Pb1200 development board uses external MUX for PSC0 to
114 * support SMB/SPI. bcsr->resets bit 12: 0=SMB 1=SPI
115 */
116#ifdef CONFIG_I2C_AU1550
117 bcsr->resets &= ~BCSR_RESETS_PCS0MUX;
118#endif
119 au_sync();
120
121#ifdef CONFIG_MIPS_PB1200
122 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n");
123#endif
124#ifdef CONFIG_MIPS_DB1200
125 printk(KERN_INFO "AMD Alchemy Db1200 Board\n");
126#endif
127
128 /* Setup Pb1200 External Interrupt Controller */
129 board_init_irq = _board_init_irq;
130}
131
132int board_au1200fb_panel(void)
133{
134 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
135 int p;
136
137 p = bcsr->switches;
138 p >>= 8;
139 p &= 0x0F;
140 return p;
141}
142
143int board_au1200fb_panel_init(void)
144{
145 /* Apply power */
146 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
147
148 bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | BCSR_BOARD_LCDBL;
149 /* printk(KERN_DEBUG "board_au1200fb_panel_init()\n"); */
150 return 0;
151}
152
153int board_au1200fb_panel_shutdown(void)
154{
155 /* Remove power */
156 BCSR *bcsr = (BCSR *)BCSR_KSEG1_ADDR;
157
158 bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD |
159 BCSR_BOARD_LCDBL);
160 /* printk(KERN_DEBUG "board_au1200fb_panel_shutdown()\n"); */
161 return 0;
162}
diff --git a/arch/mips/alchemy/pb1200/init.c b/arch/mips/alchemy/pb1200/init.c
new file mode 100644
index 000000000000..e9b2a0fd48ae
--- /dev/null
+++ b/arch/mips/alchemy/pb1200/init.c
@@ -0,0 +1,58 @@
1/*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * PB1200 board setup
5 *
6 * Copyright 2001, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
29
30#include <linux/init.h>
31#include <linux/kernel.h>
32
33#include <asm/bootinfo.h>
34
35#include <prom.h>
36
37const char *get_system_type(void)
38{
39 return "Alchemy Pb1200";
40}
41
42void __init prom_init(void)
43{
44 unsigned char *memsize_str;
45 unsigned long memsize;
46
47 prom_argc = (int)fw_arg0;
48 prom_argv = (char **)fw_arg1;
49 prom_envp = (char **)fw_arg2;
50
51 prom_init_cmdline();
52 memsize_str = prom_getenv("memsize");
53 if (!memsize_str)
54 memsize = 0x08000000;
55 else
56 strict_strtol(memsize_str, 0, &memsize);
57 add_memory_region(0, memsize, BOOT_MEM_RAM);
58}
diff --git a/arch/mips/alchemy/pb1200/irqmap.c b/arch/mips/alchemy/pb1200/irqmap.c
new file mode 100644
index 000000000000..2a505ad8715b
--- /dev/null
+++ b/arch/mips/alchemy/pb1200/irqmap.c
@@ -0,0 +1,160 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 *
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26#include <linux/init.h>
27#include <linux/interrupt.h>
28
29#include <asm/mach-au1x00/au1000.h>
30
31#ifdef CONFIG_MIPS_PB1200
32#include <asm/mach-pb1x00/pb1200.h>
33#endif
34
35#ifdef CONFIG_MIPS_DB1200
36#include <asm/mach-db1x00/db1200.h>
37#define PB1200_INT_BEGIN DB1200_INT_BEGIN
38#define PB1200_INT_END DB1200_INT_END
39#endif
40
41struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
42 /* This is external interrupt cascade */
43 { AU1000_GPIO_7, INTC_INT_LOW_LEVEL, 0 },
44};
45
46int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
47
48/*
49 * Support for External interrupts on the Pb1200 Development platform.
50 */
51static volatile int pb1200_cascade_en;
52
53irqreturn_t pb1200_cascade_handler(int irq, void *dev_id)
54{
55 unsigned short bisr = bcsr->int_status;
56 int extirq_nr = 0;
57
58 /* Clear all the edge interrupts. This has no effect on level. */
59 bcsr->int_status = bisr;
60 for ( ; bisr; bisr &= bisr - 1) {
61 extirq_nr = PB1200_INT_BEGIN + __ffs(bisr);
62 /* Ack and dispatch IRQ */
63 do_IRQ(extirq_nr);
64 }
65
66 return IRQ_RETVAL(1);
67}
68
69inline void pb1200_enable_irq(unsigned int irq_nr)
70{
71 bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
72 bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN);
73}
74
75inline void pb1200_disable_irq(unsigned int irq_nr)
76{
77 bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN);
78 bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN);
79}
80
81static unsigned int pb1200_setup_cascade(void)
82{
83 return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler,
84 0, "Pb1200 Cascade", &pb1200_cascade_handler);
85}
86
87static unsigned int pb1200_startup_irq(unsigned int irq)
88{
89 if (++pb1200_cascade_en == 1) {
90 int res;
91
92 res = pb1200_setup_cascade();
93 if (res)
94 return res;
95 }
96
97 pb1200_enable_irq(irq);
98
99 return 0;
100}
101
102static void pb1200_shutdown_irq(unsigned int irq)
103{
104 pb1200_disable_irq(irq);
105 if (--pb1200_cascade_en == 0)
106 free_irq(AU1000_GPIO_7, &pb1200_cascade_handler);
107}
108
109static struct irq_chip external_irq_type = {
110#ifdef CONFIG_MIPS_PB1200
111 .name = "Pb1200 Ext",
112#endif
113#ifdef CONFIG_MIPS_DB1200
114 .name = "Db1200 Ext",
115#endif
116 .startup = pb1200_startup_irq,
117 .shutdown = pb1200_shutdown_irq,
118 .ack = pb1200_disable_irq,
119 .mask = pb1200_disable_irq,
120 .mask_ack = pb1200_disable_irq,
121 .unmask = pb1200_enable_irq,
122};
123
124void _board_init_irq(void)
125{
126 unsigned int irq;
127
128#ifdef CONFIG_MIPS_PB1200
129 /* We have a problem with CPLD rev 3. */
130 if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) {
131 printk(KERN_ERR "WARNING!!!\n");
132 printk(KERN_ERR "WARNING!!!\n");
133 printk(KERN_ERR "WARNING!!!\n");
134 printk(KERN_ERR "WARNING!!!\n");
135 printk(KERN_ERR "WARNING!!!\n");
136 printk(KERN_ERR "WARNING!!!\n");
137 printk(KERN_ERR "Pb1200 must be at CPLD rev 4. Please have Pb1200\n");
138 printk(KERN_ERR "updated to latest revision. This software will\n");
139 printk(KERN_ERR "not work on anything less than CPLD rev 4.\n");
140 printk(KERN_ERR "WARNING!!!\n");
141 printk(KERN_ERR "WARNING!!!\n");
142 printk(KERN_ERR "WARNING!!!\n");
143 printk(KERN_ERR "WARNING!!!\n");
144 printk(KERN_ERR "WARNING!!!\n");
145 printk(KERN_ERR "WARNING!!!\n");
146 panic("Game over. Your score is 0.");
147 }
148#endif
149
150 for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) {
151 set_irq_chip_and_handler(irq, &external_irq_type,
152 handle_level_irq);
153 pb1200_disable_irq(irq);
154 }
155
156 /*
157 * GPIO_7 can not be hooked here, so it is hooked upon first
158 * request of any source attached to the cascade.
159 */
160}
diff --git a/arch/mips/alchemy/pb1200/platform.c b/arch/mips/alchemy/pb1200/platform.c
new file mode 100644
index 000000000000..f8fb0aeac571
--- /dev/null
+++ b/arch/mips/alchemy/pb1200/platform.c
@@ -0,0 +1,85 @@
1/*
2 * Pb1200/DBAu1200 board platform device registration
3 *
4 * Copyright (C) 2008 MontaVista Software Inc. <source@mvista.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
19 */
20
21#include <linux/dma-mapping.h>
22#include <linux/init.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach-au1x00/au1xxx.h>
26
27static struct resource ide_resources[] = {
28 [0] = {
29 .start = IDE_PHYS_ADDR,
30 .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1,
31 .flags = IORESOURCE_MEM
32 },
33 [1] = {
34 .start = IDE_INT,
35 .end = IDE_INT,
36 .flags = IORESOURCE_IRQ
37 }
38};
39
40static u64 ide_dmamask = DMA_32BIT_MASK;
41
42static struct platform_device ide_device = {
43 .name = "au1200-ide",
44 .id = 0,
45 .dev = {
46 .dma_mask = &ide_dmamask,
47 .coherent_dma_mask = DMA_32BIT_MASK,
48 },
49 .num_resources = ARRAY_SIZE(ide_resources),
50 .resource = ide_resources
51};
52
53static struct resource smc91c111_resources[] = {
54 [0] = {
55 .name = "smc91x-regs",
56 .start = SMC91C111_PHYS_ADDR,
57 .end = SMC91C111_PHYS_ADDR + 0xf,
58 .flags = IORESOURCE_MEM
59 },
60 [1] = {
61 .start = SMC91C111_INT,
62 .end = SMC91C111_INT,
63 .flags = IORESOURCE_IRQ
64 },
65};
66
67static struct platform_device smc91c111_device = {
68 .name = "smc91x",
69 .id = -1,
70 .num_resources = ARRAY_SIZE(smc91c111_resources),
71 .resource = smc91c111_resources
72};
73
74static struct platform_device *board_platform_devices[] __initdata = {
75 &ide_device,
76 &smc91c111_device
77};
78
79static int __init board_register_devices(void)
80{
81 return platform_add_devices(board_platform_devices,
82 ARRAY_SIZE(board_platform_devices));
83}
84
85arch_initcall(board_register_devices);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-27 08:19:22 -0500