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-rw-r--r--arch/mips/alchemy/common/Makefile4
-rw-r--r--arch/mips/alchemy/common/clock.c1094
-rw-r--r--arch/mips/alchemy/common/clocks.c105
-rw-r--r--arch/mips/alchemy/common/dbdma.c22
-rw-r--r--arch/mips/alchemy/common/dma.c15
-rw-r--r--arch/mips/alchemy/common/irq.c5
-rw-r--r--arch/mips/alchemy/common/platform.c15
-rw-r--r--arch/mips/alchemy/common/power.c74
-rw-r--r--arch/mips/alchemy/common/setup.c15
-rw-r--r--arch/mips/alchemy/common/time.c23
-rw-r--r--arch/mips/alchemy/common/usb.c47
11 files changed, 1216 insertions, 203 deletions
diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile
index cb83d8d21aef..f64744f3b59f 100644
--- a/arch/mips/alchemy/common/Makefile
+++ b/arch/mips/alchemy/common/Makefile
@@ -5,8 +5,8 @@
5# Makefile for the Alchemy Au1xx0 CPUs, generic files. 5# Makefile for the Alchemy Au1xx0 CPUs, generic files.
6# 6#
7 7
8obj-y += prom.o time.o clocks.o platform.o power.o setup.o \ 8obj-y += prom.o time.o clock.o platform.o power.o \
9 sleeper.o dma.o dbdma.o vss.o irq.o usb.o 9 setup.o sleeper.o dma.o dbdma.o vss.o irq.o usb.o
10 10
11# optional gpiolib support 11# optional gpiolib support
12ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) 12ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),)
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
new file mode 100644
index 000000000000..d7557cde271a
--- /dev/null
+++ b/arch/mips/alchemy/common/clock.c
@@ -0,0 +1,1094 @@
1/*
2 * Alchemy clocks.
3 *
4 * Exposes all configurable internal clock sources to the clk framework.
5 *
6 * We have:
7 * - Root source, usually 12MHz supplied by an external crystal
8 * - 3 PLLs which generate multiples of root rate [AUX, CPU, AUX2]
9 *
10 * Dividers:
11 * - 6 clock dividers with:
12 * * selectable source [one of the PLLs],
13 * * output divided between [2 .. 512 in steps of 2] (!Au1300)
14 * or [1 .. 256 in steps of 1] (Au1300),
15 * * can be enabled individually.
16 *
17 * - up to 6 "internal" (fixed) consumers which:
18 * * take either AUXPLL or one of the above 6 dividers as input,
19 * * divide this input by 1, 2, or 4 (and 3 on Au1300).
20 * * can be disabled separately.
21 *
22 * Misc clocks:
23 * - sysbus clock: CPU core clock (CPUPLL) divided by 2, 3 or 4.
24 * depends on board design and should be set by bootloader, read-only.
25 * - peripheral clock: half the rate of sysbus clock, source for a lot
26 * of peripheral blocks, read-only.
27 * - memory clock: clk rate to main memory chips, depends on board
28 * design and is read-only,
29 * - lrclk: the static bus clock signal for synchronous operation.
30 * depends on board design, must be set by bootloader,
31 * but may be required to correctly configure devices attached to
32 * the static bus. The Au1000/1500/1100 manuals call it LCLK, on
33 * later models it's called RCLK.
34 */
35
36#include <linux/init.h>
37#include <linux/io.h>
38#include <linux/clk-provider.h>
39#include <linux/clkdev.h>
40#include <linux/clk-private.h>
41#include <linux/slab.h>
42#include <linux/spinlock.h>
43#include <linux/types.h>
44#include <asm/mach-au1x00/au1000.h>
45
46/* Base clock: 12MHz is the default in all databooks, and I haven't
47 * found any board yet which uses a different rate.
48 */
49#define ALCHEMY_ROOTCLK_RATE 12000000
50
51/*
52 * the internal sources which can be driven by the PLLs and dividers.
53 * Names taken from the databooks, refer to them for more information,
54 * especially which ones are share a clock line.
55 */
56static const char * const alchemy_au1300_intclknames[] = {
57 "lcd_intclk", "gpemgp_clk", "maempe_clk", "maebsa_clk",
58 "EXTCLK0", "EXTCLK1"
59};
60
61static const char * const alchemy_au1200_intclknames[] = {
62 "lcd_intclk", NULL, NULL, NULL, "EXTCLK0", "EXTCLK1"
63};
64
65static const char * const alchemy_au1550_intclknames[] = {
66 "usb_clk", "psc0_intclk", "psc1_intclk", "pci_clko",
67 "EXTCLK0", "EXTCLK1"
68};
69
70static const char * const alchemy_au1100_intclknames[] = {
71 "usb_clk", "lcd_intclk", NULL, "i2s_clk", "EXTCLK0", "EXTCLK1"
72};
73
74static const char * const alchemy_au1500_intclknames[] = {
75 NULL, "usbd_clk", "usbh_clk", "pci_clko", "EXTCLK0", "EXTCLK1"
76};
77
78static const char * const alchemy_au1000_intclknames[] = {
79 "irda_clk", "usbd_clk", "usbh_clk", "i2s_clk", "EXTCLK0",
80 "EXTCLK1"
81};
82
83/* aliases for a few on-chip sources which are either shared
84 * or have gone through name changes.
85 */
86static struct clk_aliastable {
87 char *alias;
88 char *base;
89 int cputype;
90} alchemy_clk_aliases[] __initdata = {
91 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
92 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
93 { "irda_clk", "usb_clk", ALCHEMY_CPU_AU1100 },
94 { "usbh_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
95 { "usbd_clk", "usb_clk", ALCHEMY_CPU_AU1550 },
96 { "psc2_intclk", "usb_clk", ALCHEMY_CPU_AU1550 },
97 { "psc3_intclk", "EXTCLK0", ALCHEMY_CPU_AU1550 },
98 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1200 },
99 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1200 },
100 { "psc0_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
101 { "psc2_intclk", "EXTCLK0", ALCHEMY_CPU_AU1300 },
102 { "psc1_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
103 { "psc3_intclk", "EXTCLK1", ALCHEMY_CPU_AU1300 },
104
105 { NULL, NULL, 0 },
106};
107
108#define IOMEM(x) ((void __iomem *)(KSEG1ADDR(CPHYSADDR(x))))
109
110/* access locks to SYS_FREQCTRL0/1 and SYS_CLKSRC registers */
111static spinlock_t alchemy_clk_fg0_lock;
112static spinlock_t alchemy_clk_fg1_lock;
113static spinlock_t alchemy_clk_csrc_lock;
114
115/* CPU Core clock *****************************************************/
116
117static unsigned long alchemy_clk_cpu_recalc(struct clk_hw *hw,
118 unsigned long parent_rate)
119{
120 unsigned long t;
121
122 /*
123 * On early Au1000, sys_cpupll was write-only. Since these
124 * silicon versions of Au1000 are not sold, we don't bend
125 * over backwards trying to determine the frequency.
126 */
127 if (unlikely(au1xxx_cpu_has_pll_wo()))
128 t = 396000000;
129 else {
130 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f;
131 t *= parent_rate;
132 }
133
134 return t;
135}
136
137static struct clk_ops alchemy_clkops_cpu = {
138 .recalc_rate = alchemy_clk_cpu_recalc,
139};
140
141static struct clk __init *alchemy_clk_setup_cpu(const char *parent_name,
142 int ctype)
143{
144 struct clk_init_data id;
145 struct clk_hw *h;
146
147 h = kzalloc(sizeof(*h), GFP_KERNEL);
148 if (!h)
149 return ERR_PTR(-ENOMEM);
150
151 id.name = ALCHEMY_CPU_CLK;
152 id.parent_names = &parent_name;
153 id.num_parents = 1;
154 id.flags = CLK_IS_BASIC;
155 id.ops = &alchemy_clkops_cpu;
156 h->init = &id;
157
158 return clk_register(NULL, h);
159}
160
161/* AUXPLLs ************************************************************/
162
163struct alchemy_auxpll_clk {
164 struct clk_hw hw;
165 unsigned long reg; /* au1300 has also AUXPLL2 */
166 int maxmult; /* max multiplier */
167};
168#define to_auxpll_clk(x) container_of(x, struct alchemy_auxpll_clk, hw)
169
170static unsigned long alchemy_clk_aux_recalc(struct clk_hw *hw,
171 unsigned long parent_rate)
172{
173 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
174
175 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate;
176}
177
178static int alchemy_clk_aux_setr(struct clk_hw *hw,
179 unsigned long rate,
180 unsigned long parent_rate)
181{
182 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
183 unsigned long d = rate;
184
185 if (rate)
186 d /= parent_rate;
187 else
188 d = 0;
189
190 /* minimum is 84MHz, max is 756-1032 depending on variant */
191 if (((d < 7) && (d != 0)) || (d > a->maxmult))
192 return -EINVAL;
193
194 alchemy_wrsys(d, a->reg);
195 return 0;
196}
197
198static long alchemy_clk_aux_roundr(struct clk_hw *hw,
199 unsigned long rate,
200 unsigned long *parent_rate)
201{
202 struct alchemy_auxpll_clk *a = to_auxpll_clk(hw);
203 unsigned long mult;
204
205 if (!rate || !*parent_rate)
206 return 0;
207
208 mult = rate / (*parent_rate);
209
210 if (mult && (mult < 7))
211 mult = 7;
212 if (mult > a->maxmult)
213 mult = a->maxmult;
214
215 return (*parent_rate) * mult;
216}
217
218static struct clk_ops alchemy_clkops_aux = {
219 .recalc_rate = alchemy_clk_aux_recalc,
220 .set_rate = alchemy_clk_aux_setr,
221 .round_rate = alchemy_clk_aux_roundr,
222};
223
224static struct clk __init *alchemy_clk_setup_aux(const char *parent_name,
225 char *name, int maxmult,
226 unsigned long reg)
227{
228 struct clk_init_data id;
229 struct clk *c;
230 struct alchemy_auxpll_clk *a;
231
232 a = kzalloc(sizeof(*a), GFP_KERNEL);
233 if (!a)
234 return ERR_PTR(-ENOMEM);
235
236 id.name = name;
237 id.parent_names = &parent_name;
238 id.num_parents = 1;
239 id.flags = CLK_GET_RATE_NOCACHE;
240 id.ops = &alchemy_clkops_aux;
241
242 a->reg = reg;
243 a->maxmult = maxmult;
244 a->hw.init = &id;
245
246 c = clk_register(NULL, &a->hw);
247 if (!IS_ERR(c))
248 clk_register_clkdev(c, name, NULL);
249 else
250 kfree(a);
251
252 return c;
253}
254
255/* sysbus_clk *********************************************************/
256
257static struct clk __init *alchemy_clk_setup_sysbus(const char *pn)
258{
259 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2;
260 struct clk *c;
261
262 c = clk_register_fixed_factor(NULL, ALCHEMY_SYSBUS_CLK,
263 pn, 0, 1, v);
264 if (!IS_ERR(c))
265 clk_register_clkdev(c, ALCHEMY_SYSBUS_CLK, NULL);
266 return c;
267}
268
269/* Peripheral Clock ***************************************************/
270
271static struct clk __init *alchemy_clk_setup_periph(const char *pn)
272{
273 /* Peripheral clock runs at half the rate of sysbus clk */
274 struct clk *c;
275
276 c = clk_register_fixed_factor(NULL, ALCHEMY_PERIPH_CLK,
277 pn, 0, 1, 2);
278 if (!IS_ERR(c))
279 clk_register_clkdev(c, ALCHEMY_PERIPH_CLK, NULL);
280 return c;
281}
282
283/* mem clock **********************************************************/
284
285static struct clk __init *alchemy_clk_setup_mem(const char *pn, int ct)
286{
287 void __iomem *addr = IOMEM(AU1000_MEM_PHYS_ADDR);
288 unsigned long v;
289 struct clk *c;
290 int div;
291
292 switch (ct) {
293 case ALCHEMY_CPU_AU1550:
294 case ALCHEMY_CPU_AU1200:
295 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
296 div = (v & (1 << 15)) ? 1 : 2;
297 break;
298 case ALCHEMY_CPU_AU1300:
299 v = __raw_readl(addr + AU1550_MEM_SDCONFIGB);
300 div = (v & (1 << 31)) ? 1 : 2;
301 break;
302 case ALCHEMY_CPU_AU1000:
303 case ALCHEMY_CPU_AU1500:
304 case ALCHEMY_CPU_AU1100:
305 default:
306 div = 2;
307 break;
308 }
309
310 c = clk_register_fixed_factor(NULL, ALCHEMY_MEM_CLK, pn,
311 0, 1, div);
312 if (!IS_ERR(c))
313 clk_register_clkdev(c, ALCHEMY_MEM_CLK, NULL);
314 return c;
315}
316
317/* lrclk: external synchronous static bus clock ***********************/
318
319static struct clk __init *alchemy_clk_setup_lrclk(const char *pn)
320{
321 /* MEM_STCFG0[15:13] = divisor.
322 * L/RCLK = periph_clk / (divisor + 1)
323 * On Au1000, Au1500, Au1100 it's called LCLK,
324 * on later models it's called RCLK, but it's the same thing.
325 */
326 struct clk *c;
327 unsigned long v = alchemy_rdsmem(AU1000_MEM_STCFG0) >> 13;
328
329 v = (v & 7) + 1;
330 c = clk_register_fixed_factor(NULL, ALCHEMY_LR_CLK,
331 pn, 0, 1, v);
332 if (!IS_ERR(c))
333 clk_register_clkdev(c, ALCHEMY_LR_CLK, NULL);
334 return c;
335}
336
337/* Clock dividers and muxes *******************************************/
338
339/* data for fgen and csrc mux-dividers */
340struct alchemy_fgcs_clk {
341 struct clk_hw hw;
342 spinlock_t *reglock; /* register lock */
343 unsigned long reg; /* SYS_FREQCTRL0/1 */
344 int shift; /* offset in register */
345 int parent; /* parent before disable [Au1300] */
346 int isen; /* is it enabled? */
347 int *dt; /* dividertable for csrc */
348};
349#define to_fgcs_clk(x) container_of(x, struct alchemy_fgcs_clk, hw)
350
351static long alchemy_calc_div(unsigned long rate, unsigned long prate,
352 int scale, int maxdiv, unsigned long *rv)
353{
354 long div1, div2;
355
356 div1 = prate / rate;
357 if ((prate / div1) > rate)
358 div1++;
359
360 if (scale == 2) { /* only div-by-multiple-of-2 possible */
361 if (div1 & 1)
362 div1++; /* stay <=prate */
363 }
364
365 div2 = (div1 / scale) - 1; /* value to write to register */
366
367 if (div2 > maxdiv)
368 div2 = maxdiv;
369 if (rv)
370 *rv = div2;
371
372 div1 = ((div2 + 1) * scale);
373 return div1;
374}
375
376static long alchemy_clk_fgcs_detr(struct clk_hw *hw, unsigned long rate,
377 unsigned long *best_parent_rate,
378 struct clk **best_parent_clk,
379 int scale, int maxdiv)
380{
381 struct clk *pc, *bpc, *free;
382 long tdv, tpr, pr, nr, br, bpr, diff, lastdiff;
383 int j;
384
385 lastdiff = INT_MAX;
386 bpr = 0;
387 bpc = NULL;
388 br = -EINVAL;
389 free = NULL;
390
391 /* look at the rates each enabled parent supplies and select
392 * the one that gets closest to but not over the requested rate.
393 */
394 for (j = 0; j < 7; j++) {
395 pc = clk_get_parent_by_index(hw->clk, j);
396 if (!pc)
397 break;
398
399 /* if this parent is currently unused, remember it.
400 * XXX: I know it's a layering violation, but it works
401 * so well.. (if (!clk_has_active_children(pc)) )
402 */
403 if (pc->prepare_count == 0) {
404 if (!free)
405 free = pc;
406 }
407
408 pr = clk_get_rate(pc);
409 if (pr < rate)
410 continue;
411
412 /* what can hardware actually provide */
413 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
414 nr = pr / tdv;
415 diff = rate - nr;
416 if (nr > rate)
417 continue;
418
419 if (diff < lastdiff) {
420 lastdiff = diff;
421 bpr = pr;
422 bpc = pc;
423 br = nr;
424 }
425 if (diff == 0)
426 break;
427 }
428
429 /* if we couldn't get the exact rate we wanted from the enabled
430 * parents, maybe we can tell an available disabled/inactive one
431 * to give us a rate we can divide down to the requested rate.
432 */
433 if (lastdiff && free) {
434 for (j = (maxdiv == 4) ? 1 : scale; j <= maxdiv; j += scale) {
435 tpr = rate * j;
436 if (tpr < 0)
437 break;
438 pr = clk_round_rate(free, tpr);
439
440 tdv = alchemy_calc_div(rate, pr, scale, maxdiv, NULL);
441 nr = pr / tdv;
442 diff = rate - nr;
443 if (nr > rate)
444 continue;
445 if (diff < lastdiff) {
446 lastdiff = diff;
447 bpr = pr;
448 bpc = free;
449 br = nr;
450 }
451 if (diff == 0)
452 break;
453 }
454 }
455
456 *best_parent_rate = bpr;
457 *best_parent_clk = bpc;
458 return br;
459}
460
461static int alchemy_clk_fgv1_en(struct clk_hw *hw)
462{
463 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
464 unsigned long v, flags;
465
466 spin_lock_irqsave(c->reglock, flags);
467 v = alchemy_rdsys(c->reg);
468 v |= (1 << 1) << c->shift;
469 alchemy_wrsys(v, c->reg);
470 spin_unlock_irqrestore(c->reglock, flags);
471
472 return 0;
473}
474
475static int alchemy_clk_fgv1_isen(struct clk_hw *hw)
476{
477 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
478 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1);
479
480 return v & 1;
481}
482
483static void alchemy_clk_fgv1_dis(struct clk_hw *hw)
484{
485 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
486 unsigned long v, flags;
487
488 spin_lock_irqsave(c->reglock, flags);
489 v = alchemy_rdsys(c->reg);
490 v &= ~((1 << 1) << c->shift);
491 alchemy_wrsys(v, c->reg);
492 spin_unlock_irqrestore(c->reglock, flags);
493}
494
495static int alchemy_clk_fgv1_setp(struct clk_hw *hw, u8 index)
496{
497 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
498 unsigned long v, flags;
499
500 spin_lock_irqsave(c->reglock, flags);
501 v = alchemy_rdsys(c->reg);
502 if (index)
503 v |= (1 << c->shift);
504 else
505 v &= ~(1 << c->shift);
506 alchemy_wrsys(v, c->reg);
507 spin_unlock_irqrestore(c->reglock, flags);
508
509 return 0;
510}
511
512static u8 alchemy_clk_fgv1_getp(struct clk_hw *hw)
513{
514 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
515
516 return (alchemy_rdsys(c->reg) >> c->shift) & 1;
517}
518
519static int alchemy_clk_fgv1_setr(struct clk_hw *hw, unsigned long rate,
520 unsigned long parent_rate)
521{
522 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
523 unsigned long div, v, flags, ret;
524 int sh = c->shift + 2;
525
526 if (!rate || !parent_rate || rate > (parent_rate / 2))
527 return -EINVAL;
528 ret = alchemy_calc_div(rate, parent_rate, 2, 512, &div);
529 spin_lock_irqsave(c->reglock, flags);
530 v = alchemy_rdsys(c->reg);
531 v &= ~(0xff << sh);
532 v |= div << sh;
533 alchemy_wrsys(v, c->reg);
534 spin_unlock_irqrestore(c->reglock, flags);
535
536 return 0;
537}
538
539static unsigned long alchemy_clk_fgv1_recalc(struct clk_hw *hw,
540 unsigned long parent_rate)
541{
542 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
543 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2);
544
545 v = ((v & 0xff) + 1) * 2;
546 return parent_rate / v;
547}
548
549static long alchemy_clk_fgv1_detr(struct clk_hw *hw, unsigned long rate,
550 unsigned long *best_parent_rate,
551 struct clk **best_parent_clk)
552{
553 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
554 best_parent_clk, 2, 512);
555}
556
557/* Au1000, Au1100, Au15x0, Au12x0 */
558static struct clk_ops alchemy_clkops_fgenv1 = {
559 .recalc_rate = alchemy_clk_fgv1_recalc,
560 .determine_rate = alchemy_clk_fgv1_detr,
561 .set_rate = alchemy_clk_fgv1_setr,
562 .set_parent = alchemy_clk_fgv1_setp,
563 .get_parent = alchemy_clk_fgv1_getp,
564 .enable = alchemy_clk_fgv1_en,
565 .disable = alchemy_clk_fgv1_dis,
566 .is_enabled = alchemy_clk_fgv1_isen,
567};
568
569static void __alchemy_clk_fgv2_en(struct alchemy_fgcs_clk *c)
570{
571 unsigned long v = alchemy_rdsys(c->reg);
572
573 v &= ~(3 << c->shift);
574 v |= (c->parent & 3) << c->shift;
575 alchemy_wrsys(v, c->reg);
576 c->isen = 1;
577}
578
579static int alchemy_clk_fgv2_en(struct clk_hw *hw)
580{
581 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
582 unsigned long flags;
583
584 /* enable by setting the previous parent clock */
585 spin_lock_irqsave(c->reglock, flags);
586 __alchemy_clk_fgv2_en(c);
587 spin_unlock_irqrestore(c->reglock, flags);
588
589 return 0;
590}
591
592static int alchemy_clk_fgv2_isen(struct clk_hw *hw)
593{
594 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
595
596 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0;
597}
598
599static void alchemy_clk_fgv2_dis(struct clk_hw *hw)
600{
601 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
602 unsigned long v, flags;
603
604 spin_lock_irqsave(c->reglock, flags);
605 v = alchemy_rdsys(c->reg);
606 v &= ~(3 << c->shift); /* set input mux to "disabled" state */
607 alchemy_wrsys(v, c->reg);
608 c->isen = 0;
609 spin_unlock_irqrestore(c->reglock, flags);
610}
611
612static int alchemy_clk_fgv2_setp(struct clk_hw *hw, u8 index)
613{
614 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
615 unsigned long flags;
616
617 spin_lock_irqsave(c->reglock, flags);
618 c->parent = index + 1; /* value to write to register */
619 if (c->isen)
620 __alchemy_clk_fgv2_en(c);
621 spin_unlock_irqrestore(c->reglock, flags);
622
623 return 0;
624}
625
626static u8 alchemy_clk_fgv2_getp(struct clk_hw *hw)
627{
628 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
629 unsigned long flags, v;
630
631 spin_lock_irqsave(c->reglock, flags);
632 v = c->parent - 1;
633 spin_unlock_irqrestore(c->reglock, flags);
634 return v;
635}
636
637/* fg0-2 and fg4-6 share a "scale"-bit. With this bit cleared, the
638 * dividers behave exactly as on previous models (dividers are multiples
639 * of 2); with the bit set, dividers are multiples of 1, halving their
640 * range, but making them also much more flexible.
641 */
642static int alchemy_clk_fgv2_setr(struct clk_hw *hw, unsigned long rate,
643 unsigned long parent_rate)
644{
645 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
646 int sh = c->shift + 2;
647 unsigned long div, v, flags, ret;
648
649 if (!rate || !parent_rate || rate > parent_rate)
650 return -EINVAL;
651
652 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */
653 ret = alchemy_calc_div(rate, parent_rate, v ? 1 : 2,
654 v ? 256 : 512, &div);
655
656 spin_lock_irqsave(c->reglock, flags);
657 v = alchemy_rdsys(c->reg);
658 v &= ~(0xff << sh);
659 v |= (div & 0xff) << sh;
660 alchemy_wrsys(v, c->reg);
661 spin_unlock_irqrestore(c->reglock, flags);
662
663 return 0;
664}
665
666static unsigned long alchemy_clk_fgv2_recalc(struct clk_hw *hw,
667 unsigned long parent_rate)
668{
669 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
670 int sh = c->shift + 2;
671 unsigned long v, t;
672
673 v = alchemy_rdsys(c->reg);
674 t = parent_rate / (((v >> sh) & 0xff) + 1);
675 if ((v & (1 << 30)) == 0) /* test scale bit */
676 t /= 2;
677
678 return t;
679}
680
681static long alchemy_clk_fgv2_detr(struct clk_hw *hw, unsigned long rate,
682 unsigned long *best_parent_rate,
683 struct clk **best_parent_clk)
684{
685 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
686 int scale, maxdiv;
687
688 if (alchemy_rdsys(c->reg) & (1 << 30)) {
689 scale = 1;
690 maxdiv = 256;
691 } else {
692 scale = 2;
693 maxdiv = 512;
694 }
695
696 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
697 best_parent_clk, scale, maxdiv);
698}
699
700/* Au1300 larger input mux, no separate disable bit, flexible divider */
701static struct clk_ops alchemy_clkops_fgenv2 = {
702 .recalc_rate = alchemy_clk_fgv2_recalc,
703 .determine_rate = alchemy_clk_fgv2_detr,
704 .set_rate = alchemy_clk_fgv2_setr,
705 .set_parent = alchemy_clk_fgv2_setp,
706 .get_parent = alchemy_clk_fgv2_getp,
707 .enable = alchemy_clk_fgv2_en,
708 .disable = alchemy_clk_fgv2_dis,
709 .is_enabled = alchemy_clk_fgv2_isen,
710};
711
712static const char * const alchemy_clk_fgv1_parents[] = {
713 ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
714};
715
716static const char * const alchemy_clk_fgv2_parents[] = {
717 ALCHEMY_AUXPLL2_CLK, ALCHEMY_CPU_CLK, ALCHEMY_AUXPLL_CLK
718};
719
720static const char * const alchemy_clk_fgen_names[] = {
721 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
722 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK };
723
724static int __init alchemy_clk_init_fgens(int ctype)
725{
726 struct clk *c;
727 struct clk_init_data id;
728 struct alchemy_fgcs_clk *a;
729 unsigned long v;
730 int i, ret;
731
732 switch (ctype) {
733 case ALCHEMY_CPU_AU1000...ALCHEMY_CPU_AU1200:
734 id.ops = &alchemy_clkops_fgenv1;
735 id.parent_names = (const char **)alchemy_clk_fgv1_parents;
736 id.num_parents = 2;
737 break;
738 case ALCHEMY_CPU_AU1300:
739 id.ops = &alchemy_clkops_fgenv2;
740 id.parent_names = (const char **)alchemy_clk_fgv2_parents;
741 id.num_parents = 3;
742 break;
743 default:
744 return -ENODEV;
745 }
746 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
747
748 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
749 if (!a)
750 return -ENOMEM;
751
752 spin_lock_init(&alchemy_clk_fg0_lock);
753 spin_lock_init(&alchemy_clk_fg1_lock);
754 ret = 0;
755 for (i = 0; i < 6; i++) {
756 id.name = alchemy_clk_fgen_names[i];
757 a->shift = 10 * (i < 3 ? i : i - 3);
758 if (i > 2) {
759 a->reg = AU1000_SYS_FREQCTRL1;
760 a->reglock = &alchemy_clk_fg1_lock;
761 } else {
762 a->reg = AU1000_SYS_FREQCTRL0;
763 a->reglock = &alchemy_clk_fg0_lock;
764 }
765
766 /* default to first parent if bootloader has set
767 * the mux to disabled state.
768 */
769 if (ctype == ALCHEMY_CPU_AU1300) {
770 v = alchemy_rdsys(a->reg);
771 a->parent = (v >> a->shift) & 3;
772 if (!a->parent) {
773 a->parent = 1;
774 a->isen = 0;
775 } else
776 a->isen = 1;
777 }
778
779 a->hw.init = &id;
780 c = clk_register(NULL, &a->hw);
781 if (IS_ERR(c))
782 ret++;
783 else
784 clk_register_clkdev(c, id.name, NULL);
785 a++;
786 }
787
788 return ret;
789}
790
791/* internal sources muxes *********************************************/
792
793static int alchemy_clk_csrc_isen(struct clk_hw *hw)
794{
795 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
796 unsigned long v = alchemy_rdsys(c->reg);
797
798 return (((v >> c->shift) >> 2) & 7) != 0;
799}
800
801static void __alchemy_clk_csrc_en(struct alchemy_fgcs_clk *c)
802{
803 unsigned long v = alchemy_rdsys(c->reg);
804
805 v &= ~((7 << 2) << c->shift);
806 v |= ((c->parent & 7) << 2) << c->shift;
807 alchemy_wrsys(v, c->reg);
808 c->isen = 1;
809}
810
811static int alchemy_clk_csrc_en(struct clk_hw *hw)
812{
813 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
814 unsigned long flags;
815
816 /* enable by setting the previous parent clock */
817 spin_lock_irqsave(c->reglock, flags);
818 __alchemy_clk_csrc_en(c);
819 spin_unlock_irqrestore(c->reglock, flags);
820
821 return 0;
822}
823
824static void alchemy_clk_csrc_dis(struct clk_hw *hw)
825{
826 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
827 unsigned long v, flags;
828
829 spin_lock_irqsave(c->reglock, flags);
830 v = alchemy_rdsys(c->reg);
831 v &= ~((3 << 2) << c->shift); /* mux to "disabled" state */
832 alchemy_wrsys(v, c->reg);
833 c->isen = 0;
834 spin_unlock_irqrestore(c->reglock, flags);
835}
836
837static int alchemy_clk_csrc_setp(struct clk_hw *hw, u8 index)
838{
839 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
840 unsigned long flags;
841
842 spin_lock_irqsave(c->reglock, flags);
843 c->parent = index + 1; /* value to write to register */
844 if (c->isen)
845 __alchemy_clk_csrc_en(c);
846 spin_unlock_irqrestore(c->reglock, flags);
847
848 return 0;
849}
850
851static u8 alchemy_clk_csrc_getp(struct clk_hw *hw)
852{
853 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
854
855 return c->parent - 1;
856}
857
858static unsigned long alchemy_clk_csrc_recalc(struct clk_hw *hw,
859 unsigned long parent_rate)
860{
861 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
862 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3;
863
864 return parent_rate / c->dt[v];
865}
866
867static int alchemy_clk_csrc_setr(struct clk_hw *hw, unsigned long rate,
868 unsigned long parent_rate)
869{
870 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
871 unsigned long d, v, flags;
872 int i;
873
874 if (!rate || !parent_rate || rate > parent_rate)
875 return -EINVAL;
876
877 d = (parent_rate + (rate / 2)) / rate;
878 if (d > 4)
879 return -EINVAL;
880 if ((d == 3) && (c->dt[2] != 3))
881 d = 4;
882
883 for (i = 0; i < 4; i++)
884 if (c->dt[i] == d)
885 break;
886
887 if (i >= 4)
888 return -EINVAL; /* oops */
889
890 spin_lock_irqsave(c->reglock, flags);
891 v = alchemy_rdsys(c->reg);
892 v &= ~(3 << c->shift);
893 v |= (i & 3) << c->shift;
894 alchemy_wrsys(v, c->reg);
895 spin_unlock_irqrestore(c->reglock, flags);
896
897 return 0;
898}
899
900static long alchemy_clk_csrc_detr(struct clk_hw *hw, unsigned long rate,
901 unsigned long *best_parent_rate,
902 struct clk **best_parent_clk)
903{
904 struct alchemy_fgcs_clk *c = to_fgcs_clk(hw);
905 int scale = c->dt[2] == 3 ? 1 : 2; /* au1300 check */
906
907 return alchemy_clk_fgcs_detr(hw, rate, best_parent_rate,
908 best_parent_clk, scale, 4);
909}
910
911static struct clk_ops alchemy_clkops_csrc = {
912 .recalc_rate = alchemy_clk_csrc_recalc,
913 .determine_rate = alchemy_clk_csrc_detr,
914 .set_rate = alchemy_clk_csrc_setr,
915 .set_parent = alchemy_clk_csrc_setp,
916 .get_parent = alchemy_clk_csrc_getp,
917 .enable = alchemy_clk_csrc_en,
918 .disable = alchemy_clk_csrc_dis,
919 .is_enabled = alchemy_clk_csrc_isen,
920};
921
922static const char * const alchemy_clk_csrc_parents[] = {
923 /* disabled at index 0 */ ALCHEMY_AUXPLL_CLK,
924 ALCHEMY_FG0_CLK, ALCHEMY_FG1_CLK, ALCHEMY_FG2_CLK,
925 ALCHEMY_FG3_CLK, ALCHEMY_FG4_CLK, ALCHEMY_FG5_CLK
926};
927
928/* divider tables */
929static int alchemy_csrc_dt1[] = { 1, 4, 1, 2 }; /* rest */
930static int alchemy_csrc_dt2[] = { 1, 4, 3, 2 }; /* Au1300 */
931
932static int __init alchemy_clk_setup_imux(int ctype)
933{
934 struct alchemy_fgcs_clk *a;
935 const char * const *names;
936 struct clk_init_data id;
937 unsigned long v;
938 int i, ret, *dt;
939 struct clk *c;
940
941 id.ops = &alchemy_clkops_csrc;
942 id.parent_names = (const char **)alchemy_clk_csrc_parents;
943 id.num_parents = 7;
944 id.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE;
945
946 dt = alchemy_csrc_dt1;
947 switch (ctype) {
948 case ALCHEMY_CPU_AU1000:
949 names = alchemy_au1000_intclknames;
950 break;
951 case ALCHEMY_CPU_AU1500:
952 names = alchemy_au1500_intclknames;
953 break;
954 case ALCHEMY_CPU_AU1100:
955 names = alchemy_au1100_intclknames;
956 break;
957 case ALCHEMY_CPU_AU1550:
958 names = alchemy_au1550_intclknames;
959 break;
960 case ALCHEMY_CPU_AU1200:
961 names = alchemy_au1200_intclknames;
962 break;
963 case ALCHEMY_CPU_AU1300:
964 dt = alchemy_csrc_dt2;
965 names = alchemy_au1300_intclknames;
966 break;
967 default:
968 return -ENODEV;
969 }
970
971 a = kzalloc((sizeof(*a)) * 6, GFP_KERNEL);
972 if (!a)
973 return -ENOMEM;
974
975 spin_lock_init(&alchemy_clk_csrc_lock);
976 ret = 0;
977
978 for (i = 0; i < 6; i++) {
979 id.name = names[i];
980 if (!id.name)
981 goto next;
982
983 a->shift = i * 5;
984 a->reg = AU1000_SYS_CLKSRC;
985 a->reglock = &alchemy_clk_csrc_lock;
986 a->dt = dt;
987
988 /* default to first parent clock if mux is initially
989 * set to disabled state.
990 */
991 v = alchemy_rdsys(a->reg);
992 a->parent = ((v >> a->shift) >> 2) & 7;
993 if (!a->parent) {
994 a->parent = 1;
995 a->isen = 0;
996 } else
997 a->isen = 1;
998
999 a->hw.init = &id;
1000 c = clk_register(NULL, &a->hw);
1001 if (IS_ERR(c))
1002 ret++;
1003 else
1004 clk_register_clkdev(c, id.name, NULL);
1005next:
1006 a++;
1007 }
1008
1009 return ret;
1010}
1011
1012
1013/**********************************************************************/
1014
1015
1016#define ERRCK(x) \
1017 if (IS_ERR(x)) { \
1018 ret = PTR_ERR(x); \
1019 goto out; \
1020 }
1021
1022static int __init alchemy_clk_init(void)
1023{
1024 int ctype = alchemy_get_cputype(), ret, i;
1025 struct clk_aliastable *t = alchemy_clk_aliases;
1026 struct clk *c;
1027
1028 /* Root of the Alchemy clock tree: external 12MHz crystal osc */
1029 c = clk_register_fixed_rate(NULL, ALCHEMY_ROOT_CLK, NULL,
1030 CLK_IS_ROOT,
1031 ALCHEMY_ROOTCLK_RATE);
1032 ERRCK(c)
1033
1034 /* CPU core clock */
1035 c = alchemy_clk_setup_cpu(ALCHEMY_ROOT_CLK, ctype);
1036 ERRCK(c)
1037
1038 /* AUXPLLs: max 1GHz on Au1300, 748MHz on older models */
1039 i = (ctype == ALCHEMY_CPU_AU1300) ? 84 : 63;
1040 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK, ALCHEMY_AUXPLL_CLK,
1041 i, AU1000_SYS_AUXPLL);
1042 ERRCK(c)
1043
1044 if (ctype == ALCHEMY_CPU_AU1300) {
1045 c = alchemy_clk_setup_aux(ALCHEMY_ROOT_CLK,
1046 ALCHEMY_AUXPLL2_CLK, i,
1047 AU1300_SYS_AUXPLL2);
1048 ERRCK(c)
1049 }
1050
1051 /* sysbus clock: cpu core clock divided by 2, 3 or 4 */
1052 c = alchemy_clk_setup_sysbus(ALCHEMY_CPU_CLK);
1053 ERRCK(c)
1054
1055 /* peripheral clock: runs at half rate of sysbus clk */
1056 c = alchemy_clk_setup_periph(ALCHEMY_SYSBUS_CLK);
1057 ERRCK(c)
1058
1059 /* SDR/DDR memory clock */
1060 c = alchemy_clk_setup_mem(ALCHEMY_SYSBUS_CLK, ctype);
1061 ERRCK(c)
1062
1063 /* L/RCLK: external static bus clock for synchronous mode */
1064 c = alchemy_clk_setup_lrclk(ALCHEMY_PERIPH_CLK);
1065 ERRCK(c)
1066
1067 /* Frequency dividers 0-5 */
1068 ret = alchemy_clk_init_fgens(ctype);
1069 if (ret) {
1070 ret = -ENODEV;
1071 goto out;
1072 }
1073
1074 /* diving muxes for internal sources */
1075 ret = alchemy_clk_setup_imux(ctype);
1076 if (ret) {
1077 ret = -ENODEV;
1078 goto out;
1079 }
1080
1081 /* set up aliases drivers might look for */
1082 while (t->base) {
1083 if (t->cputype == ctype)
1084 clk_add_alias(t->alias, NULL, t->base, NULL);
1085 t++;
1086 }
1087
1088 pr_info("Alchemy clocktree installed\n");
1089 return 0;
1090
1091out:
1092 return ret;
1093}
1094postcore_initcall(alchemy_clk_init);
diff --git a/arch/mips/alchemy/common/clocks.c b/arch/mips/alchemy/common/clocks.c
deleted file mode 100644
index f38298a8b98c..000000000000
--- a/arch/mips/alchemy/common/clocks.c
+++ /dev/null
@@ -1,105 +0,0 @@
1/*
2 * BRIEF MODULE DESCRIPTION
3 * Simple Au1xx0 clocks routines.
4 *
5 * Copyright 2001, 2008 MontaVista Software Inc.
6 * Author: MontaVista Software, Inc. <source@mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
14 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
16 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
19 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
20 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 675 Mass Ave, Cambridge, MA 02139, USA.
27 */
28
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <asm/time.h>
32#include <asm/mach-au1x00/au1000.h>
33
34/*
35 * I haven't found anyone that doesn't use a 12 MHz source clock,
36 * but just in case.....
37 */
38#define AU1000_SRC_CLK 12000000
39
40static unsigned int au1x00_clock; /* Hz */
41static unsigned long uart_baud_base;
42
43/*
44 * Set the au1000_clock
45 */
46void set_au1x00_speed(unsigned int new_freq)
47{
48 au1x00_clock = new_freq;
49}
50
51unsigned int get_au1x00_speed(void)
52{
53 return au1x00_clock;
54}
55EXPORT_SYMBOL(get_au1x00_speed);
56
57/*
58 * The UART baud base is not known at compile time ... if
59 * we want to be able to use the same code on different
60 * speed CPUs.
61 */
62unsigned long get_au1x00_uart_baud_base(void)
63{
64 return uart_baud_base;
65}
66
67void set_au1x00_uart_baud_base(unsigned long new_baud_base)
68{
69 uart_baud_base = new_baud_base;
70}
71
72/*
73 * We read the real processor speed from the PLL. This is important
74 * because it is more accurate than computing it from the 32 KHz
75 * counter, if it exists. If we don't have an accurate processor
76 * speed, all of the peripherals that derive their clocks based on
77 * this advertised speed will introduce error and sometimes not work
78 * properly. This function is further convoluted to still allow configurations
79 * to do that in case they have really, really old silicon with a
80 * write-only PLL register. -- Dan
81 */
82unsigned long au1xxx_calc_clock(void)
83{
84 unsigned long cpu_speed;
85
86 /*
87 * On early Au1000, sys_cpupll was write-only. Since these
88 * silicon versions of Au1000 are not sold by AMD, we don't bend
89 * over backwards trying to determine the frequency.
90 */
91 if (au1xxx_cpu_has_pll_wo())
92 cpu_speed = 396000000;
93 else
94 cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
95
96 /* On Alchemy CPU:counter ratio is 1:1 */
97 mips_hpt_frequency = cpu_speed;
98 /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */
99 set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)
100 & 0x03) + 2) * 16));
101
102 set_au1x00_speed(cpu_speed);
103
104 return cpu_speed;
105}
diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c
index 19d5642c16d9..745695db5ba0 100644
--- a/arch/mips/alchemy/common/dbdma.c
+++ b/arch/mips/alchemy/common/dbdma.c
@@ -341,7 +341,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
341 (dtp->dev_flags & DEV_FLAGS_SYNC)) 341 (dtp->dev_flags & DEV_FLAGS_SYNC))
342 i |= DDMA_CFG_SYNC; 342 i |= DDMA_CFG_SYNC;
343 cp->ddma_cfg = i; 343 cp->ddma_cfg = i;
344 au_sync(); 344 wmb(); /* drain writebuffer */
345 345
346 /* 346 /*
347 * Return a non-zero value that can be used to find the channel 347 * Return a non-zero value that can be used to find the channel
@@ -631,7 +631,7 @@ u32 au1xxx_dbdma_put_source(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
631 */ 631 */
632 dma_cache_wback_inv((unsigned long)buf, nbytes); 632 dma_cache_wback_inv((unsigned long)buf, nbytes);
633 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 633 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
634 au_sync(); 634 wmb(); /* drain writebuffer */
635 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 635 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
636 ctp->chan_ptr->ddma_dbell = 0; 636 ctp->chan_ptr->ddma_dbell = 0;
637 637
@@ -693,7 +693,7 @@ u32 au1xxx_dbdma_put_dest(u32 chanid, dma_addr_t buf, int nbytes, u32 flags)
693 */ 693 */
694 dma_cache_inv((unsigned long)buf, nbytes); 694 dma_cache_inv((unsigned long)buf, nbytes);
695 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */ 695 dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
696 au_sync(); 696 wmb(); /* drain writebuffer */
697 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp)); 697 dma_cache_wback_inv((unsigned long)dp, sizeof(*dp));
698 ctp->chan_ptr->ddma_dbell = 0; 698 ctp->chan_ptr->ddma_dbell = 0;
699 699
@@ -760,7 +760,7 @@ void au1xxx_dbdma_stop(u32 chanid)
760 760
761 cp = ctp->chan_ptr; 761 cp = ctp->chan_ptr;
762 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */ 762 cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
763 au_sync(); 763 wmb(); /* drain writebuffer */
764 while (!(cp->ddma_stat & DDMA_STAT_H)) { 764 while (!(cp->ddma_stat & DDMA_STAT_H)) {
765 udelay(1); 765 udelay(1);
766 halt_timeout++; 766 halt_timeout++;
@@ -771,7 +771,7 @@ void au1xxx_dbdma_stop(u32 chanid)
771 } 771 }
772 /* clear current desc valid and doorbell */ 772 /* clear current desc valid and doorbell */
773 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V); 773 cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
774 au_sync(); 774 wmb(); /* drain writebuffer */
775} 775}
776EXPORT_SYMBOL(au1xxx_dbdma_stop); 776EXPORT_SYMBOL(au1xxx_dbdma_stop);
777 777
@@ -789,9 +789,9 @@ void au1xxx_dbdma_start(u32 chanid)
789 cp = ctp->chan_ptr; 789 cp = ctp->chan_ptr;
790 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr); 790 cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
791 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */ 791 cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
792 au_sync(); 792 wmb(); /* drain writebuffer */
793 cp->ddma_dbell = 0; 793 cp->ddma_dbell = 0;
794 au_sync(); 794 wmb(); /* drain writebuffer */
795} 795}
796EXPORT_SYMBOL(au1xxx_dbdma_start); 796EXPORT_SYMBOL(au1xxx_dbdma_start);
797 797
@@ -832,7 +832,7 @@ u32 au1xxx_get_dma_residue(u32 chanid)
832 832
833 /* This is only valid if the channel is stopped. */ 833 /* This is only valid if the channel is stopped. */
834 rv = cp->ddma_bytecnt; 834 rv = cp->ddma_bytecnt;
835 au_sync(); 835 wmb(); /* drain writebuffer */
836 836
837 return rv; 837 return rv;
838} 838}
@@ -868,7 +868,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
868 au1x_dma_chan_t *cp; 868 au1x_dma_chan_t *cp;
869 869
870 intstat = dbdma_gptr->ddma_intstat; 870 intstat = dbdma_gptr->ddma_intstat;
871 au_sync(); 871 wmb(); /* drain writebuffer */
872 chan_index = __ffs(intstat); 872 chan_index = __ffs(intstat);
873 873
874 ctp = chan_tab_ptr[chan_index]; 874 ctp = chan_tab_ptr[chan_index];
@@ -877,7 +877,7 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id)
877 877
878 /* Reset interrupt. */ 878 /* Reset interrupt. */
879 cp->ddma_irq = 0; 879 cp->ddma_irq = 0;
880 au_sync(); 880 wmb(); /* drain writebuffer */
881 881
882 if (ctp->chan_callback) 882 if (ctp->chan_callback)
883 ctp->chan_callback(irq, ctp->chan_callparam); 883 ctp->chan_callback(irq, ctp->chan_callparam);
@@ -1061,7 +1061,7 @@ static int __init dbdma_setup(unsigned int irq, dbdev_tab_t *idtable)
1061 dbdma_gptr->ddma_config = 0; 1061 dbdma_gptr->ddma_config = 0;
1062 dbdma_gptr->ddma_throttle = 0; 1062 dbdma_gptr->ddma_throttle = 0;
1063 dbdma_gptr->ddma_inten = 0xffff; 1063 dbdma_gptr->ddma_inten = 0xffff;
1064 au_sync(); 1064 wmb(); /* drain writebuffer */
1065 1065
1066 ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr); 1066 ret = request_irq(irq, dbdma_interrupt, 0, "dbdma", (void *)dbdma_gptr);
1067 if (ret) 1067 if (ret)
diff --git a/arch/mips/alchemy/common/dma.c b/arch/mips/alchemy/common/dma.c
index 9b624e2c0fcf..4fb6207b883b 100644
--- a/arch/mips/alchemy/common/dma.c
+++ b/arch/mips/alchemy/common/dma.c
@@ -141,17 +141,17 @@ void dump_au1000_dma_channel(unsigned int dmanr)
141 141
142 printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr); 142 printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
143 printk(KERN_INFO " mode = 0x%08x\n", 143 printk(KERN_INFO " mode = 0x%08x\n",
144 au_readl(chan->io + DMA_MODE_SET)); 144 __raw_readl(chan->io + DMA_MODE_SET));
145 printk(KERN_INFO " addr = 0x%08x\n", 145 printk(KERN_INFO " addr = 0x%08x\n",
146 au_readl(chan->io + DMA_PERIPHERAL_ADDR)); 146 __raw_readl(chan->io + DMA_PERIPHERAL_ADDR));
147 printk(KERN_INFO " start0 = 0x%08x\n", 147 printk(KERN_INFO " start0 = 0x%08x\n",
148 au_readl(chan->io + DMA_BUFFER0_START)); 148 __raw_readl(chan->io + DMA_BUFFER0_START));
149 printk(KERN_INFO " start1 = 0x%08x\n", 149 printk(KERN_INFO " start1 = 0x%08x\n",
150 au_readl(chan->io + DMA_BUFFER1_START)); 150 __raw_readl(chan->io + DMA_BUFFER1_START));
151 printk(KERN_INFO " count0 = 0x%08x\n", 151 printk(KERN_INFO " count0 = 0x%08x\n",
152 au_readl(chan->io + DMA_BUFFER0_COUNT)); 152 __raw_readl(chan->io + DMA_BUFFER0_COUNT));
153 printk(KERN_INFO " count1 = 0x%08x\n", 153 printk(KERN_INFO " count1 = 0x%08x\n",
154 au_readl(chan->io + DMA_BUFFER1_COUNT)); 154 __raw_readl(chan->io + DMA_BUFFER1_COUNT));
155} 155}
156 156
157/* 157/*
@@ -204,7 +204,8 @@ int request_au1000_dma(int dev_id, const char *dev_str,
204 } 204 }
205 205
206 /* fill it in */ 206 /* fill it in */
207 chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN; 207 chan->io = (void __iomem *)(KSEG1ADDR(AU1000_DMA_PHYS_ADDR) +
208 i * DMA_CHANNEL_LEN);
208 chan->dev_id = dev_id; 209 chan->dev_id = dev_id;
209 chan->dev_str = dev_str; 210 chan->dev_str = dev_str;
210 chan->fifo_addr = dev->fifo_addr; 211 chan->fifo_addr = dev->fifo_addr;
diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c
index 63a71817a00c..6cb60abfdcc9 100644
--- a/arch/mips/alchemy/common/irq.c
+++ b/arch/mips/alchemy/common/irq.c
@@ -389,13 +389,12 @@ static int au1x_ic1_setwake(struct irq_data *d, unsigned int on)
389 return -EINVAL; 389 return -EINVAL;
390 390
391 local_irq_save(flags); 391 local_irq_save(flags);
392 wakemsk = __raw_readl((void __iomem *)SYS_WAKEMSK); 392 wakemsk = alchemy_rdsys(AU1000_SYS_WAKEMSK);
393 if (on) 393 if (on)
394 wakemsk |= 1 << bit; 394 wakemsk |= 1 << bit;
395 else 395 else
396 wakemsk &= ~(1 << bit); 396 wakemsk &= ~(1 << bit);
397 __raw_writel(wakemsk, (void __iomem *)SYS_WAKEMSK); 397 alchemy_wrsys(wakemsk, AU1000_SYS_WAKEMSK);
398 wmb();
399 local_irq_restore(flags); 398 local_irq_restore(flags);
400 399
401 return 0; 400 return 0;
diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c
index 9837a134a6d6..d77a64f4c78b 100644
--- a/arch/mips/alchemy/common/platform.c
+++ b/arch/mips/alchemy/common/platform.c
@@ -11,6 +11,7 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/clk.h>
14#include <linux/dma-mapping.h> 15#include <linux/dma-mapping.h>
15#include <linux/etherdevice.h> 16#include <linux/etherdevice.h>
16#include <linux/init.h> 17#include <linux/init.h>
@@ -99,10 +100,20 @@ static struct platform_device au1xx0_uart_device = {
99 100
100static void __init alchemy_setup_uarts(int ctype) 101static void __init alchemy_setup_uarts(int ctype)
101{ 102{
102 unsigned int uartclk = get_au1x00_uart_baud_base() * 16; 103 long uartclk;
103 int s = sizeof(struct plat_serial8250_port); 104 int s = sizeof(struct plat_serial8250_port);
104 int c = alchemy_get_uarts(ctype); 105 int c = alchemy_get_uarts(ctype);
105 struct plat_serial8250_port *ports; 106 struct plat_serial8250_port *ports;
107 struct clk *clk = clk_get(NULL, ALCHEMY_PERIPH_CLK);
108
109 if (IS_ERR(clk))
110 return;
111 if (clk_prepare_enable(clk)) {
112 clk_put(clk);
113 return;
114 }
115 uartclk = clk_get_rate(clk);
116 clk_put(clk);
106 117
107 ports = kzalloc(s * (c + 1), GFP_KERNEL); 118 ports = kzalloc(s * (c + 1), GFP_KERNEL);
108 if (!ports) { 119 if (!ports) {
@@ -420,7 +431,7 @@ static void __init alchemy_setup_macs(int ctype)
420 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6); 431 memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
421 432
422 /* Register second MAC if enabled in pinfunc */ 433 /* Register second MAC if enabled in pinfunc */
423 if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) { 434 if (!(alchemy_rdsys(AU1000_SYS_PINFUNC) & SYS_PF_NI2)) {
424 ret = platform_device_register(&au1xxx_eth1_device); 435 ret = platform_device_register(&au1xxx_eth1_device);
425 if (ret) 436 if (ret)
426 printk(KERN_INFO "Alchemy: failed to register MAC1\n"); 437 printk(KERN_INFO "Alchemy: failed to register MAC1\n");
diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c
index bdb28dee8fdd..921ed30b440c 100644
--- a/arch/mips/alchemy/common/power.c
+++ b/arch/mips/alchemy/common/power.c
@@ -54,28 +54,28 @@ static unsigned int sleep_static_memctlr[4][3];
54static void save_core_regs(void) 54static void save_core_regs(void)
55{ 55{
56 /* Clocks and PLLs. */ 56 /* Clocks and PLLs. */
57 sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); 57 sleep_sys_clocks[0] = alchemy_rdsys(AU1000_SYS_FREQCTRL0);
58 sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); 58 sleep_sys_clocks[1] = alchemy_rdsys(AU1000_SYS_FREQCTRL1);
59 sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); 59 sleep_sys_clocks[2] = alchemy_rdsys(AU1000_SYS_CLKSRC);
60 sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); 60 sleep_sys_clocks[3] = alchemy_rdsys(AU1000_SYS_CPUPLL);
61 sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); 61 sleep_sys_clocks[4] = alchemy_rdsys(AU1000_SYS_AUXPLL);
62 62
63 /* pin mux config */ 63 /* pin mux config */
64 sleep_sys_pinfunc = au_readl(SYS_PINFUNC); 64 sleep_sys_pinfunc = alchemy_rdsys(AU1000_SYS_PINFUNC);
65 65
66 /* Save the static memory controller configuration. */ 66 /* Save the static memory controller configuration. */
67 sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); 67 sleep_static_memctlr[0][0] = alchemy_rdsmem(AU1000_MEM_STCFG0);
68 sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0); 68 sleep_static_memctlr[0][1] = alchemy_rdsmem(AU1000_MEM_STTIME0);
69 sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0); 69 sleep_static_memctlr[0][2] = alchemy_rdsmem(AU1000_MEM_STADDR0);
70 sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1); 70 sleep_static_memctlr[1][0] = alchemy_rdsmem(AU1000_MEM_STCFG1);
71 sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1); 71 sleep_static_memctlr[1][1] = alchemy_rdsmem(AU1000_MEM_STTIME1);
72 sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1); 72 sleep_static_memctlr[1][2] = alchemy_rdsmem(AU1000_MEM_STADDR1);
73 sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2); 73 sleep_static_memctlr[2][0] = alchemy_rdsmem(AU1000_MEM_STCFG2);
74 sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2); 74 sleep_static_memctlr[2][1] = alchemy_rdsmem(AU1000_MEM_STTIME2);
75 sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2); 75 sleep_static_memctlr[2][2] = alchemy_rdsmem(AU1000_MEM_STADDR2);
76 sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); 76 sleep_static_memctlr[3][0] = alchemy_rdsmem(AU1000_MEM_STCFG3);
77 sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); 77 sleep_static_memctlr[3][1] = alchemy_rdsmem(AU1000_MEM_STTIME3);
78 sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); 78 sleep_static_memctlr[3][2] = alchemy_rdsmem(AU1000_MEM_STADDR3);
79} 79}
80 80
81static void restore_core_regs(void) 81static void restore_core_regs(void)
@@ -85,30 +85,28 @@ static void restore_core_regs(void)
85 * one of those Au1000 with a write-only PLL, where we dont 85 * one of those Au1000 with a write-only PLL, where we dont
86 * have a valid value) 86 * have a valid value)
87 */ 87 */
88 au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); 88 alchemy_wrsys(sleep_sys_clocks[0], AU1000_SYS_FREQCTRL0);
89 au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); 89 alchemy_wrsys(sleep_sys_clocks[1], AU1000_SYS_FREQCTRL1);
90 au_writel(sleep_sys_clocks[2], SYS_CLKSRC); 90 alchemy_wrsys(sleep_sys_clocks[2], AU1000_SYS_CLKSRC);
91 au_writel(sleep_sys_clocks[4], SYS_AUXPLL); 91 alchemy_wrsys(sleep_sys_clocks[4], AU1000_SYS_AUXPLL);
92 if (!au1xxx_cpu_has_pll_wo()) 92 if (!au1xxx_cpu_has_pll_wo())
93 au_writel(sleep_sys_clocks[3], SYS_CPUPLL); 93 alchemy_wrsys(sleep_sys_clocks[3], AU1000_SYS_CPUPLL);
94 au_sync();
95 94
96 au_writel(sleep_sys_pinfunc, SYS_PINFUNC); 95 alchemy_wrsys(sleep_sys_pinfunc, AU1000_SYS_PINFUNC);
97 au_sync();
98 96
99 /* Restore the static memory controller configuration. */ 97 /* Restore the static memory controller configuration. */
100 au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); 98 alchemy_wrsmem(sleep_static_memctlr[0][0], AU1000_MEM_STCFG0);
101 au_writel(sleep_static_memctlr[0][1], MEM_STTIME0); 99 alchemy_wrsmem(sleep_static_memctlr[0][1], AU1000_MEM_STTIME0);
102 au_writel(sleep_static_memctlr[0][2], MEM_STADDR0); 100 alchemy_wrsmem(sleep_static_memctlr[0][2], AU1000_MEM_STADDR0);
103 au_writel(sleep_static_memctlr[1][0], MEM_STCFG1); 101 alchemy_wrsmem(sleep_static_memctlr[1][0], AU1000_MEM_STCFG1);
104 au_writel(sleep_static_memctlr[1][1], MEM_STTIME1); 102 alchemy_wrsmem(sleep_static_memctlr[1][1], AU1000_MEM_STTIME1);
105 au_writel(sleep_static_memctlr[1][2], MEM_STADDR1); 103 alchemy_wrsmem(sleep_static_memctlr[1][2], AU1000_MEM_STADDR1);
106 au_writel(sleep_static_memctlr[2][0], MEM_STCFG2); 104 alchemy_wrsmem(sleep_static_memctlr[2][0], AU1000_MEM_STCFG2);
107 au_writel(sleep_static_memctlr[2][1], MEM_STTIME2); 105 alchemy_wrsmem(sleep_static_memctlr[2][1], AU1000_MEM_STTIME2);
108 au_writel(sleep_static_memctlr[2][2], MEM_STADDR2); 106 alchemy_wrsmem(sleep_static_memctlr[2][2], AU1000_MEM_STADDR2);
109 au_writel(sleep_static_memctlr[3][0], MEM_STCFG3); 107 alchemy_wrsmem(sleep_static_memctlr[3][0], AU1000_MEM_STCFG3);
110 au_writel(sleep_static_memctlr[3][1], MEM_STTIME3); 108 alchemy_wrsmem(sleep_static_memctlr[3][1], AU1000_MEM_STTIME3);
111 au_writel(sleep_static_memctlr[3][2], MEM_STADDR3); 109 alchemy_wrsmem(sleep_static_memctlr[3][2], AU1000_MEM_STADDR3);
112} 110}
113 111
114void au_sleep(void) 112void au_sleep(void)
diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c
index 8267e3c97721..ea8f41869e56 100644
--- a/arch/mips/alchemy/common/setup.c
+++ b/arch/mips/alchemy/common/setup.c
@@ -27,12 +27,9 @@
27 27
28#include <linux/init.h> 28#include <linux/init.h>
29#include <linux/ioport.h> 29#include <linux/ioport.h>
30#include <linux/jiffies.h>
31#include <linux/module.h>
32 30
33#include <asm/dma-coherence.h> 31#include <asm/dma-coherence.h>
34#include <asm/mipsregs.h> 32#include <asm/mipsregs.h>
35#include <asm/time.h>
36 33
37#include <au1000.h> 34#include <au1000.h>
38 35
@@ -41,18 +38,6 @@ extern void set_cpuspec(void);
41 38
42void __init plat_mem_setup(void) 39void __init plat_mem_setup(void)
43{ 40{
44 unsigned long est_freq;
45
46 /* determine core clock */
47 est_freq = au1xxx_calc_clock();
48 est_freq += 5000; /* round */
49 est_freq -= est_freq % 10000;
50 printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(),
51 est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000);
52
53 /* this is faster than wasting cycles trying to approximate it */
54 preset_lpj = (est_freq >> 1) / HZ;
55
56 if (au1xxx_cpu_needs_config_od()) 41 if (au1xxx_cpu_needs_config_od())
57 /* Various early Au1xx0 errata corrected by this */ 42 /* Various early Au1xx0 errata corrected by this */
58 set_c0_config(1 << 19); /* Set Config[OD] */ 43 set_c0_config(1 << 19); /* Set Config[OD] */
diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c
index 93fa586d52e2..50e17e13c18b 100644
--- a/arch/mips/alchemy/common/time.c
+++ b/arch/mips/alchemy/common/time.c
@@ -46,7 +46,7 @@
46 46
47static cycle_t au1x_counter1_read(struct clocksource *cs) 47static cycle_t au1x_counter1_read(struct clocksource *cs)
48{ 48{
49 return au_readl(SYS_RTCREAD); 49 return alchemy_rdsys(AU1000_SYS_RTCREAD);
50} 50}
51 51
52static struct clocksource au1x_counter1_clocksource = { 52static struct clocksource au1x_counter1_clocksource = {
@@ -60,12 +60,11 @@ static struct clocksource au1x_counter1_clocksource = {
60static int au1x_rtcmatch2_set_next_event(unsigned long delta, 60static int au1x_rtcmatch2_set_next_event(unsigned long delta,
61 struct clock_event_device *cd) 61 struct clock_event_device *cd)
62{ 62{
63 delta += au_readl(SYS_RTCREAD); 63 delta += alchemy_rdsys(AU1000_SYS_RTCREAD);
64 /* wait for register access */ 64 /* wait for register access */
65 while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) 65 while (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_M21)
66 ; 66 ;
67 au_writel(delta, SYS_RTCMATCH2); 67 alchemy_wrsys(delta, AU1000_SYS_RTCMATCH2);
68 au_sync();
69 68
70 return 0; 69 return 0;
71} 70}
@@ -112,31 +111,29 @@ static int __init alchemy_time_init(unsigned int m2int)
112 * (the 32S bit seems to be stuck set to 1 once a single clock- 111 * (the 32S bit seems to be stuck set to 1 once a single clock-
113 * edge is detected, hence the timeouts). 112 * edge is detected, hence the timeouts).
114 */ 113 */
115 if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK)) 114 if (CNTR_OK != (alchemy_rdsys(AU1000_SYS_CNTRCTRL) & CNTR_OK))
116 goto cntr_err; 115 goto cntr_err;
117 116
118 /* 117 /*
119 * setup counter 1 (RTC) to tick at full speed 118 * setup counter 1 (RTC) to tick at full speed
120 */ 119 */
121 t = 0xffffff; 120 t = 0xffffff;
122 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t) 121 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_T1S) && --t)
123 asm volatile ("nop"); 122 asm volatile ("nop");
124 if (!t) 123 if (!t)
125 goto cntr_err; 124 goto cntr_err;
126 125
127 au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */ 126 alchemy_wrsys(0, AU1000_SYS_RTCTRIM); /* 32.768 kHz */
128 au_sync();
129 127
130 t = 0xffffff; 128 t = 0xffffff;
131 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) 129 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
132 asm volatile ("nop"); 130 asm volatile ("nop");
133 if (!t) 131 if (!t)
134 goto cntr_err; 132 goto cntr_err;
135 au_writel(0, SYS_RTCWRITE); 133 alchemy_wrsys(0, AU1000_SYS_RTCWRITE);
136 au_sync();
137 134
138 t = 0xffffff; 135 t = 0xffffff;
139 while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) 136 while ((alchemy_rdsys(AU1000_SYS_CNTRCTRL) & SYS_CNTRL_C1S) && --t)
140 asm volatile ("nop"); 137 asm volatile ("nop");
141 if (!t) 138 if (!t)
142 goto cntr_err; 139 goto cntr_err;
diff --git a/arch/mips/alchemy/common/usb.c b/arch/mips/alchemy/common/usb.c
index d193dbea84a1..297805ade849 100644
--- a/arch/mips/alchemy/common/usb.c
+++ b/arch/mips/alchemy/common/usb.c
@@ -9,6 +9,7 @@
9 * 9 *
10 */ 10 */
11 11
12#include <linux/clk.h>
12#include <linux/init.h> 13#include <linux/init.h>
13#include <linux/io.h> 14#include <linux/io.h>
14#include <linux/module.h> 15#include <linux/module.h>
@@ -387,10 +388,25 @@ static inline void au1200_usb_init(void)
387 udelay(1000); 388 udelay(1000);
388} 389}
389 390
390static inline void au1000_usb_init(unsigned long rb, int reg) 391static inline int au1000_usb_init(unsigned long rb, int reg)
391{ 392{
392 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg); 393 void __iomem *base = (void __iomem *)KSEG1ADDR(rb + reg);
393 unsigned long r = __raw_readl(base); 394 unsigned long r = __raw_readl(base);
395 struct clk *c;
396
397 /* 48MHz check. Don't init if no one can provide it */
398 c = clk_get(NULL, "usbh_clk");
399 if (IS_ERR(c))
400 return -ENODEV;
401 if (clk_round_rate(c, 48000000) != 48000000) {
402 clk_put(c);
403 return -ENODEV;
404 }
405 if (clk_set_rate(c, 48000000)) {
406 clk_put(c);
407 return -ENODEV;
408 }
409 clk_put(c);
394 410
395#if defined(__BIG_ENDIAN) 411#if defined(__BIG_ENDIAN)
396 r |= USBHEN_BE; 412 r |= USBHEN_BE;
@@ -400,6 +416,8 @@ static inline void au1000_usb_init(unsigned long rb, int reg)
400 __raw_writel(r, base); 416 __raw_writel(r, base);
401 wmb(); 417 wmb();
402 udelay(1000); 418 udelay(1000);
419
420 return 0;
403} 421}
404 422
405 423
@@ -407,8 +425,15 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
407{ 425{
408 void __iomem *base = (void __iomem *)KSEG1ADDR(rb); 426 void __iomem *base = (void __iomem *)KSEG1ADDR(rb);
409 unsigned long r = __raw_readl(base + creg); 427 unsigned long r = __raw_readl(base + creg);
428 struct clk *c = clk_get(NULL, "usbh_clk");
429
430 if (IS_ERR(c))
431 return;
410 432
411 if (enable) { 433 if (enable) {
434 if (clk_prepare_enable(c))
435 goto out;
436
412 __raw_writel(r | USBHEN_CE, base + creg); 437 __raw_writel(r | USBHEN_CE, base + creg);
413 wmb(); 438 wmb();
414 udelay(1000); 439 udelay(1000);
@@ -423,7 +448,10 @@ static inline void __au1xx0_ohci_control(int enable, unsigned long rb, int creg)
423 } else { 448 } else {
424 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg); 449 __raw_writel(r & ~(USBHEN_CE | USBHEN_E), base + creg);
425 wmb(); 450 wmb();
451 clk_disable_unprepare(c);
426 } 452 }
453out:
454 clk_put(c);
427} 455}
428 456
429static inline int au1000_usb_control(int block, int enable, unsigned long rb, 457static inline int au1000_usb_control(int block, int enable, unsigned long rb,
@@ -457,11 +485,11 @@ int alchemy_usb_control(int block, int enable)
457 case ALCHEMY_CPU_AU1500: 485 case ALCHEMY_CPU_AU1500:
458 case ALCHEMY_CPU_AU1100: 486 case ALCHEMY_CPU_AU1100:
459 ret = au1000_usb_control(block, enable, 487 ret = au1000_usb_control(block, enable,
460 AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); 488 AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG);
461 break; 489 break;
462 case ALCHEMY_CPU_AU1550: 490 case ALCHEMY_CPU_AU1550:
463 ret = au1000_usb_control(block, enable, 491 ret = au1000_usb_control(block, enable,
464 AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); 492 AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG);
465 break; 493 break;
466 case ALCHEMY_CPU_AU1200: 494 case ALCHEMY_CPU_AU1200:
467 ret = au1200_usb_control(block, enable); 495 ret = au1200_usb_control(block, enable);
@@ -569,14 +597,18 @@ static struct syscore_ops alchemy_usb_pm_ops = {
569 597
570static int __init alchemy_usb_init(void) 598static int __init alchemy_usb_init(void)
571{ 599{
600 int ret = 0;
601
572 switch (alchemy_get_cputype()) { 602 switch (alchemy_get_cputype()) {
573 case ALCHEMY_CPU_AU1000: 603 case ALCHEMY_CPU_AU1000:
574 case ALCHEMY_CPU_AU1500: 604 case ALCHEMY_CPU_AU1500:
575 case ALCHEMY_CPU_AU1100: 605 case ALCHEMY_CPU_AU1100:
576 au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR, AU1000_OHCICFG); 606 ret = au1000_usb_init(AU1000_USB_OHCI_PHYS_ADDR,
607 AU1000_OHCICFG);
577 break; 608 break;
578 case ALCHEMY_CPU_AU1550: 609 case ALCHEMY_CPU_AU1550:
579 au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR, AU1550_OHCICFG); 610 ret = au1000_usb_init(AU1550_USB_OHCI_PHYS_ADDR,
611 AU1550_OHCICFG);
580 break; 612 break;
581 case ALCHEMY_CPU_AU1200: 613 case ALCHEMY_CPU_AU1200:
582 au1200_usb_init(); 614 au1200_usb_init();
@@ -586,8 +618,9 @@ static int __init alchemy_usb_init(void)
586 break; 618 break;
587 } 619 }
588 620
589 register_syscore_ops(&alchemy_usb_pm_ops); 621 if (!ret)
622 register_syscore_ops(&alchemy_usb_pm_ops);
590 623
591 return 0; 624 return ret;
592} 625}
593arch_initcall(alchemy_usb_init); 626arch_initcall(alchemy_usb_init);
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-03 18:04:22 -0500