21 files changed, 382 insertions, 20 deletions

diff --git a/Documentation/devicetree/bindings/clock/exynos4415-clock.txt b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
new file mode 100644
index 000000000000..847d98bae8cf
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos4415-clock.txt
@@ -0,0 +1,38 @@
+* Samsung Exynos4415 Clock Controller
+
+The Exynos4415 clock controller generates and supplies clock to various
+consumer devices within the Exynos4415 SoC.
+
+Required properties:
+
+- compatible: should be one of the following:
+  - "samsung,exynos4415-cmu" - for the main system clocks controller
+    (CMU_LEFTBUS, CMU_RIGHTBUS, CMU_TOP, CMU_CPU clock domains).
+  - "samsung,exynos4415-cmu-dmc" - for the Exynos4415 SoC DRAM Memory
+    Controller (DMC) domain clock controller.
+
+- reg: physical base address of the controller and length of memory mapped
+  region.
+
+- #clock-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes can use this identifier
+to specify the clock which they consume.
+
+All available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos4415.h header and can be used in device
+tree sources.
+
+Example 1: An example of a clock controller node is listed below.
+
+        cmu: clock-controller@10030000 {
+                compatible = "samsung,exynos4415-cmu";
+                reg = <0x10030000 0x18000>;
+                #clock-cells = <1>;
+        };
+
+        cmu-dmc: clock-controller@105C0000 {
+                compatible = "samsung,exynos4415-cmu-dmc";
+                reg = <0x105C0000 0x3000>;
+                #clock-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/clock/exynos7-clock.txt b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
new file mode 100644
index 000000000000..6d3d5f80c1c3
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/exynos7-clock.txt
@@ -0,0 +1,93 @@
+* Samsung Exynos7 Clock Controller
+
+Exynos7 clock controller has various blocks which are instantiated
+independently from the device-tree. These clock controllers
+generate and supply clocks to various hardware blocks within
+the SoC.
+
+Each clock is assigned an identifier and client nodes can use
+this identifier to specify the clock which they consume. All
+available clocks are defined as preprocessor macros in
+dt-bindings/clock/exynos7-clk.h header and can be used in
+device tree sources.
+
+External clocks:
+
+There are several clocks that are generated outside the SoC. It
+is expected that they are defined using standard clock bindings
+with following clock-output-names:
+
+ - "fin_pll" - PLL input clock from XXTI
+
+Required Properties for Clock Controller:
+
+ - compatible: clock controllers will use one of the following
+        compatible strings to indicate the clock controller
+        functionality.
+
+        - "samsung,exynos7-clock-topc"
+        - "samsung,exynos7-clock-top0"
+        - "samsung,exynos7-clock-top1"
+        - "samsung,exynos7-clock-ccore"
+        - "samsung,exynos7-clock-peric0"
+        - "samsung,exynos7-clock-peric1"
+        - "samsung,exynos7-clock-peris"
+        - "samsung,exynos7-clock-fsys0"
+        - "samsung,exynos7-clock-fsys1"
+
+ - reg: physical base address of the controller and the length of
+        memory mapped region.
+
+ - #clock-cells: should be 1.
+
+ - clocks: list of clock identifiers which are fed as the input to
+        the given clock controller. Please refer the next section to
+        find the input clocks for a given controller.
+
+- clock-names: list of names of clocks which are fed as the input
+        to the given clock controller.
+
+Input clocks for top0 clock controller:
+        - fin_pll
+        - dout_sclk_bus0_pll
+        - dout_sclk_bus1_pll
+        - dout_sclk_cc_pll
+        - dout_sclk_mfc_pll
+
+Input clocks for top1 clock controller:
+        - fin_pll
+        - dout_sclk_bus0_pll
+        - dout_sclk_bus1_pll
+        - dout_sclk_cc_pll
+        - dout_sclk_mfc_pll
+
+Input clocks for ccore clock controller:
+        - fin_pll
+        - dout_aclk_ccore_133
+
+Input clocks for peric0 clock controller:
+        - fin_pll
+        - dout_aclk_peric0_66
+        - sclk_uart0
+
+Input clocks for peric1 clock controller:
+        - fin_pll
+        - dout_aclk_peric1_66
+        - sclk_uart1
+        - sclk_uart2
+        - sclk_uart3
+
+Input clocks for peris clock controller:
+        - fin_pll
+        - dout_aclk_peris_66
+
+Input clocks for fsys0 clock controller:
+        - fin_pll
+        - dout_aclk_fsys0_200
+        - dout_sclk_mmc2
+
+Input clocks for fsys1 clock controller:
+        - fin_pll
+        - dout_aclk_fsys1_200
+        - dout_sclk_mmc0
+        - dout_sclk_mmc1
diff --git a/Documentation/devicetree/bindings/clock/marvell,mmp2.txt b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
new file mode 100644
index 000000000000..af376a01f2b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,mmp2.txt
@@ -0,0 +1,21 @@
+* Marvell MMP2 Clock Controller
+
+The MMP2 clock subsystem generates and supplies clock to various
+controllers within the MMP2 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,mmp2-clock" - controller compatible with MMP2 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-mmp2.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa168.txt b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt
new file mode 100644
index 000000000000..c62eb1d173a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,pxa168.txt
@@ -0,0 +1,21 @@
+* Marvell PXA168 Clock Controller
+
+The PXA168 clock subsystem generates and supplies clock to various
+controllers within the PXA168 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa168-clock" - controller compatible with PXA168 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 3 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc". So three reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell,pxa168.h>.
diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa910.txt b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt
new file mode 100644
index 000000000000..d9f41f3c03a0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/marvell,pxa910.txt
@@ -0,0 +1,21 @@
+* Marvell PXA910 Clock Controller
+
+The PXA910 clock subsystem generates and supplies clock to various
+controllers within the PXA910 SoC.
+
+Required Properties:
+
+- compatible: should be one of the following.
+  - "marvell,pxa910-clock" - controller compatible with PXA910 SoC.
+
+- reg: physical base address of the clock subsystem and length of memory mapped
+  region. There are 4 places in SOC has clock control logic:
+  "mpmu", "apmu", "apbc", "apbcp". So four reg spaces need to be defined.
+
+- #clock-cells: should be 1.
+- #reset-cells: should be 1.
+
+Each clock is assigned an identifier and client nodes use this identifier
+to specify the clock which they consume.
+
+All these identifier could be found in <dt-bindings/clock/marvell-pxa910.h>.
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
index 952e373178d2..054f65f9319c 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clocks.txt
@@ -7,11 +7,16 @@ to 64.
 Required Properties:
 
   - compatible: Must be one of the following
+    - "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
+    - "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
     - "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
     - "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2) DIV6 clocks
+    - "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
     - "renesas,cpg-div6-clock" for generic DIV6 clocks
   - reg: Base address and length of the memory resource used by the DIV6 clock
-  - clocks: Reference to the parent clock
+  - clocks: Reference to the parent clock(s); either one, four, or eight
+    clocks must be specified.  For clocks with multiple parents, invalid
+    settings must be specified as "<0>".
   - #clock-cells: Must be 0
   - clock-output-names: The name of the clock as a free-form string
 
@@ -19,10 +24,11 @@ Required Properties:
 Example
 -------
 
-        sd2_clk: sd2_clk@e6150078 {
-                compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
-                reg = <0 0xe6150078 0 4>;
-                clocks = <&pll1_div2_clk>;
+        sdhi2_clk: sdhi2_clk@e615007c {
+                compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
+                reg = <0 0xe615007c 0 4>;
+                clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
+                         <0>, <&extal2_clk>;
                 #clock-cells = <0>;
-                clock-output-names = "sd2";
+                clock-output-names = "sdhi2ck";
         };
diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
index a5f52238c80d..2e18676bd4b5 100644
--- a/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
+++ b/Documentation/devicetree/bindings/clock/renesas,cpg-mstp-clocks.txt
@@ -26,11 +26,11 @@ Required Properties:
     must appear in the same order as the output clocks.
   - #clock-cells: Must be 1
   - clock-output-names: The name of the clocks as free-form strings
-  - renesas,clock-indices: Indices of the gate clocks into the group (0 to 31)
+  - clock-indices: Indices of the gate clocks into the group (0 to 31)
 
-The clocks, clock-output-names and renesas,clock-indices properties contain one
-entry per gate clock. The MSTP groups are sparsely populated. Unimplemented
-gate clocks must not be declared.
+The clocks, clock-output-names and clock-indices properties contain one entry
+per gate clock. The MSTP groups are sparsely populated. Unimplemented gate
+clocks must not be declared.
 
 
 Example
diff --git a/Documentation/devicetree/bindings/clock/sunxi.txt b/Documentation/devicetree/bindings/clock/sunxi.txt
index ed116df9c3e7..67b2b99f2b33 100644
--- a/Documentation/devicetree/bindings/clock/sunxi.txt
+++ b/Documentation/devicetree/bindings/clock/sunxi.txt
@@ -10,14 +10,17 @@ Required properties:
         "allwinner,sun4i-a10-pll1-clk" - for the main PLL clock and PLL4
         "allwinner,sun6i-a31-pll1-clk" - for the main PLL clock on A31
         "allwinner,sun8i-a23-pll1-clk" - for the main PLL clock on A23
+        "allwinner,sun9i-a80-pll4-clk" - for the peripheral PLLs on A80
         "allwinner,sun4i-a10-pll5-clk" - for the PLL5 clock
         "allwinner,sun4i-a10-pll6-clk" - for the PLL6 clock
         "allwinner,sun6i-a31-pll6-clk" - for the PLL6 clock on A31
+        "allwinner,sun9i-a80-gt-clk" - for the GT bus clock on A80
         "allwinner,sun4i-a10-cpu-clk" - for the CPU multiplexer clock
         "allwinner,sun4i-a10-axi-clk" - for the AXI clock
         "allwinner,sun8i-a23-axi-clk" - for the AXI clock on A23
         "allwinner,sun4i-a10-axi-gates-clk" - for the AXI gates
         "allwinner,sun4i-a10-ahb-clk" - for the AHB clock
+        "allwinner,sun9i-a80-ahb-clk" - for the AHB bus clocks on A80
         "allwinner,sun4i-a10-ahb-gates-clk" - for the AHB gates on A10
         "allwinner,sun5i-a13-ahb-gates-clk" - for the AHB gates on A13
         "allwinner,sun5i-a10s-ahb-gates-clk" - for the AHB gates on A10s
@@ -26,24 +29,29 @@ Required properties:
         "allwinner,sun6i-a31-ahb1-mux-clk" - for the AHB1 multiplexer on A31
         "allwinner,sun6i-a31-ahb1-gates-clk" - for the AHB1 gates on A31
         "allwinner,sun8i-a23-ahb1-gates-clk" - for the AHB1 gates on A23
+        "allwinner,sun9i-a80-ahb0-gates-clk" - for the AHB0 gates on A80
+        "allwinner,sun9i-a80-ahb1-gates-clk" - for the AHB1 gates on A80
+        "allwinner,sun9i-a80-ahb2-gates-clk" - for the AHB2 gates on A80
         "allwinner,sun4i-a10-apb0-clk" - for the APB0 clock
         "allwinner,sun6i-a31-apb0-clk" - for the APB0 clock on A31
         "allwinner,sun8i-a23-apb0-clk" - for the APB0 clock on A23
+        "allwinner,sun9i-a80-apb0-clk" - for the APB0 bus clock on A80
         "allwinner,sun4i-a10-apb0-gates-clk" - for the APB0 gates on A10
         "allwinner,sun5i-a13-apb0-gates-clk" - for the APB0 gates on A13
         "allwinner,sun5i-a10s-apb0-gates-clk" - for the APB0 gates on A10s
         "allwinner,sun6i-a31-apb0-gates-clk" - for the APB0 gates on A31
         "allwinner,sun7i-a20-apb0-gates-clk" - for the APB0 gates on A20
         "allwinner,sun8i-a23-apb0-gates-clk" - for the APB0 gates on A23
+        "allwinner,sun9i-a80-apb0-gates-clk" - for the APB0 gates on A80
         "allwinner,sun4i-a10-apb1-clk" - for the APB1 clock
-        "allwinner,sun4i-a10-apb1-mux-clk" - for the APB1 clock muxing
+        "allwinner,sun9i-a80-apb1-clk" - for the APB1 bus clock on A80
         "allwinner,sun4i-a10-apb1-gates-clk" - for the APB1 gates on A10
         "allwinner,sun5i-a13-apb1-gates-clk" - for the APB1 gates on A13
         "allwinner,sun5i-a10s-apb1-gates-clk" - for the APB1 gates on A10s
         "allwinner,sun6i-a31-apb1-gates-clk" - for the APB1 gates on A31
         "allwinner,sun7i-a20-apb1-gates-clk" - for the APB1 gates on A20
         "allwinner,sun8i-a23-apb1-gates-clk" - for the APB1 gates on A23
-        "allwinner,sun6i-a31-apb2-div-clk" - for the APB2 gates on A31
+        "allwinner,sun9i-a80-apb1-gates-clk" - for the APB1 gates on A80
         "allwinner,sun6i-a31-apb2-gates-clk" - for the APB2 gates on A31
         "allwinner,sun8i-a23-apb2-gates-clk" - for the APB2 gates on A23
         "allwinner,sun5i-a13-mbus-clk" - for the MBUS clock on A13
@@ -63,8 +71,9 @@ Required properties for all clocks:
         multiplexed clocks, the list order must match the hardware
         programming order.
 - #clock-cells : from common clock binding; shall be set to 0 except for
-        "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk" and
-        "allwinner,sun4i-pll6-clk" where it shall be set to 1
+        the following compatibles where it shall be set to 1:
+        "allwinner,*-gates-clk", "allwinner,sun4i-pll5-clk",
+        "allwinner,sun4i-pll6-clk", "allwinner,sun6i-a31-pll6-clk"
 - clock-output-names : shall be the corresponding names of the outputs.
         If the clock module only has one output, the name shall be the
         module name.
@@ -79,6 +88,12 @@ Clock consumers should specify the desired clocks they use with a
 "clocks" phandle cell. Consumers that are using a gated clock should
 provide an additional ID in their clock property. This ID is the
 offset of the bit controlling this particular gate in the register.
+For the other clocks with "#clock-cells" = 1, the additional ID shall
+refer to the index of the output.
+
+For "allwinner,sun6i-a31-pll6-clk", there are 2 outputs. The first output
+is the normal PLL6 output, or "pll6". The second output is rate doubled
+PLL6, or "pll6x2".
 
 For example:
 
@@ -106,6 +121,14 @@ pll5: clk@01c20020 {
         clock-output-names = "pll5_ddr", "pll5_other";
 };
 
+pll6: clk@01c20028 {
+        #clock-cells = <1>;
+        compatible = "allwinner,sun6i-a31-pll6-clk";
+        reg = <0x01c20028 0x4>;
+        clocks = <&osc24M>;
+        clock-output-names = "pll6", "pll6x2";
+};
+
 cpu: cpu@01c20054 {
         #clock-cells = <0>;
         compatible = "allwinner,sun4i-a10-cpu-clk";
diff --git a/Documentation/devicetree/bindings/mailbox/mailbox.txt b/Documentation/devicetree/bindings/mailbox/mailbox.txt
new file mode 100644
index 000000000000..1a2cd3d266db
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/mailbox.txt
@@ -0,0 +1,38 @@
+* Generic Mailbox Controller and client driver bindings
+
+Generic binding to provide a way for Mailbox controller drivers to
+assign appropriate mailbox channel to client drivers.
+
+* Mailbox Controller
+
+Required property:
+- #mbox-cells: Must be at least 1. Number of cells in a mailbox
+                specifier.
+
+Example:
+        mailbox: mailbox {
+                ...
+                #mbox-cells = <1>;
+        };
+
+
+* Mailbox Client
+
+Required property:
+- mboxes: List of phandle and mailbox channel specifiers.
+
+Optional property:
+- mbox-names: List of identifier strings for each mailbox channel
+                required by the client. The use of this property
+                is discouraged in favor of using index in list of
+                'mboxes' while requesting a mailbox. Instead the
+                platforms may define channel indices, in DT headers,
+                to something legible.
+
+Example:
+        pwr_cntrl: power {
+                ...
+                mbox-names = "pwr-ctrl", "rpc";
+                mboxes = <&mailbox 0
+                        &mailbox 1>;
+        };
diff --git a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
index 0f8487b88822..e77e167593db 100644
--- a/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
+++ b/Documentation/devicetree/bindings/net/smsc-lan91c111.txt
@@ -11,3 +11,5 @@ Optional properties:
   are supported on the device.  Valid value for SMSC LAN91c111 are
   1, 2 or 4.  If it's omitted or invalid, the size would be 2 meaning
   16-bit access only.
+- power-gpios: GPIO to control the PWRDWN pin
+- reset-gpios: GPIO to control the RESET pin
diff --git a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
index 0bda229a6171..3899d6a557c1 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-fsl-ftm.txt
@@ -1,5 +1,20 @@
 Freescale FlexTimer Module (FTM) PWM controller
 
+The same FTM PWM device can have a different endianness on different SoCs. The
+device tree provides a property to describing this so that an operating system
+device driver can handle all variants of the device. Refer to the table below
+for the endianness of the FTM PWM block as integrated into the existing SoCs:
+
+        SoC     | FTM-PWM endianness
+        --------+-------------------
+        Vybrid  | LE
+        LS1     | BE
+        LS2     | LE
+
+Please see ../regmap/regmap.txt for more detail about how to specify endian
+modes in device tree.
+
+
 Required properties:
 - compatible: Should be "fsl,vf610-ftm-pwm".
 - reg: Physical base address and length of the controller's registers
@@ -16,7 +31,8 @@ Required properties:
 - pinctrl-names: Must contain a "default" entry.
 - pinctrl-NNN: One property must exist for each entry in pinctrl-names.
   See pinctrl/pinctrl-bindings.txt for details of the property values.
-
+- big-endian: Boolean property, required if the FTM PWM registers use a big-
+  endian rather than little-endian layout.
 
 Example:
 
@@ -32,4 +48,5 @@ pwm0: pwm@40038000 {
                         <&clks VF610_CLK_FTM0_EXT_FIX_EN>;
                 pinctrl-names = "default";
                 pinctrl-0 = <&pinctrl_pwm0_1>;
+                big-endian;
 };
diff --git a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
index d47d15a6a298..b8be3d09ee26 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
+++ b/Documentation/devicetree/bindings/pwm/pwm-rockchip.txt
@@ -7,8 +7,8 @@ Required properties:
    "rockchip,vop-pwm": found integrated in VOP on RK3288 SoC
  - reg: physical base address and length of the controller's registers
  - clocks: phandle and clock specifier of the PWM reference clock
- - #pwm-cells: should be 2. See pwm.txt in this directory for a
-   description of the cell format.
+ - #pwm-cells: must be 2 (rk2928) or 3 (rk3288). See pwm.txt in this directory
+   for a description of the cell format.
 
 Example:
 
diff --git a/Documentation/devicetree/bindings/sound/sgtl5000.txt b/Documentation/devicetree/bindings/sound/sgtl5000.txt
index 955df60a118c..d556dcb8816b 100644
--- a/Documentation/devicetree/bindings/sound/sgtl5000.txt
+++ b/Documentation/devicetree/bindings/sound/sgtl5000.txt
@@ -7,10 +7,20 @@ Required properties:
 
 - clocks : the clock provider of SYS_MCLK
 
+- VDDA-supply : the regulator provider of VDDA
+
+- VDDIO-supply: the regulator provider of VDDIO
+
+Optional properties:
+
+- VDDD-supply : the regulator provider of VDDD
+
 Example:
 
 codec: sgtl5000@0a {
         compatible = "fsl,sgtl5000";
         reg = <0x0a>;
         clocks = <&clks 150>;
+        VDDA-supply = <&reg_3p3v>;
+        VDDIO-supply = <&reg_3p3v>;
 };
diff --git a/Documentation/devicetree/bindings/submitting-patches.txt b/Documentation/devicetree/bindings/submitting-patches.txt
index 042a0273b8ba..b7ba01ad1426 100644
--- a/Documentation/devicetree/bindings/submitting-patches.txt
+++ b/Documentation/devicetree/bindings/submitting-patches.txt
@@ -12,6 +12,9 @@ I. For patch submitters
 
        devicetree@vger.kernel.org
 
+  3) The Documentation/ portion of the patch should come in the series before
+     the code implementing the binding.
+
 II. For kernel maintainers
 
   1) If you aren't comfortable reviewing a given binding, reply to it and ask
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
index 1f0f67234a91..3c67bd50aa10 100644
--- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
@@ -1,7 +1,10 @@
 * Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
 
 Required properties:
-- compatible : "fsl,imx6q-thermal"
+- compatible : "fsl,imx6q-tempmon" for i.MX6Q, "fsl,imx6sx-tempmon" for i.MX6SX.
+  i.MX6SX has two more IRQs than i.MX6Q, one is IRQ_LOW and the other is IRQ_PANIC,
+  when temperature is below than low threshold, IRQ_LOW will be triggered, when temperature
+  is higher than panic threshold, system will auto reboot by SRC module.
 - fsl,tempmon : phandle pointer to system controller that contains TEMPMON
   control registers, e.g. ANATOP on imx6q.
 - fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 0ef00be44b01..43404b197933 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -7,7 +7,10 @@ Required properties:
                             - "renesas,thermal-r8a73a4" (R-Mobile AP6)
                             - "renesas,thermal-r8a7779" (R-Car H1)
                             - "renesas,thermal-r8a7790" (R-Car H2)
-                            - "renesas,thermal-r8a7791" (R-Car M2)
+                            - "renesas,thermal-r8a7791" (R-Car M2-W)
+                            - "renesas,thermal-r8a7792" (R-Car V2H)
+                            - "renesas,thermal-r8a7793" (R-Car M2-N)
+                            - "renesas,thermal-r8a7794" (R-Car E2)
 - reg                   : Address range of the thermal registers.
                           The 1st reg will be recognized as common register
                           if it has "interrupts".
diff --git a/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt b/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt
new file mode 100644
index 000000000000..c3a36ee45552
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/cadence-wdt.txt
@@ -0,0 +1,24 @@
+Zynq Watchdog Device Tree Bindings
+-------------------------------------------
+
+Required properties:
+- compatible            : Should be "cdns,wdt-r1p2".
+- clocks                : This is pclk (APB clock).
+- interrupts            : This is wd_irq - watchdog timeout interrupt.
+- interrupt-parent      : Must be core interrupt controller.
+
+Optional properties
+- reset-on-timeout      : If this property exists, then a reset is done
+                          when watchdog times out.
+- timeout-sec           : Watchdog timeout value (in seconds).
+
+Example:
+        watchdog@f8005000 {
+                compatible = "cdns,wdt-r1p2";
+                clocks = <&clkc 45>;
+                interrupt-parent = <&intc>;
+                interrupts = <0 9 1>;
+                reg = <0xf8005000 0x1000>;
+                reset-on-timeout;
+                timeout-sec = <10>;
+        };
diff --git a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt
index e52ba2da868c..8dab6fd024aa 100644
--- a/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt
@@ -7,7 +7,8 @@ Required properties:
 
 Optional property:
 - big-endian: If present the watchdog device's registers are implemented
-  in big endian mode, otherwise in little mode.
+  in big endian mode, otherwise in native mode(same with CPU), for more
+  detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
 
 Examples:
 
diff --git a/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt b/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt
new file mode 100644
index 000000000000..9200fc2d508c
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/meson6-wdt.txt
@@ -0,0 +1,13 @@
+Meson SoCs Watchdog timer
+
+Required properties:
+
+- compatible : should be "amlogic,meson6-wdt"
+- reg : Specifies base physical address and size of the registers.
+
+Example:
+
+wdt: watchdog@c1109900 {
+        compatible = "amlogic,meson6-wdt";
+        reg = <0xc1109900 0x8>;
+};
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
new file mode 100644
index 000000000000..4726924d034e
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.txt
@@ -0,0 +1,24 @@
+Qualcomm Krait Processor Sub-system (KPSS) Watchdog
+---------------------------------------------------
+
+Required properties :
+- compatible : shall contain only one of the following:
+
+                        "qcom,kpss-wdt-msm8960"
+                        "qcom,kpss-wdt-apq8064"
+                        "qcom,kpss-wdt-ipq8064"
+
+- reg : shall contain base register location and length
+- clocks : shall contain the input clock
+
+Optional properties :
+- timeout-sec : shall contain the default watchdog timeout in seconds,
+                if unset, the default timeout is 30 seconds
+
+Example:
+        watchdog@208a038 {
+                compatible = "qcom,kpss-wdt-ipq8064";
+                reg = <0x0208a038 0x40>;
+                clocks = <&sleep_clk>;
+                timeout-sec = <10>;
+        };
diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
index cfff37511aac..8f3d96af81d7 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.txt
@@ -9,6 +9,7 @@ Required properties:
         (a) "samsung,s3c2410-wdt" for Exynos4 and previous SoCs
         (b) "samsung,exynos5250-wdt" for Exynos5250
         (c) "samsung,exynos5420-wdt" for Exynos5420
+        (c) "samsung,exynos7-wdt" for Exynos7
 
 - reg : base physical address of the controller and length of memory mapped
         region.