40 files changed, 667 insertions, 51 deletions
diff --git a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
index f4445e5a2bbb..1e097037349c 100644
--- a/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
+++ b/Documentation/devicetree/bindings/arm/exynos/power_domain.txt
@@ -22,6 +22,8 @@ Optional Properties:
        - pclkN, clkN: Pairs of parent of input clock and input clock to the
                devices in this power domain. Maximum of 4 pairs (N = 0 to 3)
                are supported currently.
+- power-domains: phandle pointing to the parent power domain, for more details
+                 see Documentation/devicetree/bindings/power/power_domain.txt
 Node of a device using power domains must have a power-domains property
 defined with a phandle to respective power domain.
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
new file mode 100644
index 000000000000..44aa3c451ccf
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-cpucfg.txt
@@ -0,0 +1,14 @@
+Freescale Vybrid Miscellaneous System Control - CPU Configuration
+The MSCM IP contains multiple sub modules, this binding describes the first
+block of registers which contains CPU configuration information.
+Required properties:
+- compatible:   "fsl,vf610-mscm-cpucfg", "syscon"
+- reg:          the register range of the MSCM CPU configuration registers
+Example:
+        mscm_cpucfg: cpucfg@40001000 {
+                compatible = "fsl,vf610-mscm-cpucfg", "syscon";
+                reg = <0x40001000 0x800>;
+        }
diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
new file mode 100644
index 000000000000..669808b2af49
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/freescale/fsl,vf610-mscm-ir.txt
@@ -0,0 +1,33 @@
+Freescale Vybrid Miscellaneous System Control - Interrupt Router
+The MSCM IP contains multiple sub modules, this binding describes the second
+block of registers which control the interrupt router. The interrupt router
+allows to configure the recipient of each peripheral interrupt. Furthermore
+it controls the directed processor interrupts. The module is available in all
+Vybrid SoC's but is only really useful in dual core configurations (VF6xx
+which comes with a Cortex-A5/Cortex-M4 combination).
+Required properties:
+- compatible:           "fsl,vf610-mscm-ir"
+- reg:                  the register range of the MSCM Interrupt Router
+- fsl,cpucfg:           The handle to the MSCM CPU configuration node, required
+                        to get the current CPU ID
+- interrupt-controller: Identifies the node as an interrupt controller
+- #interrupt-cells:     Two cells, interrupt number and cells.
+                        The hardware interrupt number according to interrupt
+                        assignment of the interrupt router is required.
+                        Flags get passed only when using GIC as parent. Flags
+                        encoding as documented by the GIC bindings.
+- interrupt-parent:     Should be the phandle for the interrupt controller of
+                        the CPU the device tree is intended to be used on. This
+                        is either the node of the GIC or NVIC controller.
+Example:
+        mscm_ir: interrupt-controller@40001800 {
+                compatible = "fsl,vf610-mscm-ir";
+                reg = <0x40001800 0x400>;
+                fsl,cpucfg = <&mscm_cpucfg>;
+                interrupt-controller;
+                #interrupt-cells = <2>;
+                interrupt-parent = <&intc>;
+        }
diff --git a/Documentation/devicetree/bindings/arm/gic.txt b/Documentation/devicetree/bindings/arm/gic.txt
index c97484b73e72..1e0d21201d3a 100644
--- a/Documentation/devicetree/bindings/arm/gic.txt
+++ b/Documentation/devicetree/bindings/arm/gic.txt
@@ -56,11 +56,6 @@ Optional
  regions, used when the GIC doesn't have banked registers. The offset is
  cpu-offset * cpu-nr.
- arm,routable-irqs : Total number of gic irq inputs which are not directly
-                  connected from the peripherals, but are routed dynamically
-                  by a crossbar/multiplexer preceding the GIC. The GIC irq
-                  input line is assigned dynamically when the corresponding
-                  peripheral's crossbar line is mapped.
 Example:
        intc: interrupt-controller@fff11000 {
@@ -68,7 +63,6 @@ Example:
                #interrupt-cells = <3>;
                #address-cells = <1>;
                interrupt-controller;
-                arm,routable-irqs = <160>;
                reg = <0xfff11000 0x1000>,
                      <0xfff10100 0x100>;
        };
diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
index 4139db353d0a..a9b28d74d902 100644
--- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt
+++ b/Documentation/devicetree/bindings/arm/omap/crossbar.txt
@@ -9,7 +9,9 @@ inputs.
 Required properties:
 - compatible : Should be "ti,irq-crossbar"
 - reg: Base address and the size of the crossbar registers.
- ti,max-irqs: Total number of irqs available at the interrupt controller.
+- interrupt-controller: indicates that this block is an interrupt controller.
+- interrupt-parent: the interrupt controller this block is connected to.
+- ti,max-irqs: Total number of irqs available at the parent interrupt controller.
 - ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed.
 - ti,reg-size: Size of a individual register in bytes. Every individual
            register is assumed to be of same size. Valid sizes are 1, 2, 4.
@@ -27,13 +29,13 @@ Optional properties:
  when the interrupt controller irq is unused (when not provided, default is 0)
 Examples:
-                crossbar_mpu: @4a020000 {
+                crossbar_mpu: crossbar@4a002a48 {
                        compatible = "ti,irq-crossbar";
                        reg = <0x4a002a48 0x130>;
                        ti,max-irqs = <160>;
                        ti,max-crossbar-sources = <400>;
                        ti,reg-size = <2>;
-                        ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>;
+                        ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
                        ti,irqs-skip = <10 133 139 140>;
                };
@@ -44,10 +46,6 @@ Documentation/devicetree/bindings/arm/gic.txt for further details.
 An interrupt consumer on an SoC using crossbar will use:
        interrupts = <GIC_SPI request_number interrupt_level>
-When the request number is between 0 to that described by
-"ti,max-crossbar-sources", it is assumed to be a crossbar mapping. If the
-request_number is greater than "ti,max-crossbar-sources", then it is mapped as a
-quirky hardware mapping direct to GIC.
 Example:
        device_x@0x4a023000 {
@@ -55,9 +53,3 @@ Example:
                interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                ...
        };
-        device_y@0x4a033000 {
-                /* Direct mapped GIC SPI 1 used */
-                interrupts = <GIC_SPI DIRECT_IRQ(1) IRQ_TYPE_LEVEL_HIGH>;
-                ...
-        };
diff --git a/Documentation/devicetree/bindings/arm/samsung/pmu.txt b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
index 67b211381f2b..2d6356d8daf4 100644
--- a/Documentation/devicetree/bindings/arm/samsung/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/samsung/pmu.txt
@@ -29,10 +29,27 @@ Properties:
 - clocks : list of phandles and specifiers to all input clocks listed in
                clock-names property.
+Optional properties:
+Some PMUs are capable of behaving as an interrupt controller (mostly
+to wake up a suspended PMU). In which case, they can have the
+following properties:
+- interrupt-controller: indicate that said PMU is an interrupt controller
+- #interrupt-cells: must be identical to the that of the parent interrupt
+  controller.
+- interrupt-parent: a phandle indicating which interrupt controller
+  this PMU signals interrupts to.
 Example :
 pmu_system_controller: system-controller@10040000 {
        compatible = "samsung,exynos5250-pmu", "syscon";
        reg = <0x10040000 0x5000>;
+        interrupt-controller;
+        #interrupt-cells = <3>;
+        interrupt-parent = <&gic>;
        #clock-cells = <1>;
        clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
                        "clkout4", "clkout8", "clkout9";
diff --git a/Documentation/devicetree/bindings/arm/sti.txt b/Documentation/devicetree/bindings/arm/sti.txt
index d70ec358736c..8d27f6b084c7 100644
--- a/Documentation/devicetree/bindings/arm/sti.txt
+++ b/Documentation/devicetree/bindings/arm/sti.txt
@@ -13,6 +13,10 @@ Boards with the ST STiH407 SoC shall have the following properties:
 Required root node property:
 compatible = "st,stih407";
+Boards with the ST STiH410 SoC shall have the following properties:
+Required root node property:
+compatible = "st,stih410";
 Boards with the ST STiH418 SoC shall have the following properties:
 Required root node property:
 compatible = "st,stih418";
diff --git a/Documentation/devicetree/bindings/ata/ahci-st.txt b/Documentation/devicetree/bindings/ata/ahci-st.txt
index 0574a77a0b9f..e1d01df8e3c1 100644
--- a/Documentation/devicetree/bindings/ata/ahci-st.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-st.txt
@@ -3,29 +3,48 @@ STMicroelectronics STi SATA controller
 This binding describes a SATA device.
 Required properties:
- - compatible      : Must be "st,sti-ahci"
+ - compatible      : Must be "st,ahci"
 - reg             : Physical base addresses and length of register sets
 - interrupts      : Interrupt associated with the SATA device
 - interrupt-names :   Associated name must be; "hostc"
- - resets          : The power-down and soft-reset lines of SATA IP
- - reset-names     :   Associated names must be; "pwr-dwn" and "sw-rst"
 - clocks          : The phandle for the clock
 - clock-names     :   Associated name must be; "ahci_clk"
- - phys            : The phandle for the PHY device
+ - phys            : The phandle for the PHY port
 - phy-names       :   Associated name must be; "ahci_phy"
+Optional properties:
+ - resets          : The power-down, soft-reset and power-reset lines of SATA IP
+ - reset-names     :   Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst"
 Example:
+        /* Example for stih416 */
        sata0: sata@fe380000 {
-                compatible      = "st,sti-ahci";
+                compatible      = "st,ahci";
-                reg             = <0xfe380000 0x1000>;
+                reg             = <0xfe380000 0x1000>;
-                interrupts      = <GIC_SPI 157 IRQ_TYPE_NONE>;
+                interrupts      = <GIC_SPI 157 IRQ_TYPE_NONE>;
-                interrupt-names = "hostc";
+                interrupt-names = "hostc";
-                phys            = <&miphy365x_phy MIPHY_PORT_0 MIPHY_TYPE_SATA>;
+                phys            = <&phy_port0 PHY_TYPE_SATA>;
-                phy-names       = "ahci_phy";
+                phy-names       = "ahci_phy";
-                resets          = <&powerdown STIH416_SATA0_POWERDOWN>,
+                resets          = <&powerdown STIH416_SATA0_POWERDOWN>,
                                  <&softreset STIH416_SATA0_SOFTRESET>;
-                reset-names     = "pwr-dwn", "sw-rst";
+                reset-names     = "pwr-dwn", "sw-rst";
-                clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
+                clocks          = <&clk_s_a0_ls CLK_ICN_REG>;
-                clock-names     = "ahci_clk";
+                clock-names     = "ahci_clk";
+        };
+        /* Example for stih407 family silicon */
+        sata0: sata@9b20000 {
+                compatible      = "st,ahci";
+                reg             = <0x9b20000 0x1000>;
+                interrupts      = <GIC_SPI 159 IRQ_TYPE_NONE>;
+                interrupt-names = "hostc";
+                phys            = <&phy_port0 PHY_TYPE_SATA>;
+                phy-names       = "ahci_phy";
+                resets          = <&powerdown STIH407_SATA0_POWERDOWN>,
+                                  <&softreset STIH407_SATA0_SOFTRESET>,
+                                  <&softreset STIH407_SATA0_PWR_SOFTRESET>;
+                reset-names     = "pwr-dwn", "sw-rst", "pwr-rst";
+                clocks          = <&clk_s_c0_flexgen CLK_ICN_REG>;
+                clock-names     = "ahci_clk";
        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-fan.txt b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
index 2dd457a3469a..439a7430fc68 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-fan.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
@@ -2,15 +2,20 @@ Bindings for fan connected to GPIO lines
 Required properties:
 - compatible : "gpio-fan"
+Optional properties:
 - gpios: Specifies the pins that map to bits in the control value,
  ordered MSB-->LSB.
 - gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
  control value that should be set to achieve them. This array
  must have the RPM values in ascending order.
-Optional properties:
 - alarm-gpios: This pin going active indicates something is wrong with
  the fan, and a udev event will be fired.
+- cooling-cells: If used as a cooling device, must be <2>
+  Also see: Documentation/devicetree/bindings/thermal/thermal.txt
+  min and max states are derived from the speed-map of the fan.
+Note: At least one the "gpios" or "alarm-gpios" properties must be set.
 Examples:
@@ -23,3 +28,13 @@ Examples:
                                      6000 2>;
                alarm-gpios = <&gpio1 15 1>;
        };
+        gpio_fan_cool: gpio_fan {
+                compatible = "gpio-fan";
+                gpios = <&gpio2 14 1
+                         &gpio2 13 1>;
+                gpio-fan,speed-map =    <0    0>,
+                                        <3000 1>,
+                                        <6000 2>;
+                alarm-gpios = <&gpio2 15 1>;
+                #cooling-cells = <2>; /* min followed by max */
+        };
diff --git a/Documentation/devicetree/bindings/i2c/i2c-imx.txt b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
index 52d37fd8d3e5..ce4311d726ae 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-imx.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-imx.txt
@@ -7,6 +7,7 @@ Required properties:
  - "fsl,vf610-i2c" for I2C compatible with the one integrated on Vybrid vf610 SoC
 - reg : Should contain I2C/HS-I2C registers location and length
 - interrupts : Should contain I2C/HS-I2C interrupt
+- clocks : Should contain the I2C/HS-I2C clock specifier
 Optional properties:
 - clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
diff --git a/Documentation/devicetree/bindings/iio/adc/da9150-gpadc.txt b/Documentation/devicetree/bindings/iio/adc/da9150-gpadc.txt
new file mode 100644
index 000000000000..c07228da92ac
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/da9150-gpadc.txt
@@ -0,0 +1,16 @@
+Dialog Semiconductor DA9150 IIO GPADC bindings
+Required properties:
+- compatible: "dlg,da9150-gpadc" for DA9150 IIO GPADC
+- #io-channel-cells: Should be set to <1>
+  (See Documentation/devicetree/bindings/iio/iio-bindings.txt for further info)
+For further information on GPADC channels, see device datasheet.
+Example:
+        gpadc: da9150-gpadc {
+                compatible = "dlg,da9150-gpadc";
+                #io-channel-cells = <1>;
+        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
new file mode 100644
index 000000000000..1099fe0788fa
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra-ictlr.txt
@@ -0,0 +1,43 @@
+NVIDIA Legacy Interrupt Controller
+All Tegra SoCs contain a legacy interrupt controller that routes
+interrupts to the GIC, and also serves as a wakeup source. It is also
+referred to as "ictlr", hence the name of the binding.
+The HW block exposes a number of interrupt controllers, each
+implementing a set of 32 interrupts.
+Required properties:
+- compatible : should be: "nvidia,tegra<chip>-ictlr". The LIC on
+  subsequent SoCs remained backwards-compatible with Tegra30, so on
+  Tegra generations later than Tegra30 the compatible value should
+  include "nvidia,tegra30-ictlr".       
+- reg : Specifies base physical address and size of the registers.
+  Each controller must be described separately (Tegra20 has 4 of them,
+  whereas Tegra30 and later have 5"  
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+Notes:
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the ictlr as an interrupt parent. SGIs and PPIs
+  are explicitly forbidden.
+Example:
+        ictlr: interrupt-controller@60004000 {
+                compatible = "nvidia,tegra20-ictlr", "nvidia,tegra-ictlr";
+                reg = <0x60004000 64>,
+                      <0x60004100 64>,
+                      <0x60004200 64>,
+                      <0x60004300 64>;
+                interrupt-controller;
+                #interrupt-cells = <3>;
+                interrupt-parent = <&intc>;
+        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
index 1a88e62228e5..63633bdea7e4 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,irqc.txt
@@ -4,7 +4,7 @@ Required properties:
 - compatible: has to be "renesas,irqc-<soctype>", "renesas,irqc" as fallback.
  Examples with soctypes are:
-    - "renesas,irqc-r8a73a4" (R-Mobile AP6)
+    - "renesas,irqc-r8a73a4" (R-Mobile APE6)
    - "renesas,irqc-r8a7790" (R-Car H2)
    - "renesas,irqc-r8a7791" (R-Car M2-W)
    - "renesas,irqc-r8a7792" (R-Car V2H)
@@ -12,6 +12,7 @@ Required properties:
    - "renesas,irqc-r8a7794" (R-Car E2)
 - #interrupt-cells: has to be <2>: an interrupt index and flags, as defined in
  interrupts.txt in this directory
+- clocks: Must contain a reference to the functional clock.
 Optional properties:
@@ -29,4 +30,5 @@ Example:
                             <0 1 IRQ_TYPE_LEVEL_HIGH>,
                             <0 2 IRQ_TYPE_LEVEL_HIGH>,
                             <0 3 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
        };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
new file mode 100644
index 000000000000..ced6014061a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
@@ -0,0 +1,35 @@
+STMicroelectronics STi System Configuration Controlled IRQs
+-----------------------------------------------------------
+On STi based systems; External, CTI (Core Sight), PMU (Performance Management),
+and PL310 L2 Cache IRQs are controlled using System Configuration registers.
+This driver is used to unmask them prior to use.
+Required properties:
+- compatible    : Should be set to one of:
+                        "st,stih415-irq-syscfg"
+                        "st,stih416-irq-syscfg"
+                        "st,stih407-irq-syscfg"
+                        "st,stid127-irq-syscfg"
+- st,syscfg     : Phandle to Cortex-A9 IRQ system config registers
+- st,irq-device : Array of IRQs to enable - should be 2 in length
+- st,fiq-device : Array of FIQs to enable - should be 2 in length
+Optional properties:
+- st,invert-ext : External IRQs can be inverted at will.  This property inverts
+                  these IRQs using bitwise logic.  A number of defines have been
+                  provided for convenience:
+                        ST_IRQ_SYSCFG_EXT_1_INV
+                        ST_IRQ_SYSCFG_EXT_2_INV
+                        ST_IRQ_SYSCFG_EXT_3_INV
+Example:
+irq-syscfg {
+        compatible    = "st,stih416-irq-syscfg";
+        st,syscfg     = <&syscfg_cpu>;
+        st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
+                        <ST_IRQ_SYSCFG_PMU_1>;
+        st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
+                        <ST_IRQ_SYSCFG_DISABLED>;
+        st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>;
+};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
new file mode 100644
index 000000000000..43effa0a4fe7
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/ti,omap4-wugen-mpu
@@ -0,0 +1,33 @@
+TI OMAP4 Wake-up Generator
+All TI OMAP4/5 (and their derivatives) an interrupt controller that
+routes interrupts to the GIC, and also serves as a wakeup source. It
+is also referred to as "WUGEN-MPU", hence the name of the binding.
+Reguired properties:
+- compatible : should contain at least "ti,omap4-wugen-mpu" or
+  "ti,omap5-wugen-mpu"
+- reg : Specifies base physical address and size of the registers.
+- interrupt-controller : Identifies the node as an interrupt controller.
+- #interrupt-cells : Specifies the number of cells needed to encode an
+  interrupt source. The value must be 3.
+- interrupt-parent : a phandle to the GIC these interrupts are routed
+  to.
+Notes:
+- Because this HW ultimately routes interrupts to the GIC, the
+  interrupt specifier must be that of the GIC.
+- Only SPIs can use the WUGEN as an interrupt parent. SGIs and PPIs
+  are explicitly forbiden.
+Example:
+       wakeupgen: interrupt-controller@48281000 {
+               compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
+               interrupt-controller;
+               #interrupt-cells = <3>;
+               reg = <0x48281000 0x1000>;
+               interrupt-parent = <&gic>;
+       };
diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
new file mode 100644
index 000000000000..72cc9cc95880
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-iproc.txt
@@ -0,0 +1,23 @@
+Broadcom IPROC SDHCI controller
+This file documents differences between the core properties described
+by mmc.txt and the properties that represent the IPROC SDHCI controller.
+Required properties:
+- compatible : Should be "brcm,sdhci-iproc-cygnus".
+- clocks : The clock feeding the SDHCI controller.
+Optional properties:
+  - sdhci,auto-cmd12: specifies that controller should use auto CMD12.
+Example:
+sdhci0: sdhci@0x18041000 {
+        compatible = "brcm,sdhci-iproc-cygnus";
+        reg = <0x18041000 0x100>;
+        interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&lcpll0_clks BCM_CYGNUS_LCPLL0_SDIO_CLK>;
+        bus-width = <4>;
+        sdhci,auto-cmd12;
+        no-1-8-v;
+};
diff --git a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
index ee4fc0576c7d..aad98442788b 100644
--- a/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/exynos-dw-mshc.txt
@@ -36,6 +36,8 @@ Required Properties:
  in transmit mode and CIU clock phase shift value in receive mode for double
  data rate mode operation. Refer notes below for the order of the cells and the
  valid values.
+* samsung,dw-mshc-hs400-timing: Specifies the value of CIU TX and RX clock phase
+  shift value for hs400 mode operation.
  Notes for the sdr-timing and ddr-timing values:
@@ -50,6 +52,9 @@ Required Properties:
      - if CIU clock divider value is 0 (that is divide by 1), both tx and rx
        phase shift clocks should be 0.
+* samsung,read-strobe-delay: RCLK (Data strobe) delay to control HS400 mode
+  (Latency value for delay line in Read path)
 Required properties for a slot (Deprecated - Recommend to use one slot per host):
 * gpios: specifies a list of gpios used for command, clock and data bus. The
@@ -82,5 +87,7 @@ Example:
                samsung,dw-mshc-ciu-div = <3>;
                samsung,dw-mshc-sdr-timing = <2 3>;
                samsung,dw-mshc-ddr-timing = <1 2>;
+                samsung,dw-mshc-hs400-timing = <0 2>;
+                samsung,read-strobe-delay = <90>;
                bus-width = <8>;
        };
diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
index 9046ba06c47a..415c5575cbf7 100644
--- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
+++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.txt
@@ -17,6 +17,10 @@ Optional properties:
  to select a proper data sampling window in case the clock quality is not good
  due to signal path is too long on the board. Please refer to eSDHC/uSDHC
  chapter, DLL (Delay Line) section in RM for details.
+- voltage-ranges : Specify the voltage range in case there are software
+  transparent level shifters on the outputs of the controller. Two cells are
+  required, first cell specifies minimum slot voltage (mV), second cell
+  specifies maximum slot voltage (mV). Several ranges could be specified.
 Examples:
diff --git a/Documentation/devicetree/bindings/mmc/mmc-card.txt b/Documentation/devicetree/bindings/mmc/mmc-card.txt
new file mode 100644
index 000000000000..a70fcd65b9ea
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mmc-card.txt
@@ -0,0 +1,31 @@
+mmc-card / eMMC bindings
+------------------------
+This documents describes the devicetree bindings for a mmc-host controller
+child node describing a mmc-card / an eMMC, see "Use of Function subnodes"
+in mmc.txt
+Required properties:
+-compatible : Must be "mmc-card"
+-reg        : Must be <0>
+Optional properties:
+-broken-hpi : Use this to indicate that the mmc-card has a broken hpi
+              implementation, and that hpi should not be used
+Example:
+&mmc2 {
+        pinctrl-names = "default";
+        pinctrl-0 = <&mmc2_pins_a>;
+        vmmc-supply = <&reg_vcc3v3>;
+        bus-width = <8>;
+        non-removable;
+        status = "okay";
+        mmccard: mmccard@0 {
+                reg = <0>;
+                compatible = "mmc-card";
+                broken-hpi;
+        };
+};
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-st.txt b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
index 7527db447a35..18d950df2749 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-st.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-st.txt
@@ -5,20 +5,62 @@ Documentation/devicetree/bindings/mmc/mmc.txt and the properties
 used by the sdhci-st driver.
 Required properties:
- compatible :  Must be "st,sdhci"
+- compatible:           Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
- clock-names : Should be "mmc"
+                        to set the internal glue logic used for configuring the MMC
-                See: Documentation/devicetree/bindings/resource-names.txt
+                        subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
- clocks :      Phandle of the clock used by the sdhci controler
+                        family).
-                See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- clock-names:          Should be "mmc".
+                        See: Documentation/devicetree/bindings/resource-names.txt
+- clocks:               Phandle to the clock.
+                        See: Documentation/devicetree/bindings/clock/clock-bindings.txt
+- interrupts:           One mmc interrupt should be described here.
+- interrupt-names:      Should be "mmcirq".
+- pinctrl-names:        A pinctrl state names "default" must be defined.
+- pinctrl-0:            Phandle referencing pin configuration of the sd/emmc controller.
+                        See: Documentation/devicetree/bindings/pinctrl/pinctrl-binding.txt
+- reg:                  This must provide the host controller base address and it can also
+                        contain the FlashSS Top register for TX/RX delay used by the driver
+                        to configure DLL inside the flashSS, if so reg-names must also be
+                        specified.
 Optional properties:
- non-removable: non-removable slot
+- reg-names:            Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
+                        for eMMC on stih407 family silicon to configure DLL inside FlashSS.
- bus-width: Number of data lines
-                 See: Documentation/devicetree/bindings/mmc/mmc.txt
+- non-removable:        Non-removable slot. Also used for configuring mmcss in STiH407 SoC
+                        family.
+                        See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+- bus-width:            Number of data lines.
+                        See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+- max-frequency:        Can be 200MHz, 100Mz or 50MHz (default) and used for
+                        configuring the CCONFIG3 in the mmcss.
+                        See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+- resets:               Phandle and reset specifier pair to softreset line of HC IP.
+                        See: Documentation/devicetree/bindings/reset/reset.txt
+- vqmmc-supply:         Phandle to the regulator dt node, mentioned as the vcc/vdd
+                        supply in eMMC/SD specs.
+- sd-uhs--sdr50:        To enable the SDR50 in the mmcss.
+                        See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+- sd-uhs-sdr104:        To enable the SDR104 in the mmcss.
+                        See:  Documentation/devicetree/bindings/mmc/mmc.txt.
+- sd-uhs-ddr50:         To enable the DDR50 in the mmcss.
+                        See:  Documentation/devicetree/bindings/mmc/mmc.txt.
 Example:
+/* Example stih416e eMMC configuration */
 mmc0: sdhci@fe81e000 {
        compatible      = "st,sdhci";
        status          = "disabled";
@@ -29,5 +71,43 @@ mmc0: sdhci@fe81e000 {
        pinctrl-0       = <&pinctrl_mmc0>;
        clock-names     = "mmc";
        clocks          = <&clk_s_a1_ls 1>;
-        bus-width       = <8>
+        bus-width       = <8>
+/* Example SD stih407 family configuration */
+mmc1: sdhci@09080000 {
+        compatible      = "st,sdhci-stih407", "st,sdhci";
+        status          = "disabled";
+        reg             = <0x09080000 0x7ff>;
+        reg-names       = "mmc";
+        interrupts      = <GIC_SPI 90 IRQ_TYPE_NONE>;
+        interrupt-names = "mmcirq";
+        pinctrl-names   = "default";
+        pinctrl-0       = <&pinctrl_sd1>;
+        clock-names     = "mmc";
+        clocks          = <&clk_s_c0_flexgen CLK_MMC_1>;
+        resets          = <&softreset STIH407_MMC1_SOFTRESET>;
+        bus-width       = <4>;
+};
+/* Example eMMC stih407 family configuration */
+mmc0: sdhci@09060000 {
+        compatible      = "st,sdhci-stih407", "st,sdhci";
+        status          = "disabled";
+        reg             = <0x09060000 0x7ff>, <0x9061008 0x20>;
+        reg-names       = "mmc", "top-mmc-delay";
+        interrupts      = <GIC_SPI 92 IRQ_TYPE_NONE>;
+        interrupt-names = "mmcirq";
+        pinctrl-names   = "default";
+        pinctrl-0       = <&pinctrl_mmc0>;
+        clock-names     = "mmc";
+        clocks          = <&clk_s_c0_flexgen CLK_MMC_0>;
+        vqmmc-supply    = <&vmmc_reg>;
+        max-frequency   = <200000000>;
+        bus-width       = <8>;
+        non-removable;
+        sd-uhs-sdr50;
+        sd-uhs-sdr104;
+        sd-uhs-ddr50;
 };
diff --git a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt b/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt
index 33df3932168e..8db32384a486 100644
--- a/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt
+++ b/Documentation/devicetree/bindings/net/amd-xgbe-phy.txt
@@ -27,6 +27,8 @@ property is used.
 - amd,serdes-cdr-rate: CDR rate speed selection
 - amd,serdes-pq-skew: PQ (data sampling) skew
 - amd,serdes-tx-amp: TX amplitude boost
+- amd,serdes-dfe-tap-config: DFE taps available to run
+- amd,serdes-dfe-tap-enable: DFE taps to enable
 Example:
        xgbe_phy@e1240800 {
@@ -41,4 +43,6 @@ Example:
                amd,serdes-cdr-rate = <2>, <2>, <7>;
                amd,serdes-pq-skew = <10>, <10>, <30>;
                amd,serdes-tx-amp = <15>, <15>, <10>;
+                amd,serdes-dfe-tap-config = <3>, <3>, <1>;
+                amd,serdes-dfe-tap-enable = <0>, <0>, <127>;
        };
diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
index cfcc52705ed8..6151999c5dca 100644
--- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
+++ b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt
@@ -4,7 +4,10 @@ Ethernet nodes are defined to describe on-chip ethernet interfaces in
 APM X-Gene SoC.
 Required properties for all the ethernet interfaces:
- compatible: Should be "apm,xgene-enet"
+- compatible: Should state binding information from the following list,
+  - "apm,xgene-enet":    RGMII based 1G interface
+  - "apm,xgene1-sgenet": SGMII based 1G interface
+  - "apm,xgene1-xgenet": XFI based 10G interface
 - reg: Address and length of the register set for the device. It contains the
  information of registers in the same order as described by reg-names
 - reg-names: Should contain the register set names
diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt
index e124847443f8..f0b4cd72411d 100644
--- a/Documentation/devicetree/bindings/net/dsa/dsa.txt
+++ b/Documentation/devicetree/bindings/net/dsa/dsa.txt
@@ -19,7 +19,9 @@ the parent DSA node. The maximum number of allowed child nodes is 4
 (DSA_MAX_SWITCHES).
 Each of these switch child nodes should have the following required properties:
- reg                   : Describes the switch address on the MII bus
+- reg                   : Contains two fields. The first one describes the
+                          address on the MII bus. The second is the switch
+                          number that must be unique in cascaded configurations
 - #address-cells        : Must be 1
 - #size-cells           : Must be 0
diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
new file mode 100644
index 000000000000..f7ce50e38ed4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.txt
@@ -0,0 +1,63 @@
+* Broadcom iProc PCIe controller with the platform bus interface
+Required properties:
+- compatible: Must be "brcm,iproc-pcie"
+- reg: base address and length of the PCIe controller I/O register space
+- #interrupt-cells: set to <1>
+- interrupt-map-mask and interrupt-map, standard PCI properties to define the
+  mapping of the PCIe interface to interrupt numbers
+- linux,pci-domain: PCI domain ID. Should be unique for each host controller
+- bus-range: PCI bus numbers covered
+- #address-cells: set to <3>
+- #size-cells: set to <2>
+- device_type: set to "pci"
+- ranges: ranges for the PCI memory and I/O regions
+Optional properties:
+- phys: phandle of the PCIe PHY device
+- phy-names: must be "pcie-phy"
+Example:
+        pcie0: pcie@18012000 {
+                compatible = "brcm,iproc-pcie";
+                reg = <0x18012000 0x1000>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
+                linux,pci-domain = <0>;
+                bus-range = <0x00 0xff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x81000000 0 0          0x28000000 0 0x00010000
+                          0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
+                phys = <&phy 0 5>;
+                phy-names = "pcie-phy";
+        };
+        pcie1: pcie@18013000 {
+                compatible = "brcm,iproc-pcie";
+                reg = <0x18013000 0x1000>;
+                #interrupt-cells = <1>;
+                interrupt-map-mask = <0 0 0 0>;
+                interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
+                linux,pci-domain = <1>;
+                bus-range = <0x00 0xff>;
+                #address-cells = <3>;
+                #size-cells = <2>;
+                device_type = "pci";
+                ranges = <0x81000000 0 0          0x48000000 0 0x00010000
+                          0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
+                phys = <&phy 1 6>;
+                phy-names = "pcie-phy";
+        };
diff --git a/Documentation/devicetree/bindings/power/da9150-charger.txt b/Documentation/devicetree/bindings/power/da9150-charger.txt
new file mode 100644
index 000000000000..f3906663c454
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/da9150-charger.txt
@@ -0,0 +1,26 @@
+Dialog Semiconductor DA9150 Charger Power Supply bindings
+Required properties:
+- compatible: "dlg,da9150-charger" for DA9150 Charger Power Supply
+Optional properties:
+- io-channels: List of phandle and IIO specifier pairs
+- io-channel-names: List of channel names used by charger
+      ["CHAN_IBUS", "CHAN_VBUS", "CHAN_TJUNC", "CHAN_VBAT"]
+  (See Documentation/devicetree/bindings/iio/iio-bindings.txt for further info)
+Example:
+        da9150-charger {
+                compatible = "dlg,da9150-charger";
+                io-channels = <&gpadc 0>,
+                              <&gpadc 2>,
+                              <&gpadc 8>,
+                              <&gpadc 5>;
+                io-channel-names = "CHAN_IBUS",
+                                   "CHAN_VBUS",
+                                   "CHAN_TJUNC",
+                                   "CHAN_VBAT";
+        };
diff --git a/Documentation/devicetree/bindings/power/power_domain.txt b/Documentation/devicetree/bindings/power/power_domain.txt
index 98c16672ab5f..0f8ed3710c66 100644
--- a/Documentation/devicetree/bindings/power/power_domain.txt
+++ b/Documentation/devicetree/bindings/power/power_domain.txt
@@ -19,6 +19,16 @@ Required properties:
   providing multiple PM domains (e.g. power controllers), but can be any value
   as specified by device tree binding documentation of particular provider.
+Optional properties:
+ - power-domains : A phandle and PM domain specifier as defined by bindings of
+                   the power controller specified by phandle.
+   Some power domains might be powered from another power domain (or have
+   other hardware specific dependencies). For representing such dependency
+   a standard PM domain consumer binding is used. When provided, all domains
+   created by the given provider should be subdomains of the domain
+   specified by this binding. More details about power domain specifier are
+   available in the next section.
 Example:
        power: power-controller@12340000 {
@@ -30,6 +40,25 @@ Example:
 The node above defines a power controller that is a PM domain provider and
 expects one cell as its phandle argument.
+Example 2:
+        parent: power-controller@12340000 {
+                compatible = "foo,power-controller";
+                reg = <0x12340000 0x1000>;
+                #power-domain-cells = <1>;
+        };
+        child: power-controller@12340000 {
+                compatible = "foo,power-controller";
+                reg = <0x12341000 0x1000>;
+                power-domains = <&parent 0>;
+                #power-domain-cells = <1>;
+        };
+The nodes above define two power controllers: 'parent' and 'child'.
+Domains created by the 'child' power controller are subdomains of '0' power
+domain provided by the 'parent' power controller.
 ==PM domain consumers==
 Required properties:
diff --git a/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt
new file mode 100644
index 000000000000..1e2546f8b08a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/syscon-poweroff.txt
@@ -0,0 +1,23 @@
+Generic SYSCON mapped register poweroff driver
+This is a generic poweroff driver using syscon to map the poweroff register.
+The poweroff is generally performed with a write to the poweroff register
+defined by the register map pointed by syscon reference plus the offset
+with the mask defined in the poweroff node.
+Required properties:
+- compatible: should contain "syscon-poweroff"
+- regmap: this is phandle to the register map node
+- offset: offset in the register map for the poweroff register (in bytes)
+- mask: the poweroff value written to the poweroff register (32 bit access)
+Default will be little endian mode, 32 bit access only.
+Examples:
+        poweroff {
+           compatible = "syscon-poweroff";
+           regmap = <&regmapnode>;
+           offset = <0x0>;
+           mask = <0x7a>;
+        };
diff --git a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt
index dad6358074ac..e91485d11241 100644
--- a/Documentation/devicetree/bindings/regulator/act8865-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/act8865-regulator.txt
@@ -2,13 +2,35 @@ ACT88xx regulators
 -------------------
 Required properties:
- compatible: "active-semi,act8846" or "active-semi,act8865"
+- compatible: "active-semi,act8846" or "active-semi,act8865" or "active-semi,act8600"
 - reg: I2C slave address
 Optional properties:
 - system-power-controller: Telling whether or not this pmic is controlling
  the system power. See Documentation/devicetree/bindings/power/power-controller.txt .
+Optional input supply properties:
+- for act8600:
+  - vp1-supply: The input supply for DCDC_REG1
+  - vp2-supply: The input supply for DCDC_REG2
+  - vp3-supply: The input supply for DCDC_REG3
+  - inl-supply: The input supply for LDO_REG5, LDO_REG6, LDO_REG7 and LDO_REG8
+  SUDCDC_REG4, LDO_REG9 and LDO_REG10 do not have separate supplies.
+- for act8846:
+  - vp1-supply: The input supply for REG1
+  - vp2-supply: The input supply for REG2
+  - vp3-supply: The input supply for REG3
+  - vp4-supply: The input supply for REG4
+  - inl1-supply: The input supply for REG5, REG6 and REG7
+  - inl2-supply: The input supply for REG8 and LDO_REG9
+  - inl3-supply: The input supply for REG10, REG11 and REG12
+- for act8865:
+  - vp1-supply: The input supply for DCDC_REG1
+  - vp2-supply: The input supply for DCDC_REG2
+  - vp3-supply: The input supply for DCDC_REG3
+  - inl45-supply: The input supply for LDO_REG1 and LDO_REG2
+  - inl67-supply: The input supply for LDO_REG3 and LDO_REG4
 Any standard regulator properties can be used to configure the single regulator.
 The valid names for regulators are:
@@ -16,6 +38,9 @@ The valid names for regulators are:
        REG1, REG2, REG3, REG4, REG5, REG6, REG7, REG8, REG9, REG10, REG11, REG12
        - for act8865:
        DCDC_REG1, DCDC_REG2, DCDC_REG3, LDO_REG1, LDO_REG2, LDO_REG3, LDO_REG4.
+        - for act8600:
+        DCDC_REG1, DCDC_REG2, DCDC_REG3, SUDCDC_REG4, LDO_REG5, LDO_REG6, LDO_REG7,
+        LDO_REG8, LDO_REG9, LDO_REG10,
 Example:
 --------
diff --git a/Documentation/devicetree/bindings/serial/of-serial.txt b/Documentation/devicetree/bindings/serial/8250.txt
index 91d5ab0e60fc..91d5ab0e60fc 100644
--- a/Documentation/devicetree/bindings/serial/of-serial.txt
+++ b/Documentation/devicetree/bindings/serial/8250.txt
diff --git a/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt b/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt
new file mode 100644
index 000000000000..ebcbb62c0a76
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/axis,etraxfs-uart.txt
@@ -0,0 +1,19 @@
+ETRAX FS UART
+Required properties:
+- compatible : "axis,etraxfs-uart"
+- reg: offset and length of the register set for the device.
+- interrupts: device interrupt
+Optional properties:
+- {dtr,dsr,ri,cd}-gpios: specify a GPIO for DTR/DSR/RI/CD
+  line respectively.
+Example:
+serial@b00260000 {
+        compatible = "axis,etraxfs-uart";
+        reg = <0xb0026000 0x1000>;
+        interrupts = <68>;
+        status = "disabled";
+};
diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
index 7f76214f728a..289c40ed7470 100644
--- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
+++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.txt
@@ -21,6 +21,18 @@ Optional properties:
 - reg-io-width : the size (in bytes) of the IO accesses that should be
  performed on the device.  If this property is not present then single byte
  accesses are used.
+- dcd-override : Override the DCD modem status signal. This signal will always
+  be reported as active instead of being obtained from the modem status
+  register. Define this if your serial port does not use this pin.
+- dsr-override : Override the DTS modem status signal. This signal will always
+  be reported as active instead of being obtained from the modem status
+  register. Define this if your serial port does not use this pin.
+- cts-override : Override the CTS modem status signal. This signal will always
+  be reported as active instead of being obtained from the modem status
+  register. Define this if your serial port does not use this pin.
+- ri-override : Override the RI modem status signal. This signal will always be
+  reported as inactive instead of being obtained from the modem status register.
+  Define this if your serial port does not use this pin.
 Example:
@@ -31,6 +43,10 @@ Example:
                interrupts = <10>;
                reg-shift = <2>;
                reg-io-width = <4>;
+                dcd-override;
+                dsr-override;
+                cts-override;
+                ri-override;
        };
 Example with one clock:
diff --git a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
index aad527b357a0..523341a0e113 100644
--- a/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
+++ b/Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt
@@ -2,11 +2,21 @@
  (CSPI/eCSPI) for i.MX
 Required properties:
- compatible : Should be "fsl,<soc>-cspi" or "fsl,<soc>-ecspi"
+- compatible :
+  - "fsl,imx1-cspi" for SPI compatible with the one integrated on i.MX1
+  - "fsl,imx21-cspi" for SPI compatible with the one integrated on i.MX21
+  - "fsl,imx27-cspi" for SPI compatible with the one integrated on i.MX27
+  - "fsl,imx31-cspi" for SPI compatible with the one integrated on i.MX31
+  - "fsl,imx35-cspi" for SPI compatible with the one integrated on i.MX35
+  - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51
 - reg : Offset and length of the register set for the device
 - interrupts : Should contain CSPI/eCSPI interrupt
 - fsl,spi-num-chipselects : Contains the number of the chipselect
 - cs-gpios : Specifies the gpio pins to be used for chipselects.
+- clocks : Clock specifiers for both ipg and per clocks.
+- clock-names : Clock names should include both "ipg" and "per"
+See the clock consumer binding,
+        Documentation/devicetree/bindings/clock/clock-bindings.txt
 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
                Documentation/devicetree/bindings/dma/dma.txt
 - dma-names: DMA request names should include "tx" and "rx" if present.
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
index e2c88df2cc15..5c090771c016 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
@@ -33,6 +33,11 @@ Optional properties:
                nodes.  If unspecified, a single SPI device without a chip
                select can be used.
+- dmas:         Two DMA channel specifiers following the convention outlined
+                in bindings/dma/dma.txt
+- dma-names:    Names for the dma channels, if present. There must be at
+                least one channel named "tx" for transmit and named "rx" for
+                receive.
 SPI slave nodes must be children of the SPI master node and can contain
 properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
@@ -51,6 +56,9 @@ Example:
                clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
                clock-names = "core", "iface";
+                dmas = <&blsp1_bam 13>, <&blsp1_bam 12>;
+                dma-names = "rx", "tx";
                pinctrl-names = "default";
                pinctrl-0 = <&spi8_default>;
diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
index cbbe16ed3874..70af78a9185e 100644
--- a/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt
@@ -16,6 +16,12 @@ Optional property:
  in big endian mode, otherwise in native mode(same with CPU), for more
  detail please see: Documentation/devicetree/bindings/regmap/regmap.txt.
+Optional SPI slave node properties:
+- fsl,spi-cs-sck-delay: a delay in nanoseconds between activating chip
+  select and the start of clock signal, at the start of a transfer.
+- fsl,spi-sck-cs-delay: a delay in nanoseconds between stopping the clock
+  signal and deactivating chip select, at the end of a transfer.
 Example:
 dspi0@4002c000 {
@@ -43,6 +49,8 @@ dspi0@4002c000 {
                reg = <0>;
                linux,modalias = "m25p80";
                modal = "at26df081a";
+                fsl,spi-cs-sck-delay = <100>;
+                fsl,spi-sck-cs-delay = <50>;
        };
 };
diff --git a/Documentation/devicetree/bindings/spi/spi-img-spfi.txt b/Documentation/devicetree/bindings/spi/spi-img-spfi.txt
index c7dd50fb8eb2..e02fbf18c82c 100644
--- a/Documentation/devicetree/bindings/spi/spi-img-spfi.txt
+++ b/Documentation/devicetree/bindings/spi/spi-img-spfi.txt
@@ -14,6 +14,7 @@ Required properties:
 - dma-names: Must include the following entries:
  - rx
  - tx
+- cs-gpios: Must specify the GPIOs used for chipselect lines.
 - #address-cells: Must be 1.
 - #size-cells: Must be 0.
diff --git a/Documentation/devicetree/bindings/spi/spi-rockchip.txt b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
index 467dec441c62..0c491bda4c65 100644
--- a/Documentation/devicetree/bindings/spi/spi-rockchip.txt
+++ b/Documentation/devicetree/bindings/spi/spi-rockchip.txt
@@ -24,6 +24,9 @@ Optional Properties:
 - dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
                Documentation/devicetree/bindings/dma/dma.txt
 - dma-names: DMA request names should include "tx" and "rx" if present.
+- rx-sample-delay-ns: nanoseconds to delay after the SCLK edge before sampling
+                Rx data (may need to be fine tuned for high capacitance lines).
+                No delay (0) by default.
 Example:
@@ -33,6 +36,7 @@ Example:
                reg = <0xff110000 0x1000>;
                dmas = <&pdma1 11>, <&pdma1 12>;
                dma-names = "tx", "rx";
+                rx-sample-delay-ns = <10>;
                #address-cells = <1>;
                #size-cells = <0>;
                interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
diff --git a/Documentation/devicetree/bindings/submitting-patches.txt b/Documentation/devicetree/bindings/submitting-patches.txt
index 56742bc70218..7d44eae7ab0b 100644
--- a/Documentation/devicetree/bindings/submitting-patches.txt
+++ b/Documentation/devicetree/bindings/submitting-patches.txt
@@ -12,6 +12,9 @@ I. For patch submitters
       devicetree@vger.kernel.org
+     and Cc: the DT maintainers. Use scripts/get_maintainer.pl to identify
+     all of the DT maintainers.
  3) The Documentation/ portion of the patch should come in the series before
     the code implementing the binding.
diff --git a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
index 43404b197933..332e625f6ed0 100644
--- a/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/rcar-thermal.txt
@@ -4,7 +4,7 @@ Required properties:
 - compatible            : "renesas,thermal-<soctype>", "renesas,rcar-thermal"
                          as fallback.
                          Examples with soctypes are:
-                            - "renesas,thermal-r8a73a4" (R-Mobile AP6)
+                            - "renesas,thermal-r8a73a4" (R-Mobile APE6)
                            - "renesas,thermal-r8a7779" (R-Car H1)
                            - "renesas,thermal-r8a7790" (R-Car H2)
                            - "renesas,thermal-r8a7791" (R-Car M2-W)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 389ca1347a77..fae26d014aaf 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -20,6 +20,7 @@ amlogic	Amlogic, Inc.
 ams     AMS AG
 amstaos AMS-Taos Inc.
 apm     Applied Micro Circuits Corporation (APM)
+arasan  Arasan Chip Systems
 arm     ARM Ltd.
 armadeus        ARMadeus Systems SARL
 asahi-kasei     Asahi Kasei Corp.
@@ -27,6 +28,7 @@ atmel	Atmel Corporation
 auo     AU Optronics Corporation
 avago   Avago Technologies
 avic    Shanghai AVIC Optoelectronics Co., Ltd.
+axis    Axis Communications AB
 bosch   Bosch Sensortec GmbH
 brcm    Broadcom Corporation
 buffalo Buffalo, Inc.
diff --git a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
index f90e294d7631..a4d869744f59 100644
--- a/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/atmel-wdt.txt
@@ -26,6 +26,11 @@ Optional properties:
 - atmel,disable : Should be present if you want to disable the watchdog.
 - atmel,idle-halt : Should be present if you want to stop the watchdog when
        entering idle state.
+        CAUTION: This property should be used with care, it actually makes the
+        watchdog not counting when the CPU is in idle state, therefore the
+        watchdog reset time depends on mean CPU usage and will not reset at all
+        if the CPU stop working while it is in idle state, which is probably
+        not what you want.
 - atmel,dbg-halt : Should be present if you want to stop the watchdog when
        entering debug state.