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-rw-r--r--drivers/gpu/drm/i915/i915_reg.h1
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c8
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c4
3 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b4bb1ef77ddc..9d24d65f0c3e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -568,6 +568,7 @@
568#define CM0_MASK_SHIFT 16 568#define CM0_MASK_SHIFT 16
569#define CM0_IZ_OPT_DISABLE (1<<6) 569#define CM0_IZ_OPT_DISABLE (1<<6)
570#define CM0_ZR_OPT_DISABLE (1<<5) 570#define CM0_ZR_OPT_DISABLE (1<<5)
571#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
571#define CM0_DEPTH_EVICT_DISABLE (1<<4) 572#define CM0_DEPTH_EVICT_DISABLE (1<<4)
572#define CM0_COLOR_EVICT_DISABLE (1<<3) 573#define CM0_COLOR_EVICT_DISABLE (1<<3)
573#define CM0_DEPTH_WRITE_DISABLE (1<<1) 574#define CM0_DEPTH_WRITE_DISABLE (1<<1)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index f75806e5bff5..80fce51e2f43 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -401,6 +401,14 @@ static int init_render_ring(struct intel_ring_buffer *ring)
401 if (INTEL_INFO(dev)->gen >= 6) { 401 if (INTEL_INFO(dev)->gen >= 6) {
402 I915_WRITE(INSTPM, 402 I915_WRITE(INSTPM,
403 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING); 403 INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
404
405 /* From the Sandybridge PRM, volume 1 part 3, page 24:
406 * "If this bit is set, STCunit will have LRA as replacement
407 * policy. [...] This bit must be reset. LRA replacement
408 * policy is not supported."
409 */
410 I915_WRITE(CACHE_MODE_0,
411 CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
404 } 412 }
405 413
406 return ret; 414 return ret;
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index c5c31e091a92..af1054f8202a 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -958,8 +958,8 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
958 break; 958 break;
959 } 959 }
960 960
961 if (radeon_encoder->active_device & 961 if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
962 (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) { 962 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
963 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; 963 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
964 struct drm_connector *connector = 964 struct drm_connector *connector =
965 radeon_get_connector_for_encoder(encoder); 965 radeon_get_connector_for_encoder(encoder);