diff options
-rw-r--r-- | arch/arm/boot/dts/zynq-7000.dtsi | 8 | ||||
-rw-r--r-- | arch/arm/mach-msm/timer.c | 1 | ||||
-rw-r--r-- | arch/arm/mach-zynq/Kconfig | 1 | ||||
-rw-r--r-- | drivers/clocksource/arm_arch_timer.c | 2 | ||||
-rw-r--r-- | drivers/clocksource/arm_global_timer.c | 3 | ||||
-rw-r--r-- | drivers/clocksource/bcm2835_timer.c | 4 | ||||
-rw-r--r-- | drivers/clocksource/clksrc-dbx500-prcmu.c | 5 | ||||
-rw-r--r-- | drivers/clocksource/clksrc-of.c | 1 | ||||
-rw-r--r-- | drivers/clocksource/dw_apb_timer_of.c | 16 | ||||
-rw-r--r-- | drivers/clocksource/mxs_timer.c | 4 | ||||
-rw-r--r-- | drivers/clocksource/nomadik-mtu.c | 4 | ||||
-rw-r--r-- | drivers/clocksource/samsung_pwm_timer.c | 4 | ||||
-rw-r--r-- | drivers/clocksource/tegra20_timer.c | 8 | ||||
-rw-r--r-- | drivers/clocksource/time-armada-370-xp.c | 4 | ||||
-rw-r--r-- | drivers/clocksource/timer-prima2.c | 6 | ||||
-rw-r--r-- | drivers/clocksource/vf_pit_timer.c | 4 | ||||
-rw-r--r-- | drivers/clocksource/vt8500_timer.c | 2 | ||||
-rw-r--r-- | include/linux/clockchips.h | 1 | ||||
-rw-r--r-- | kernel/time/tick-broadcast.c | 1 |
19 files changed, 41 insertions, 38 deletions
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index e32b92b949d2..e7f73b2e4550 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi | |||
@@ -92,6 +92,14 @@ | |||
92 | }; | 92 | }; |
93 | }; | 93 | }; |
94 | 94 | ||
95 | global_timer: timer@f8f00200 { | ||
96 | compatible = "arm,cortex-a9-global-timer"; | ||
97 | reg = <0xf8f00200 0x20>; | ||
98 | interrupts = <1 11 0x301>; | ||
99 | interrupt-parent = <&intc>; | ||
100 | clocks = <&clkc 4>; | ||
101 | }; | ||
102 | |||
95 | ttc0: ttc0@f8001000 { | 103 | ttc0: ttc0@f8001000 { |
96 | interrupt-parent = <&intc>; | 104 | interrupt-parent = <&intc>; |
97 | interrupts = < 0 10 4 0 11 4 0 12 4 >; | 105 | interrupts = < 0 10 4 0 11 4 0 12 4 >; |
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c index 696fb73296d0..1e9c3383daba 100644 --- a/arch/arm/mach-msm/timer.c +++ b/arch/arm/mach-msm/timer.c | |||
@@ -274,7 +274,6 @@ static void __init msm_dt_timer_init(struct device_node *np) | |||
274 | pr_err("Unknown frequency\n"); | 274 | pr_err("Unknown frequency\n"); |
275 | return; | 275 | return; |
276 | } | 276 | } |
277 | of_node_put(np); | ||
278 | 277 | ||
279 | event_base = base + 0x4; | 278 | event_base = base + 0x4; |
280 | sts_base = base + 0x88; | 279 | sts_base = base + 0x88; |
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 04f8a4a6e755..6b04260aa142 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig | |||
@@ -13,5 +13,6 @@ config ARCH_ZYNQ | |||
13 | select HAVE_SMP | 13 | select HAVE_SMP |
14 | select SPARSE_IRQ | 14 | select SPARSE_IRQ |
15 | select CADENCE_TTC_TIMER | 15 | select CADENCE_TTC_TIMER |
16 | select ARM_GLOBAL_TIMER | ||
16 | help | 17 | help |
17 | Support for Xilinx Zynq ARM Cortex A9 Platform | 18 | Support for Xilinx Zynq ARM Cortex A9 Platform |
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index fbd9ccd5e114..ce98d5e70927 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c | |||
@@ -389,7 +389,7 @@ static struct clocksource clocksource_counter = { | |||
389 | .rating = 400, | 389 | .rating = 400, |
390 | .read = arch_counter_read, | 390 | .read = arch_counter_read, |
391 | .mask = CLOCKSOURCE_MASK(56), | 391 | .mask = CLOCKSOURCE_MASK(56), |
392 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 392 | .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, |
393 | }; | 393 | }; |
394 | 394 | ||
395 | static struct cyclecounter cyclecounter = { | 395 | static struct cyclecounter cyclecounter = { |
diff --git a/drivers/clocksource/arm_global_timer.c b/drivers/clocksource/arm_global_timer.c index b66c1f36066c..c639b1a9e996 100644 --- a/drivers/clocksource/arm_global_timer.c +++ b/drivers/clocksource/arm_global_timer.c | |||
@@ -169,7 +169,8 @@ static int gt_clockevents_init(struct clock_event_device *clk) | |||
169 | int cpu = smp_processor_id(); | 169 | int cpu = smp_processor_id(); |
170 | 170 | ||
171 | clk->name = "arm_global_timer"; | 171 | clk->name = "arm_global_timer"; |
172 | clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; | 172 | clk->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT | |
173 | CLOCK_EVT_FEAT_PERCPU; | ||
173 | clk->set_mode = gt_clockevent_set_mode; | 174 | clk->set_mode = gt_clockevent_set_mode; |
174 | clk->set_next_event = gt_clockevent_set_next_event; | 175 | clk->set_next_event = gt_clockevent_set_next_event; |
175 | clk->cpumask = cpumask_of(cpu); | 176 | clk->cpumask = cpumask_of(cpu); |
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c index 07ea7ce900dc..26ed331b1aad 100644 --- a/drivers/clocksource/bcm2835_timer.c +++ b/drivers/clocksource/bcm2835_timer.c | |||
@@ -49,7 +49,7 @@ struct bcm2835_timer { | |||
49 | 49 | ||
50 | static void __iomem *system_clock __read_mostly; | 50 | static void __iomem *system_clock __read_mostly; |
51 | 51 | ||
52 | static u32 notrace bcm2835_sched_read(void) | 52 | static u64 notrace bcm2835_sched_read(void) |
53 | { | 53 | { |
54 | return readl_relaxed(system_clock); | 54 | return readl_relaxed(system_clock); |
55 | } | 55 | } |
@@ -110,7 +110,7 @@ static void __init bcm2835_timer_init(struct device_node *node) | |||
110 | panic("Can't read clock-frequency"); | 110 | panic("Can't read clock-frequency"); |
111 | 111 | ||
112 | system_clock = base + REG_COUNTER_LO; | 112 | system_clock = base + REG_COUNTER_LO; |
113 | setup_sched_clock(bcm2835_sched_read, 32, freq); | 113 | sched_clock_register(bcm2835_sched_read, 32, freq); |
114 | 114 | ||
115 | clocksource_mmio_init(base + REG_COUNTER_LO, node->name, | 115 | clocksource_mmio_init(base + REG_COUNTER_LO, node->name, |
116 | freq, 300, 32, clocksource_mmio_readl_up); | 116 | freq, 300, 32, clocksource_mmio_readl_up); |
diff --git a/drivers/clocksource/clksrc-dbx500-prcmu.c b/drivers/clocksource/clksrc-dbx500-prcmu.c index a9fd4ad25674..b375106844d8 100644 --- a/drivers/clocksource/clksrc-dbx500-prcmu.c +++ b/drivers/clocksource/clksrc-dbx500-prcmu.c | |||
@@ -53,7 +53,7 @@ static struct clocksource clocksource_dbx500_prcmu = { | |||
53 | 53 | ||
54 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | 54 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK |
55 | 55 | ||
56 | static u32 notrace dbx500_prcmu_sched_clock_read(void) | 56 | static u64 notrace dbx500_prcmu_sched_clock_read(void) |
57 | { | 57 | { |
58 | if (unlikely(!clksrc_dbx500_timer_base)) | 58 | if (unlikely(!clksrc_dbx500_timer_base)) |
59 | return 0; | 59 | return 0; |
@@ -81,8 +81,7 @@ void __init clksrc_dbx500_prcmu_init(void __iomem *base) | |||
81 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); | 81 | clksrc_dbx500_timer_base + PRCMU_TIMER_REF); |
82 | } | 82 | } |
83 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK | 83 | #ifdef CONFIG_CLKSRC_DBX500_PRCMU_SCHED_CLOCK |
84 | setup_sched_clock(dbx500_prcmu_sched_clock_read, | 84 | sched_clock_register(dbx500_prcmu_sched_clock_read, 32, RATE_32K); |
85 | 32, RATE_32K); | ||
86 | #endif | 85 | #endif |
87 | clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); | 86 | clocksource_register_hz(&clocksource_dbx500_prcmu, RATE_32K); |
88 | } | 87 | } |
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c index b9ddd9e3a2f5..35639cf4e5a2 100644 --- a/drivers/clocksource/clksrc-of.c +++ b/drivers/clocksource/clksrc-of.c | |||
@@ -35,5 +35,6 @@ void __init clocksource_of_init(void) | |||
35 | 35 | ||
36 | init_func = match->data; | 36 | init_func = match->data; |
37 | init_func(np); | 37 | init_func(np); |
38 | of_node_put(np); | ||
38 | } | 39 | } |
39 | } | 40 | } |
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c index 4cbae4f762b1..45ba8aecc729 100644 --- a/drivers/clocksource/dw_apb_timer_of.c +++ b/drivers/clocksource/dw_apb_timer_of.c | |||
@@ -23,7 +23,7 @@ | |||
23 | #include <linux/clk.h> | 23 | #include <linux/clk.h> |
24 | #include <linux/sched_clock.h> | 24 | #include <linux/sched_clock.h> |
25 | 25 | ||
26 | static void timer_get_base_and_rate(struct device_node *np, | 26 | static void __init timer_get_base_and_rate(struct device_node *np, |
27 | void __iomem **base, u32 *rate) | 27 | void __iomem **base, u32 *rate) |
28 | { | 28 | { |
29 | struct clk *timer_clk; | 29 | struct clk *timer_clk; |
@@ -55,11 +55,11 @@ static void timer_get_base_and_rate(struct device_node *np, | |||
55 | 55 | ||
56 | try_clock_freq: | 56 | try_clock_freq: |
57 | if (of_property_read_u32(np, "clock-freq", rate) && | 57 | if (of_property_read_u32(np, "clock-freq", rate) && |
58 | of_property_read_u32(np, "clock-frequency", rate)) | 58 | of_property_read_u32(np, "clock-frequency", rate)) |
59 | panic("No clock nor clock-frequency property for %s", np->name); | 59 | panic("No clock nor clock-frequency property for %s", np->name); |
60 | } | 60 | } |
61 | 61 | ||
62 | static void add_clockevent(struct device_node *event_timer) | 62 | static void __init add_clockevent(struct device_node *event_timer) |
63 | { | 63 | { |
64 | void __iomem *iobase; | 64 | void __iomem *iobase; |
65 | struct dw_apb_clock_event_device *ced; | 65 | struct dw_apb_clock_event_device *ced; |
@@ -82,7 +82,7 @@ static void add_clockevent(struct device_node *event_timer) | |||
82 | static void __iomem *sched_io_base; | 82 | static void __iomem *sched_io_base; |
83 | static u32 sched_rate; | 83 | static u32 sched_rate; |
84 | 84 | ||
85 | static void add_clocksource(struct device_node *source_timer) | 85 | static void __init add_clocksource(struct device_node *source_timer) |
86 | { | 86 | { |
87 | void __iomem *iobase; | 87 | void __iomem *iobase; |
88 | struct dw_apb_clocksource *cs; | 88 | struct dw_apb_clocksource *cs; |
@@ -106,7 +106,7 @@ static void add_clocksource(struct device_node *source_timer) | |||
106 | sched_rate = rate; | 106 | sched_rate = rate; |
107 | } | 107 | } |
108 | 108 | ||
109 | static u32 read_sched_clock(void) | 109 | static u64 read_sched_clock(void) |
110 | { | 110 | { |
111 | return __raw_readl(sched_io_base); | 111 | return __raw_readl(sched_io_base); |
112 | } | 112 | } |
@@ -117,7 +117,7 @@ static const struct of_device_id sptimer_ids[] __initconst = { | |||
117 | { /* Sentinel */ }, | 117 | { /* Sentinel */ }, |
118 | }; | 118 | }; |
119 | 119 | ||
120 | static void init_sched_clock(void) | 120 | static void __init init_sched_clock(void) |
121 | { | 121 | { |
122 | struct device_node *sched_timer; | 122 | struct device_node *sched_timer; |
123 | 123 | ||
@@ -128,7 +128,7 @@ static void init_sched_clock(void) | |||
128 | of_node_put(sched_timer); | 128 | of_node_put(sched_timer); |
129 | } | 129 | } |
130 | 130 | ||
131 | setup_sched_clock(read_sched_clock, 32, sched_rate); | 131 | sched_clock_register(read_sched_clock, 32, sched_rate); |
132 | } | 132 | } |
133 | 133 | ||
134 | static int num_called; | 134 | static int num_called; |
@@ -138,12 +138,10 @@ static void __init dw_apb_timer_init(struct device_node *timer) | |||
138 | case 0: | 138 | case 0: |
139 | pr_debug("%s: found clockevent timer\n", __func__); | 139 | pr_debug("%s: found clockevent timer\n", __func__); |
140 | add_clockevent(timer); | 140 | add_clockevent(timer); |
141 | of_node_put(timer); | ||
142 | break; | 141 | break; |
143 | case 1: | 142 | case 1: |
144 | pr_debug("%s: found clocksource timer\n", __func__); | 143 | pr_debug("%s: found clocksource timer\n", __func__); |
145 | add_clocksource(timer); | 144 | add_clocksource(timer); |
146 | of_node_put(timer); | ||
147 | init_sched_clock(); | 145 | init_sched_clock(); |
148 | break; | 146 | break; |
149 | default: | 147 | default: |
diff --git a/drivers/clocksource/mxs_timer.c b/drivers/clocksource/mxs_timer.c index 0f5e65f74dc3..445b68a01dc5 100644 --- a/drivers/clocksource/mxs_timer.c +++ b/drivers/clocksource/mxs_timer.c | |||
@@ -222,7 +222,7 @@ static struct clocksource clocksource_mxs = { | |||
222 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | 222 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
223 | }; | 223 | }; |
224 | 224 | ||
225 | static u32 notrace mxs_read_sched_clock_v2(void) | 225 | static u64 notrace mxs_read_sched_clock_v2(void) |
226 | { | 226 | { |
227 | return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); | 227 | return ~readl_relaxed(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1)); |
228 | } | 228 | } |
@@ -236,7 +236,7 @@ static int __init mxs_clocksource_init(struct clk *timer_clk) | |||
236 | else { | 236 | else { |
237 | clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), | 237 | clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1), |
238 | "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); | 238 | "mxs_timer", c, 200, 32, clocksource_mmio_readl_down); |
239 | setup_sched_clock(mxs_read_sched_clock_v2, 32, c); | 239 | sched_clock_register(mxs_read_sched_clock_v2, 32, c); |
240 | } | 240 | } |
241 | 241 | ||
242 | return 0; | 242 | return 0; |
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c index 1b74bea12385..ed7b73b508e0 100644 --- a/drivers/clocksource/nomadik-mtu.c +++ b/drivers/clocksource/nomadik-mtu.c | |||
@@ -76,7 +76,7 @@ static struct delay_timer mtu_delay_timer; | |||
76 | * local implementation which uses the clocksource to get some | 76 | * local implementation which uses the clocksource to get some |
77 | * better resolution when scheduling the kernel. | 77 | * better resolution when scheduling the kernel. |
78 | */ | 78 | */ |
79 | static u32 notrace nomadik_read_sched_clock(void) | 79 | static u64 notrace nomadik_read_sched_clock(void) |
80 | { | 80 | { |
81 | if (unlikely(!mtu_base)) | 81 | if (unlikely(!mtu_base)) |
82 | return 0; | 82 | return 0; |
@@ -231,7 +231,7 @@ static void __init __nmdk_timer_init(void __iomem *base, int irq, | |||
231 | "mtu_0"); | 231 | "mtu_0"); |
232 | 232 | ||
233 | #ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK | 233 | #ifdef CONFIG_CLKSRC_NOMADIK_MTU_SCHED_CLOCK |
234 | setup_sched_clock(nomadik_read_sched_clock, 32, rate); | 234 | sched_clock_register(nomadik_read_sched_clock, 32, rate); |
235 | #endif | 235 | #endif |
236 | 236 | ||
237 | /* Timer 1 is used for events, register irq and clockevents */ | 237 | /* Timer 1 is used for events, register irq and clockevents */ |
diff --git a/drivers/clocksource/samsung_pwm_timer.c b/drivers/clocksource/samsung_pwm_timer.c index ab29476ee5f9..85082e8d3052 100644 --- a/drivers/clocksource/samsung_pwm_timer.c +++ b/drivers/clocksource/samsung_pwm_timer.c | |||
@@ -331,7 +331,7 @@ static struct clocksource samsung_clocksource = { | |||
331 | * this wraps around for now, since it is just a relative time | 331 | * this wraps around for now, since it is just a relative time |
332 | * stamp. (Inspired by U300 implementation.) | 332 | * stamp. (Inspired by U300 implementation.) |
333 | */ | 333 | */ |
334 | static u32 notrace samsung_read_sched_clock(void) | 334 | static u64 notrace samsung_read_sched_clock(void) |
335 | { | 335 | { |
336 | return samsung_clocksource_read(NULL); | 336 | return samsung_clocksource_read(NULL); |
337 | } | 337 | } |
@@ -357,7 +357,7 @@ static void __init samsung_clocksource_init(void) | |||
357 | else | 357 | else |
358 | pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14; | 358 | pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14; |
359 | 359 | ||
360 | setup_sched_clock(samsung_read_sched_clock, | 360 | sched_clock_register(samsung_read_sched_clock, |
361 | pwm.variant.bits, clock_rate); | 361 | pwm.variant.bits, clock_rate); |
362 | 362 | ||
363 | samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits); | 363 | samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits); |
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c index 93961703b887..642849256d82 100644 --- a/drivers/clocksource/tegra20_timer.c +++ b/drivers/clocksource/tegra20_timer.c | |||
@@ -98,7 +98,7 @@ static struct clock_event_device tegra_clockevent = { | |||
98 | .set_mode = tegra_timer_set_mode, | 98 | .set_mode = tegra_timer_set_mode, |
99 | }; | 99 | }; |
100 | 100 | ||
101 | static u32 notrace tegra_read_sched_clock(void) | 101 | static u64 notrace tegra_read_sched_clock(void) |
102 | { | 102 | { |
103 | return timer_readl(TIMERUS_CNTR_1US); | 103 | return timer_readl(TIMERUS_CNTR_1US); |
104 | } | 104 | } |
@@ -181,8 +181,6 @@ static void __init tegra20_init_timer(struct device_node *np) | |||
181 | rate = clk_get_rate(clk); | 181 | rate = clk_get_rate(clk); |
182 | } | 182 | } |
183 | 183 | ||
184 | of_node_put(np); | ||
185 | |||
186 | switch (rate) { | 184 | switch (rate) { |
187 | case 12000000: | 185 | case 12000000: |
188 | timer_writel(0x000b, TIMERUS_USEC_CFG); | 186 | timer_writel(0x000b, TIMERUS_USEC_CFG); |
@@ -200,7 +198,7 @@ static void __init tegra20_init_timer(struct device_node *np) | |||
200 | WARN(1, "Unknown clock rate"); | 198 | WARN(1, "Unknown clock rate"); |
201 | } | 199 | } |
202 | 200 | ||
203 | setup_sched_clock(tegra_read_sched_clock, 32, 1000000); | 201 | sched_clock_register(tegra_read_sched_clock, 32, 1000000); |
204 | 202 | ||
205 | if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, | 203 | if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, |
206 | "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { | 204 | "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { |
@@ -241,8 +239,6 @@ static void __init tegra20_init_rtc(struct device_node *np) | |||
241 | else | 239 | else |
242 | clk_prepare_enable(clk); | 240 | clk_prepare_enable(clk); |
243 | 241 | ||
244 | of_node_put(np); | ||
245 | |||
246 | register_persistent_clock(NULL, tegra_read_persistent_clock); | 242 | register_persistent_clock(NULL, tegra_read_persistent_clock); |
247 | } | 243 | } |
248 | CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); | 244 | CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); |
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c index 0198504ef6b0..d8e47e502785 100644 --- a/drivers/clocksource/time-armada-370-xp.c +++ b/drivers/clocksource/time-armada-370-xp.c | |||
@@ -96,7 +96,7 @@ static void local_timer_ctrl_clrset(u32 clr, u32 set) | |||
96 | local_base + TIMER_CTRL_OFF); | 96 | local_base + TIMER_CTRL_OFF); |
97 | } | 97 | } |
98 | 98 | ||
99 | static u32 notrace armada_370_xp_read_sched_clock(void) | 99 | static u64 notrace armada_370_xp_read_sched_clock(void) |
100 | { | 100 | { |
101 | return ~readl(timer_base + TIMER0_VAL_OFF); | 101 | return ~readl(timer_base + TIMER0_VAL_OFF); |
102 | } | 102 | } |
@@ -258,7 +258,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np) | |||
258 | /* | 258 | /* |
259 | * Set scale and timer for sched_clock. | 259 | * Set scale and timer for sched_clock. |
260 | */ | 260 | */ |
261 | setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk); | 261 | sched_clock_register(armada_370_xp_read_sched_clock, 32, timer_clk); |
262 | 262 | ||
263 | /* | 263 | /* |
264 | * Setup free-running clocksource timer (interrupts | 264 | * Setup free-running clocksource timer (interrupts |
diff --git a/drivers/clocksource/timer-prima2.c b/drivers/clocksource/timer-prima2.c index ef3cfb269d8b..8a492d34ff9f 100644 --- a/drivers/clocksource/timer-prima2.c +++ b/drivers/clocksource/timer-prima2.c | |||
@@ -165,9 +165,9 @@ static struct irqaction sirfsoc_timer_irq = { | |||
165 | }; | 165 | }; |
166 | 166 | ||
167 | /* Overwrite weak default sched_clock with more precise one */ | 167 | /* Overwrite weak default sched_clock with more precise one */ |
168 | static u32 notrace sirfsoc_read_sched_clock(void) | 168 | static u64 notrace sirfsoc_read_sched_clock(void) |
169 | { | 169 | { |
170 | return (u32)(sirfsoc_timer_read(NULL) & 0xffffffff); | 170 | return sirfsoc_timer_read(NULL); |
171 | } | 171 | } |
172 | 172 | ||
173 | static void __init sirfsoc_clockevent_init(void) | 173 | static void __init sirfsoc_clockevent_init(void) |
@@ -206,7 +206,7 @@ static void __init sirfsoc_prima2_timer_init(struct device_node *np) | |||
206 | 206 | ||
207 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); | 207 | BUG_ON(clocksource_register_hz(&sirfsoc_clocksource, CLOCK_TICK_RATE)); |
208 | 208 | ||
209 | setup_sched_clock(sirfsoc_read_sched_clock, 32, CLOCK_TICK_RATE); | 209 | sched_clock_register(sirfsoc_read_sched_clock, 64, CLOCK_TICK_RATE); |
210 | 210 | ||
211 | BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); | 211 | BUG_ON(setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq)); |
212 | 212 | ||
diff --git a/drivers/clocksource/vf_pit_timer.c b/drivers/clocksource/vf_pit_timer.c index 587e0202a70b..02821b06a39e 100644 --- a/drivers/clocksource/vf_pit_timer.c +++ b/drivers/clocksource/vf_pit_timer.c | |||
@@ -52,7 +52,7 @@ static inline void pit_irq_acknowledge(void) | |||
52 | __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); | 52 | __raw_writel(PITTFLG_TIF, clkevt_base + PITTFLG); |
53 | } | 53 | } |
54 | 54 | ||
55 | static unsigned int pit_read_sched_clock(void) | 55 | static u64 pit_read_sched_clock(void) |
56 | { | 56 | { |
57 | return __raw_readl(clksrc_base + PITCVAL); | 57 | return __raw_readl(clksrc_base + PITCVAL); |
58 | } | 58 | } |
@@ -64,7 +64,7 @@ static int __init pit_clocksource_init(unsigned long rate) | |||
64 | __raw_writel(~0UL, clksrc_base + PITLDVAL); | 64 | __raw_writel(~0UL, clksrc_base + PITLDVAL); |
65 | __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); | 65 | __raw_writel(PITTCTRL_TEN, clksrc_base + PITTCTRL); |
66 | 66 | ||
67 | setup_sched_clock(pit_read_sched_clock, 32, rate); | 67 | sched_clock_register(pit_read_sched_clock, 32, rate); |
68 | return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, | 68 | return clocksource_mmio_init(clksrc_base + PITCVAL, "vf-pit", rate, |
69 | 300, 32, clocksource_mmio_readl_down); | 69 | 300, 32, clocksource_mmio_readl_down); |
70 | } | 70 | } |
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c index 64f553f04fa4..ad3c0e83a779 100644 --- a/drivers/clocksource/vt8500_timer.c +++ b/drivers/clocksource/vt8500_timer.c | |||
@@ -137,14 +137,12 @@ static void __init vt8500_timer_init(struct device_node *np) | |||
137 | if (!regbase) { | 137 | if (!regbase) { |
138 | pr_err("%s: Missing iobase description in Device Tree\n", | 138 | pr_err("%s: Missing iobase description in Device Tree\n", |
139 | __func__); | 139 | __func__); |
140 | of_node_put(np); | ||
141 | return; | 140 | return; |
142 | } | 141 | } |
143 | timer_irq = irq_of_parse_and_map(np, 0); | 142 | timer_irq = irq_of_parse_and_map(np, 0); |
144 | if (!timer_irq) { | 143 | if (!timer_irq) { |
145 | pr_err("%s: Missing irq description in Device Tree\n", | 144 | pr_err("%s: Missing irq description in Device Tree\n", |
146 | __func__); | 145 | __func__); |
147 | of_node_put(np); | ||
148 | return; | 146 | return; |
149 | } | 147 | } |
150 | 148 | ||
diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h index 0857922e8ad0..493aa021c7a9 100644 --- a/include/linux/clockchips.h +++ b/include/linux/clockchips.h | |||
@@ -60,6 +60,7 @@ enum clock_event_mode { | |||
60 | * Core shall set the interrupt affinity dynamically in broadcast mode | 60 | * Core shall set the interrupt affinity dynamically in broadcast mode |
61 | */ | 61 | */ |
62 | #define CLOCK_EVT_FEAT_DYNIRQ 0x000020 | 62 | #define CLOCK_EVT_FEAT_DYNIRQ 0x000020 |
63 | #define CLOCK_EVT_FEAT_PERCPU 0x000040 | ||
63 | 64 | ||
64 | /** | 65 | /** |
65 | * struct clock_event_device - clock event device descriptor | 66 | * struct clock_event_device - clock event device descriptor |
diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c index 218bcb565fed..9532690daaa9 100644 --- a/kernel/time/tick-broadcast.c +++ b/kernel/time/tick-broadcast.c | |||
@@ -70,6 +70,7 @@ static bool tick_check_broadcast_device(struct clock_event_device *curdev, | |||
70 | struct clock_event_device *newdev) | 70 | struct clock_event_device *newdev) |
71 | { | 71 | { |
72 | if ((newdev->features & CLOCK_EVT_FEAT_DUMMY) || | 72 | if ((newdev->features & CLOCK_EVT_FEAT_DUMMY) || |
73 | (newdev->features & CLOCK_EVT_FEAT_PERCPU) || | ||
73 | (newdev->features & CLOCK_EVT_FEAT_C3STOP)) | 74 | (newdev->features & CLOCK_EVT_FEAT_C3STOP)) |
74 | return false; | 75 | return false; |
75 | 76 | ||