ALSA - hda: Add support for parsing new HDA capabilities

Skylake onwards HDA controller supports new capabilities like
Global Time Stamping (GTS) capability. So add support to parse
these new capabilities.

Signed-off-by: Guneshwor Singh <guneshwor.o.singh@intel.com>
Signed-off-by: Hardik T Shah <hardik.t.shah@intel.com>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>

1 files changed, 36 insertions, 0 deletions

diff --git a/include/sound/hda_register.h b/include/sound/hda_register.h
index ff1aecf325e8..0013063db7f2 100644
--- a/include/sound/hda_register.h
+++ b/include/sound/hda_register.h
@@ -89,6 +89,19 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 #define AZX_REG_SD_BDLPL                0x18
 #define AZX_REG_SD_BDLPU                0x1c
 
+/* GTS registers */
+#define AZX_REG_LLCH                    0x14
+
+#define AZX_REG_GTS_BASE                0x520
+
+#define AZX_REG_GTSCC   (AZX_REG_GTS_BASE + 0x00)
+#define AZX_REG_WALFCC  (AZX_REG_GTS_BASE + 0x04)
+#define AZX_REG_TSCCL   (AZX_REG_GTS_BASE + 0x08)
+#define AZX_REG_TSCCU   (AZX_REG_GTS_BASE + 0x0C)
+#define AZX_REG_LLPFOC  (AZX_REG_GTS_BASE + 0x14)
+#define AZX_REG_LLPCL   (AZX_REG_GTS_BASE + 0x18)
+#define AZX_REG_LLPCU   (AZX_REG_GTS_BASE + 0x1C)
+
 /* Haswell/Broadwell display HD-A controller Extended Mode registers */
 #define AZX_REG_HSW_EM4                 0x100c
 #define AZX_REG_HSW_EM5                 0x1010
@@ -242,6 +255,29 @@ enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 /* Interval used to calculate the iterating register offset */
 #define AZX_DRSM_INTERVAL               0x08
 
+/* Global time synchronization registers */
+#define GTSCC_TSCCD_MASK                0x80000000
+#define GTSCC_TSCCD_SHIFT               BIT(31)
+#define GTSCC_TSCCI_MASK                0x20
+#define GTSCC_CDMAS_DMA_DIR_SHIFT       4
+
+#define WALFCC_CIF_MASK                 0x1FF
+#define WALFCC_FN_SHIFT                 9
+#define HDA_CLK_CYCLES_PER_FRAME        512
+
+/*
+ * An error occurs near frame "rollover". The clocks in frame value indicates
+ * whether this error may have occurred. Here we use the value of 10. Please
+ * see the errata for the right number [<10]
+ */
+#define HDA_MAX_CYCLE_VALUE             499
+#define HDA_MAX_CYCLE_OFFSET            10
+#define HDA_MAX_CYCLE_READ_RETRY        10
+
+#define TSCCU_CCU_SHIFT                 32
+#define LLPC_CCU_SHIFT                  32
+
+
 /*
  * helpers to read the stream position
  */