diff options
author | dawei.chien@mediatek.com <dawei.chien@mediatek.com> | 2016-08-17 23:50:52 -0400 |
---|---|---|
committer | Zhang Rui <rui.zhang@intel.com> | 2016-09-27 02:02:16 -0400 |
commit | b7cf0053738c5491df532a625321e976eaa93b22 (patch) | |
tree | 616e2e25e3a4072b918679214f803adb710dfce9 /drivers/thermal | |
parent | 77d6e7212cd53dd93de6fab26d7ca89c8d591c07 (diff) |
thermal: Add Mediatek thermal driver for mt2701.
This patch adds support for mt2701 chip to mtk_thermal,
and integrate both mt8173 and mt2701 on the same driver.
MT8173 has four banks and five sensors, and MT2701 has
only one bank and three sensors.
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Zhang Rui <rui.zhang@intel.com>
Diffstat (limited to 'drivers/thermal')
-rw-r--r-- | drivers/thermal/mtk_thermal.c | 215 |
1 files changed, 152 insertions, 63 deletions
diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c index 262ab0a2266f..7b233c718e2e 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mtk_thermal.c | |||
@@ -2,6 +2,7 @@ | |||
2 | * Copyright (c) 2015 MediaTek Inc. | 2 | * Copyright (c) 2015 MediaTek Inc. |
3 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> | 3 | * Author: Hanyi Wu <hanyi.wu@mediatek.com> |
4 | * Sascha Hauer <s.hauer@pengutronix.de> | 4 | * Sascha Hauer <s.hauer@pengutronix.de> |
5 | * Dawei Chien <dawei.chien@mediatek.com> | ||
5 | * | 6 | * |
6 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
7 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
@@ -21,6 +22,7 @@ | |||
21 | #include <linux/nvmem-consumer.h> | 22 | #include <linux/nvmem-consumer.h> |
22 | #include <linux/of.h> | 23 | #include <linux/of.h> |
23 | #include <linux/of_address.h> | 24 | #include <linux/of_address.h> |
25 | #include <linux/of_device.h> | ||
24 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
25 | #include <linux/slab.h> | 27 | #include <linux/slab.h> |
26 | #include <linux/io.h> | 28 | #include <linux/io.h> |
@@ -88,6 +90,7 @@ | |||
88 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) | 90 | #define TEMP_ADCVALIDMASK_VALID_HIGH BIT(5) |
89 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) | 91 | #define TEMP_ADCVALIDMASK_VALID_POS(bit) (bit) |
90 | 92 | ||
93 | /* MT8173 thermal sensors */ | ||
91 | #define MT8173_TS1 0 | 94 | #define MT8173_TS1 0 |
92 | #define MT8173_TS2 1 | 95 | #define MT8173_TS2 1 |
93 | #define MT8173_TS3 2 | 96 | #define MT8173_TS3 2 |
@@ -106,7 +109,12 @@ | |||
106 | /* The number of sensing points per bank */ | 109 | /* The number of sensing points per bank */ |
107 | #define MT8173_NUM_SENSORS_PER_ZONE 4 | 110 | #define MT8173_NUM_SENSORS_PER_ZONE 4 |
108 | 111 | ||
109 | /* Layout of the fuses providing the calibration data */ | 112 | /* |
113 | * Layout of the fuses providing the calibration data | ||
114 | * These macros could be used for both MT8173 and MT2701. | ||
115 | * MT8173 has five sensors and need five VTS calibration data, | ||
116 | * and MT2701 has three sensors and need three VTS calibration data. | ||
117 | */ | ||
110 | #define MT8173_CALIB_BUF0_VALID BIT(0) | 118 | #define MT8173_CALIB_BUF0_VALID BIT(0) |
111 | #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff) | 119 | #define MT8173_CALIB_BUF1_ADC_GE(x) (((x) >> 22) & 0x3ff) |
112 | #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff) | 120 | #define MT8173_CALIB_BUF0_VTS_TS1(x) (((x) >> 17) & 0x1ff) |
@@ -117,24 +125,50 @@ | |||
117 | #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f) | 125 | #define MT8173_CALIB_BUF0_DEGC_CALI(x) (((x) >> 1) & 0x3f) |
118 | #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f) | 126 | #define MT8173_CALIB_BUF0_O_SLOPE(x) (((x) >> 26) & 0x3f) |
119 | 127 | ||
128 | /* MT2701 thermal sensors */ | ||
129 | #define MT2701_TS1 0 | ||
130 | #define MT2701_TS2 1 | ||
131 | #define MT2701_TSABB 2 | ||
132 | |||
133 | /* AUXADC channel 11 is used for the temperature sensors */ | ||
134 | #define MT2701_TEMP_AUXADC_CHANNEL 11 | ||
135 | |||
136 | /* The total number of temperature sensors in the MT2701 */ | ||
137 | #define MT2701_NUM_SENSORS 3 | ||
138 | |||
120 | #define THERMAL_NAME "mtk-thermal" | 139 | #define THERMAL_NAME "mtk-thermal" |
121 | 140 | ||
141 | /* The number of sensing points per bank */ | ||
142 | #define MT2701_NUM_SENSORS_PER_ZONE 3 | ||
143 | |||
122 | struct mtk_thermal; | 144 | struct mtk_thermal; |
123 | 145 | ||
146 | struct thermal_bank_cfg { | ||
147 | unsigned int num_sensors; | ||
148 | const int *sensors; | ||
149 | }; | ||
150 | |||
124 | struct mtk_thermal_bank { | 151 | struct mtk_thermal_bank { |
125 | struct mtk_thermal *mt; | 152 | struct mtk_thermal *mt; |
126 | int id; | 153 | int id; |
127 | }; | 154 | }; |
128 | 155 | ||
156 | struct mtk_thermal_data { | ||
157 | s32 num_banks; | ||
158 | s32 num_sensors; | ||
159 | s32 auxadc_channel; | ||
160 | const int *sensor_mux_values; | ||
161 | const int *msr; | ||
162 | const int *adcpnp; | ||
163 | struct thermal_bank_cfg bank_data[]; | ||
164 | }; | ||
165 | |||
129 | struct mtk_thermal { | 166 | struct mtk_thermal { |
130 | struct device *dev; | 167 | struct device *dev; |
131 | void __iomem *thermal_base; | 168 | void __iomem *thermal_base; |
132 | 169 | ||
133 | struct clk *clk_peri_therm; | 170 | struct clk *clk_peri_therm; |
134 | struct clk *clk_auxadc; | 171 | struct clk *clk_auxadc; |
135 | |||
136 | struct mtk_thermal_bank banks[MT8173_NUM_ZONES]; | ||
137 | |||
138 | /* lock: for getting and putting banks */ | 172 | /* lock: for getting and putting banks */ |
139 | struct mutex lock; | 173 | struct mutex lock; |
140 | 174 | ||
@@ -144,16 +178,44 @@ struct mtk_thermal { | |||
144 | s32 o_slope; | 178 | s32 o_slope; |
145 | s32 vts[MT8173_NUM_SENSORS]; | 179 | s32 vts[MT8173_NUM_SENSORS]; |
146 | 180 | ||
181 | const struct mtk_thermal_data *conf; | ||
182 | struct mtk_thermal_bank banks[]; | ||
147 | }; | 183 | }; |
148 | 184 | ||
149 | struct mtk_thermal_bank_cfg { | 185 | /* MT8173 thermal sensor data */ |
150 | unsigned int num_sensors; | 186 | const int mt8173_bank_data[MT8173_NUM_ZONES][3] = { |
151 | unsigned int sensors[MT8173_NUM_SENSORS_PER_ZONE]; | 187 | { MT8173_TS2, MT8173_TS3 }, |
188 | { MT8173_TS2, MT8173_TS4 }, | ||
189 | { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | ||
190 | { MT8173_TS2 }, | ||
152 | }; | 191 | }; |
153 | 192 | ||
154 | static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; | 193 | const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = { |
194 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR2 | ||
195 | }; | ||
155 | 196 | ||
156 | /* | 197 | const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = { |
198 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3 | ||
199 | }; | ||
200 | |||
201 | const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; | ||
202 | |||
203 | /* MT2701 thermal sensor data */ | ||
204 | const int mt2701_bank_data[MT2701_NUM_SENSORS] = { | ||
205 | MT2701_TS1, MT2701_TS2, MT2701_TSABB | ||
206 | }; | ||
207 | |||
208 | const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = { | ||
209 | TEMP_MSR0, TEMP_MSR1, TEMP_MSR2 | ||
210 | }; | ||
211 | |||
212 | const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = { | ||
213 | TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2 | ||
214 | }; | ||
215 | |||
216 | const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 }; | ||
217 | |||
218 | /** | ||
157 | * The MT8173 thermal controller has four banks. Each bank can read up to | 219 | * The MT8173 thermal controller has four banks. Each bank can read up to |
158 | * four temperature sensors simultaneously. The MT8173 has a total of 5 | 220 | * four temperature sensors simultaneously. The MT8173 has a total of 5 |
159 | * temperature sensors. We use each bank to measure a certain area of the | 221 | * temperature sensors. We use each bank to measure a certain area of the |
@@ -166,42 +228,53 @@ static const int sensor_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 }; | |||
166 | * data, and this indeed needs the temperatures of the individual banks | 228 | * data, and this indeed needs the temperatures of the individual banks |
167 | * for making better decisions. | 229 | * for making better decisions. |
168 | */ | 230 | */ |
169 | static const struct mtk_thermal_bank_cfg bank_data[] = { | 231 | static const struct mtk_thermal_data mt8173_thermal_data = { |
170 | { | 232 | .auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL, |
171 | .num_sensors = 2, | 233 | .num_banks = MT8173_NUM_ZONES, |
172 | .sensors = { MT8173_TS2, MT8173_TS3 }, | 234 | .num_sensors = MT8173_NUM_SENSORS, |
173 | }, { | 235 | .bank_data = { |
174 | .num_sensors = 2, | 236 | { |
175 | .sensors = { MT8173_TS2, MT8173_TS4 }, | 237 | .num_sensors = 2, |
176 | }, { | 238 | .sensors = mt8173_bank_data[0], |
177 | .num_sensors = 3, | 239 | }, { |
178 | .sensors = { MT8173_TS1, MT8173_TS2, MT8173_TSABB }, | 240 | .num_sensors = 2, |
179 | }, { | 241 | .sensors = mt8173_bank_data[1], |
180 | .num_sensors = 1, | 242 | }, { |
181 | .sensors = { MT8173_TS2 }, | 243 | .num_sensors = 3, |
244 | .sensors = mt8173_bank_data[2], | ||
245 | }, { | ||
246 | .num_sensors = 1, | ||
247 | .sensors = mt8173_bank_data[3], | ||
248 | }, | ||
182 | }, | 249 | }, |
250 | .msr = mt8173_msr, | ||
251 | .adcpnp = mt8173_adcpnp, | ||
252 | .sensor_mux_values = mt8173_mux_values, | ||
183 | }; | 253 | }; |
184 | 254 | ||
185 | struct mtk_thermal_sense_point { | 255 | /** |
186 | int msr; | 256 | * The MT2701 thermal controller has one bank, which can read up to |
187 | int adcpnp; | 257 | * three temperature sensors simultaneously. The MT2701 has a total of 3 |
188 | }; | 258 | * temperature sensors. |
189 | 259 | * | |
190 | static const struct mtk_thermal_sense_point | 260 | * The thermal core only gets the maximum temperature of this one bank, |
191 | sensing_points[MT8173_NUM_SENSORS_PER_ZONE] = { | 261 | * so the bank concept wouldn't be necessary here. However, the SVS (Smart |
192 | { | 262 | * Voltage Scaling) unit makes its decisions based on the same bank |
193 | .msr = TEMP_MSR0, | 263 | * data. |
194 | .adcpnp = TEMP_ADCPNP0, | 264 | */ |
195 | }, { | 265 | static const struct mtk_thermal_data mt2701_thermal_data = { |
196 | .msr = TEMP_MSR1, | 266 | .auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL, |
197 | .adcpnp = TEMP_ADCPNP1, | 267 | .num_banks = 1, |
198 | }, { | 268 | .num_sensors = MT2701_NUM_SENSORS, |
199 | .msr = TEMP_MSR2, | 269 | .bank_data = { |
200 | .adcpnp = TEMP_ADCPNP2, | 270 | { |
201 | }, { | 271 | .num_sensors = 3, |
202 | .msr = TEMP_MSR3, | 272 | .sensors = mt2701_bank_data, |
203 | .adcpnp = TEMP_ADCPNP3, | 273 | }, |
204 | }, | 274 | }, |
275 | .msr = mt2701_msr, | ||
276 | .adcpnp = mt2701_adcpnp, | ||
277 | .sensor_mux_values = mt2701_mux_values, | ||
205 | }; | 278 | }; |
206 | 279 | ||
207 | /** | 280 | /** |
@@ -270,13 +343,16 @@ static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank) | |||
270 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) | 343 | static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank) |
271 | { | 344 | { |
272 | struct mtk_thermal *mt = bank->mt; | 345 | struct mtk_thermal *mt = bank->mt; |
346 | const struct mtk_thermal_data *conf = mt->conf; | ||
273 | int i, temp = INT_MIN, max = INT_MIN; | 347 | int i, temp = INT_MIN, max = INT_MIN; |
274 | u32 raw; | 348 | u32 raw; |
275 | 349 | ||
276 | for (i = 0; i < bank_data[bank->id].num_sensors; i++) { | 350 | for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) { |
277 | raw = readl(mt->thermal_base + sensing_points[i].msr); | 351 | raw = readl(mt->thermal_base + conf->msr[i]); |
278 | 352 | ||
279 | temp = raw_to_mcelsius(mt, bank_data[bank->id].sensors[i], raw); | 353 | temp = raw_to_mcelsius(mt, |
354 | conf->bank_data[bank->id].sensors[i], | ||
355 | raw); | ||
280 | 356 | ||
281 | /* | 357 | /* |
282 | * The first read of a sensor often contains very high bogus | 358 | * The first read of a sensor often contains very high bogus |
@@ -299,7 +375,7 @@ static int mtk_read_temp(void *data, int *temperature) | |||
299 | int i; | 375 | int i; |
300 | int tempmax = INT_MIN; | 376 | int tempmax = INT_MIN; |
301 | 377 | ||
302 | for (i = 0; i < MT8173_NUM_ZONES; i++) { | 378 | for (i = 0; i < mt->conf->num_banks; i++) { |
303 | struct mtk_thermal_bank *bank = &mt->banks[i]; | 379 | struct mtk_thermal_bank *bank = &mt->banks[i]; |
304 | 380 | ||
305 | mtk_thermal_get_bank(bank); | 381 | mtk_thermal_get_bank(bank); |
@@ -322,7 +398,7 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |||
322 | u32 apmixed_phys_base, u32 auxadc_phys_base) | 398 | u32 apmixed_phys_base, u32 auxadc_phys_base) |
323 | { | 399 | { |
324 | struct mtk_thermal_bank *bank = &mt->banks[num]; | 400 | struct mtk_thermal_bank *bank = &mt->banks[num]; |
325 | const struct mtk_thermal_bank_cfg *cfg = &bank_data[num]; | 401 | const struct mtk_thermal_data *conf = mt->conf; |
326 | int i; | 402 | int i; |
327 | 403 | ||
328 | bank->id = num; | 404 | bank->id = num; |
@@ -368,7 +444,7 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |||
368 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) | 444 | * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0) |
369 | * automatically by hw | 445 | * automatically by hw |
370 | */ | 446 | */ |
371 | writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCMUX); | 447 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCMUX); |
372 | 448 | ||
373 | /* AHB address for auxadc mux selection */ | 449 | /* AHB address for auxadc mux selection */ |
374 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, | 450 | writel(auxadc_phys_base + AUXADC_CON1_CLR_V, |
@@ -379,18 +455,18 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |||
379 | mt->thermal_base + TEMP_PNPMUXADDR); | 455 | mt->thermal_base + TEMP_PNPMUXADDR); |
380 | 456 | ||
381 | /* AHB value for auxadc enable */ | 457 | /* AHB value for auxadc enable */ |
382 | writel(BIT(MT8173_TEMP_AUXADC_CHANNEL), mt->thermal_base + TEMP_ADCEN); | 458 | writel(BIT(conf->auxadc_channel), mt->thermal_base + TEMP_ADCEN); |
383 | 459 | ||
384 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ | 460 | /* AHB address for auxadc enable (channel 0 immediate mode selected) */ |
385 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, | 461 | writel(auxadc_phys_base + AUXADC_CON1_SET_V, |
386 | mt->thermal_base + TEMP_ADCENADDR); | 462 | mt->thermal_base + TEMP_ADCENADDR); |
387 | 463 | ||
388 | /* AHB address for auxadc valid bit */ | 464 | /* AHB address for auxadc valid bit */ |
389 | writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), | 465 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
390 | mt->thermal_base + TEMP_ADCVALIDADDR); | 466 | mt->thermal_base + TEMP_ADCVALIDADDR); |
391 | 467 | ||
392 | /* AHB address for auxadc voltage output */ | 468 | /* AHB address for auxadc voltage output */ |
393 | writel(auxadc_phys_base + AUXADC_DATA(MT8173_TEMP_AUXADC_CHANNEL), | 469 | writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel), |
394 | mt->thermal_base + TEMP_ADCVOLTADDR); | 470 | mt->thermal_base + TEMP_ADCVOLTADDR); |
395 | 471 | ||
396 | /* read valid & voltage are at the same register */ | 472 | /* read valid & voltage are at the same register */ |
@@ -407,11 +483,12 @@ static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num, | |||
407 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | 483 | writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
408 | mt->thermal_base + TEMP_ADCWRITECTRL); | 484 | mt->thermal_base + TEMP_ADCWRITECTRL); |
409 | 485 | ||
410 | for (i = 0; i < cfg->num_sensors; i++) | 486 | for (i = 0; i < conf->bank_data[num].num_sensors; i++) |
411 | writel(sensor_mux_values[cfg->sensors[i]], | 487 | writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]], |
412 | mt->thermal_base + sensing_points[i].adcpnp); | 488 | mt->thermal_base + conf->adcpnp[i]); |
413 | 489 | ||
414 | writel((1 << cfg->num_sensors) - 1, mt->thermal_base + TEMP_MONCTL0); | 490 | writel((1 << conf->bank_data[num].num_sensors) - 1, |
491 | mt->thermal_base + TEMP_MONCTL0); | ||
415 | 492 | ||
416 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | | 493 | writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE | |
417 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, | 494 | TEMP_ADCWRITECTRL_ADC_MUX_WRITE, |
@@ -442,7 +519,7 @@ static int mtk_thermal_get_calibration_data(struct device *dev, | |||
442 | 519 | ||
443 | /* Start with default values */ | 520 | /* Start with default values */ |
444 | mt->adc_ge = 512; | 521 | mt->adc_ge = 512; |
445 | for (i = 0; i < MT8173_NUM_SENSORS; i++) | 522 | for (i = 0; i < mt->conf->num_sensors; i++) |
446 | mt->vts[i] = 260; | 523 | mt->vts[i] = 260; |
447 | mt->degc_cali = 40; | 524 | mt->degc_cali = 40; |
448 | mt->o_slope = 0; | 525 | mt->o_slope = 0; |
@@ -486,18 +563,36 @@ out: | |||
486 | return ret; | 563 | return ret; |
487 | } | 564 | } |
488 | 565 | ||
566 | static const struct of_device_id mtk_thermal_of_match[] = { | ||
567 | { | ||
568 | .compatible = "mediatek,mt8173-thermal", | ||
569 | .data = (void *)&mt8173_thermal_data, | ||
570 | }, | ||
571 | { | ||
572 | .compatible = "mediatek,mt2701-thermal", | ||
573 | .data = (void *)&mt2701_thermal_data, | ||
574 | }, { | ||
575 | }, | ||
576 | }; | ||
577 | MODULE_DEVICE_TABLE(of, mtk_thermal_of_match); | ||
578 | |||
489 | static int mtk_thermal_probe(struct platform_device *pdev) | 579 | static int mtk_thermal_probe(struct platform_device *pdev) |
490 | { | 580 | { |
491 | int ret, i; | 581 | int ret, i; |
492 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; | 582 | struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node; |
493 | struct mtk_thermal *mt; | 583 | struct mtk_thermal *mt; |
494 | struct resource *res; | 584 | struct resource *res; |
585 | const struct of_device_id *of_id; | ||
495 | u64 auxadc_phys_base, apmixed_phys_base; | 586 | u64 auxadc_phys_base, apmixed_phys_base; |
496 | 587 | ||
497 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); | 588 | mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL); |
498 | if (!mt) | 589 | if (!mt) |
499 | return -ENOMEM; | 590 | return -ENOMEM; |
500 | 591 | ||
592 | of_id = of_match_device(mtk_thermal_of_match, &pdev->dev); | ||
593 | if (of_id) | ||
594 | mt->conf = (const struct mtk_thermal_data *)of_id->data; | ||
595 | |||
501 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); | 596 | mt->clk_peri_therm = devm_clk_get(&pdev->dev, "therm"); |
502 | if (IS_ERR(mt->clk_peri_therm)) | 597 | if (IS_ERR(mt->clk_peri_therm)) |
503 | return PTR_ERR(mt->clk_peri_therm); | 598 | return PTR_ERR(mt->clk_peri_therm); |
@@ -565,7 +660,7 @@ static int mtk_thermal_probe(struct platform_device *pdev) | |||
565 | goto err_disable_clk_auxadc; | 660 | goto err_disable_clk_auxadc; |
566 | } | 661 | } |
567 | 662 | ||
568 | for (i = 0; i < MT8173_NUM_ZONES; i++) | 663 | for (i = 0; i < mt->conf->num_banks; i++) |
569 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, | 664 | mtk_thermal_init_bank(mt, i, apmixed_phys_base, |
570 | auxadc_phys_base); | 665 | auxadc_phys_base); |
571 | 666 | ||
@@ -592,13 +687,6 @@ static int mtk_thermal_remove(struct platform_device *pdev) | |||
592 | return 0; | 687 | return 0; |
593 | } | 688 | } |
594 | 689 | ||
595 | static const struct of_device_id mtk_thermal_of_match[] = { | ||
596 | { | ||
597 | .compatible = "mediatek,mt8173-thermal", | ||
598 | }, { | ||
599 | }, | ||
600 | }; | ||
601 | |||
602 | static struct platform_driver mtk_thermal_driver = { | 690 | static struct platform_driver mtk_thermal_driver = { |
603 | .probe = mtk_thermal_probe, | 691 | .probe = mtk_thermal_probe, |
604 | .remove = mtk_thermal_remove, | 692 | .remove = mtk_thermal_remove, |
@@ -610,6 +698,7 @@ static struct platform_driver mtk_thermal_driver = { | |||
610 | 698 | ||
611 | module_platform_driver(mtk_thermal_driver); | 699 | module_platform_driver(mtk_thermal_driver); |
612 | 700 | ||
701 | MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>"); | ||
613 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); | 702 | MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); |
614 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); | 703 | MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>"); |
615 | MODULE_DESCRIPTION("Mediatek thermal driver"); | 704 | MODULE_DESCRIPTION("Mediatek thermal driver"); |