spi: s3c64xx: do not disable the clock while configuring the spi

When the clock is coming from the cmu it is not required to be
disabled and then re-enabled in order to change the rate.

Besides, some exynos chipsets (e.g. exynos5433) do not deliver
any to the SFR if one from the pclk ("spi" in this case) or sclk
("busclk") is disabled.

Remove the clock disabling/enabling to avoid falling into this
situation.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Signed-off-by: Mark Brown <broonie@kernel.org>

1 files changed, 1 insertions, 7 deletions

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 9f0119f64f93..df88fa161d8a 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -596,9 +596,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
         u32 val;
 
         /* Disable Clock */
-        if (sdd->port_conf->clk_from_cmu) {
-                clk_disable_unprepare(sdd->src_clk);
-        } else {
+        if (!sdd->port_conf->clk_from_cmu) {
                 val = readl(regs + S3C64XX_SPI_CLK_CFG);
                 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
                 writel(val, regs + S3C64XX_SPI_CLK_CFG);
@@ -641,11 +639,7 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
         writel(val, regs + S3C64XX_SPI_MODE_CFG);
 
         if (sdd->port_conf->clk_from_cmu) {
-                /* Configure Clock */
-                /* There is half-multiplier before the SPI */
                 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
-                /* Enable Clock */
-                clk_prepare_enable(sdd->src_clk);
         } else {
                 /* Configure Clock */
                 val = readl(regs + S3C64XX_SPI_CLK_CFG);