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authorJarkko Nikula <jarkko.nikula@linux.intel.com>2015-10-28 09:13:41 -0400
committerMark Brown <broonie@kernel.org>2015-10-29 22:18:05 -0400
commit8b136baa5892f25bba0373d6eb0f5f84efc93986 (patch)
treedb604a7b69c70e6d6be3029c4611e698cefe62d4 /drivers/spi/spi-pxa2xx.c
parentd0283eb2dbc11ec08375fdf6a436e96d25b3a593 (diff)
spi: pxa2xx: Detect number of enabled Intel LPSS SPI chip select signals
SPI capabilities register located in private registers space of newer Intel LPSS SPI host controllers tell in register bits 12:9 which chip select signals are enabled. Use that information for detecting the number of chip selects. For simplicity we assume chip selects are enabled one after another without disabled chip selects between. For instance CS0 | CS1 | CS2 but not CS0 | CS1 | CS3. Signed-off-by: Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-pxa2xx.c')
-rw-r--r--drivers/spi/spi-pxa2xx.c22
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 040f6bb566a1..a5c2dce7d0a3 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -13,6 +13,7 @@
13 * GNU General Public License for more details. 13 * GNU General Public License for more details.
14 */ 14 */
15 15
16#include <linux/bitops.h>
16#include <linux/init.h> 17#include <linux/init.h>
17#include <linux/module.h> 18#include <linux/module.h>
18#include <linux/device.h> 19#include <linux/device.h>
@@ -66,6 +67,8 @@ MODULE_ALIAS("platform:pxa2xx-spi");
66#define LPSS_CS_CONTROL_CS_HIGH BIT(1) 67#define LPSS_CS_CONTROL_CS_HIGH BIT(1)
67#define LPSS_CS_CONTROL_CS_SEL_SHIFT 8 68#define LPSS_CS_CONTROL_CS_SEL_SHIFT 8
68#define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT) 69#define LPSS_CS_CONTROL_CS_SEL_MASK (3 << LPSS_CS_CONTROL_CS_SEL_SHIFT)
70#define LPSS_CAPS_CS_EN_SHIFT 9
71#define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
69 72
70struct lpss_config { 73struct lpss_config {
71 /* LPSS offset from drv_data->ioaddr */ 74 /* LPSS offset from drv_data->ioaddr */
@@ -74,6 +77,7 @@ struct lpss_config {
74 int reg_general; 77 int reg_general;
75 int reg_ssp; 78 int reg_ssp;
76 int reg_cs_ctrl; 79 int reg_cs_ctrl;
80 int reg_capabilities;
77 /* FIFO thresholds */ 81 /* FIFO thresholds */
78 u32 rx_threshold; 82 u32 rx_threshold;
79 u32 tx_threshold_lo; 83 u32 tx_threshold_lo;
@@ -87,6 +91,7 @@ static const struct lpss_config lpss_platforms[] = {
87 .reg_general = 0x08, 91 .reg_general = 0x08,
88 .reg_ssp = 0x0c, 92 .reg_ssp = 0x0c,
89 .reg_cs_ctrl = 0x18, 93 .reg_cs_ctrl = 0x18,
94 .reg_capabilities = -1,
90 .rx_threshold = 64, 95 .rx_threshold = 64,
91 .tx_threshold_lo = 160, 96 .tx_threshold_lo = 160,
92 .tx_threshold_hi = 224, 97 .tx_threshold_hi = 224,
@@ -96,6 +101,7 @@ static const struct lpss_config lpss_platforms[] = {
96 .reg_general = 0x08, 101 .reg_general = 0x08,
97 .reg_ssp = 0x0c, 102 .reg_ssp = 0x0c,
98 .reg_cs_ctrl = 0x18, 103 .reg_cs_ctrl = 0x18,
104 .reg_capabilities = -1,
99 .rx_threshold = 64, 105 .rx_threshold = 64,
100 .tx_threshold_lo = 160, 106 .tx_threshold_lo = 160,
101 .tx_threshold_hi = 224, 107 .tx_threshold_hi = 224,
@@ -105,6 +111,7 @@ static const struct lpss_config lpss_platforms[] = {
105 .reg_general = -1, 111 .reg_general = -1,
106 .reg_ssp = 0x20, 112 .reg_ssp = 0x20,
107 .reg_cs_ctrl = 0x24, 113 .reg_cs_ctrl = 0x24,
114 .reg_capabilities = 0xfc,
108 .rx_threshold = 1, 115 .rx_threshold = 1,
109 .tx_threshold_lo = 32, 116 .tx_threshold_lo = 32,
110 .tx_threshold_hi = 56, 117 .tx_threshold_hi = 56,
@@ -1400,6 +1407,7 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1400 struct spi_master *master; 1407 struct spi_master *master;
1401 struct driver_data *drv_data; 1408 struct driver_data *drv_data;
1402 struct ssp_device *ssp; 1409 struct ssp_device *ssp;
1410 const struct lpss_config *config;
1403 int status; 1411 int status;
1404 u32 tmp; 1412 u32 tmp;
1405 1413
@@ -1439,7 +1447,6 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1439 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1447 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1440 1448
1441 master->bus_num = ssp->port_id; 1449 master->bus_num = ssp->port_id;
1442 master->num_chipselect = platform_info->num_chipselect;
1443 master->dma_alignment = DMA_ALIGNMENT; 1450 master->dma_alignment = DMA_ALIGNMENT;
1444 master->cleanup = cleanup; 1451 master->cleanup = cleanup;
1445 master->setup = setup; 1452 master->setup = setup;
@@ -1525,6 +1532,19 @@ static int pxa2xx_spi_probe(struct platform_device *pdev)
1525 if (is_lpss_ssp(drv_data)) 1532 if (is_lpss_ssp(drv_data))
1526 lpss_ssp_setup(drv_data); 1533 lpss_ssp_setup(drv_data);
1527 1534
1535 if (is_lpss_ssp(drv_data)) {
1536 lpss_ssp_setup(drv_data);
1537 config = lpss_get_config(drv_data);
1538 if (config->reg_capabilities >= 0) {
1539 tmp = __lpss_ssp_read_priv(drv_data,
1540 config->reg_capabilities);
1541 tmp &= LPSS_CAPS_CS_EN_MASK;
1542 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1543 platform_info->num_chipselect = ffz(tmp);
1544 }
1545 }
1546 master->num_chipselect = platform_info->num_chipselect;
1547
1528 tasklet_init(&drv_data->pump_transfers, pump_transfers, 1548 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1529 (unsigned long)drv_data); 1549 (unsigned long)drv_data);
1530 1550