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authorLeilk Liu <leilk.liu@mediatek.com>2015-08-20 05:19:08 -0400
committerMark Brown <broonie@kernel.org>2015-08-20 14:16:12 -0400
commita71d6ea6d3ec3e8ba4220370f29531903e3bc153 (patch)
treefb05c1b144b607e00532763d47961b0c07132a2b /drivers/spi/spi-mt65xx.c
parentaf57937e862370c14b7d71d15d969593ffca1ba8 (diff)
spi: mediatek: use BIT() to instead of SPI_CMD_*_OFFSET
This patch removes SPI_CMD_*_OFFSET defines, and uses the BIT(x) defines instead. Signed-off-by: Leilk Liu <leilk.liu@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'drivers/spi/spi-mt65xx.c')
-rw-r--r--drivers/spi/spi-mt65xx.c37
1 files changed, 20 insertions, 17 deletions
diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c
index 55d1c3e51864..516b4ed757e5 100644
--- a/drivers/spi/spi-mt65xx.c
+++ b/drivers/spi/spi-mt65xx.c
@@ -48,15 +48,8 @@
48#define SPI_CFG1_PACKET_LOOP_MASK 0xff00 48#define SPI_CFG1_PACKET_LOOP_MASK 0xff00
49#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000 49#define SPI_CFG1_PACKET_LENGTH_MASK 0x3ff0000
50 50
51#define SPI_CMD_ACT_OFFSET 0 51#define SPI_CMD_ACT BIT(0)
52#define SPI_CMD_RESUME_OFFSET 1 52#define SPI_CMD_RESUME BIT(1)
53#define SPI_CMD_CPHA_OFFSET 8
54#define SPI_CMD_CPOL_OFFSET 9
55#define SPI_CMD_TXMSBF_OFFSET 12
56#define SPI_CMD_RXMSBF_OFFSET 13
57#define SPI_CMD_RX_ENDIAN_OFFSET 14
58#define SPI_CMD_TX_ENDIAN_OFFSET 15
59
60#define SPI_CMD_RST BIT(2) 53#define SPI_CMD_RST BIT(2)
61#define SPI_CMD_PAUSE_EN BIT(4) 54#define SPI_CMD_PAUSE_EN BIT(4)
62#define SPI_CMD_DEASSERT BIT(5) 55#define SPI_CMD_DEASSERT BIT(5)
@@ -143,9 +136,14 @@ static void mtk_spi_config(struct mtk_spi *mdata,
143 reg_val = readl(mdata->base + SPI_CMD_REG); 136 reg_val = readl(mdata->base + SPI_CMD_REG);
144 137
145 /* set the mlsbx and mlsbtx */ 138 /* set the mlsbx and mlsbtx */
146 reg_val &= ~(SPI_CMD_TXMSBF | SPI_CMD_RXMSBF); 139 if (chip_config->tx_mlsb)
147 reg_val |= (chip_config->tx_mlsb << SPI_CMD_TXMSBF_OFFSET); 140 reg_val |= SPI_CMD_TXMSBF;
148 reg_val |= (chip_config->rx_mlsb << SPI_CMD_RXMSBF_OFFSET); 141 else
142 reg_val &= ~SPI_CMD_TXMSBF;
143 if (chip_config->rx_mlsb)
144 reg_val |= SPI_CMD_RXMSBF;
145 else
146 reg_val &= ~SPI_CMD_RXMSBF;
149 147
150 /* set the tx/rx endian */ 148 /* set the tx/rx endian */
151#ifdef __LITTLE_ENDIAN 149#ifdef __LITTLE_ENDIAN
@@ -201,9 +199,14 @@ static int mtk_spi_prepare_message(struct spi_master *master,
201 cpol = spi->mode & SPI_CPOL ? 1 : 0; 199 cpol = spi->mode & SPI_CPOL ? 1 : 0;
202 200
203 reg_val = readl(mdata->base + SPI_CMD_REG); 201 reg_val = readl(mdata->base + SPI_CMD_REG);
204 reg_val &= ~(SPI_CMD_CPHA | SPI_CMD_CPOL); 202 if (cpha)
205 reg_val |= (cpha << SPI_CMD_CPHA_OFFSET); 203 reg_val |= SPI_CMD_CPHA;
206 reg_val |= (cpol << SPI_CMD_CPOL_OFFSET); 204 else
205 reg_val &= ~SPI_CMD_CPHA;
206 if (cpol)
207 reg_val |= SPI_CMD_CPOL;
208 else
209 reg_val &= ~SPI_CMD_CPOL;
207 writel(reg_val, mdata->base + SPI_CMD_REG); 210 writel(reg_val, mdata->base + SPI_CMD_REG);
208 211
209 chip_config = spi->controller_data; 212 chip_config = spi->controller_data;
@@ -282,9 +285,9 @@ static void mtk_spi_enable_transfer(struct spi_master *master)
282 285
283 cmd = readl(mdata->base + SPI_CMD_REG); 286 cmd = readl(mdata->base + SPI_CMD_REG);
284 if (mdata->state == MTK_SPI_IDLE) 287 if (mdata->state == MTK_SPI_IDLE)
285 cmd |= 1 << SPI_CMD_ACT_OFFSET; 288 cmd |= SPI_CMD_ACT;
286 else 289 else
287 cmd |= 1 << SPI_CMD_RESUME_OFFSET; 290 cmd |= SPI_CMD_RESUME;
288 writel(cmd, mdata->base + SPI_CMD_REG); 291 writel(cmd, mdata->base + SPI_CMD_REG);
289} 292}
290 293