scsi: ufs-qcom: add QUniPro hardware support and power optimizations

New revisions of UFS host controller supports the new UniPro
hardware controller (referred as QUniPro). This patch adds
the support to enable this new UniPro controller hardware.

This change also adds power optimization for bus scaling feature,
as well as support for HS-G3 power mode.

Reviewed-by: Subhash Jadavani <subhashj@codeaurora.org>
Reviewed-by: Gilad Broner <gbroner@codeaurora.org>
Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org>
Reviewed-by: Hannes Reinecke <hare@suse.de>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>

1 files changed, 29 insertions, 2 deletions

diff --git a/drivers/scsi/ufs/ufs-qcom.h b/drivers/scsi/ufs/ufs-qcom.h
index 1b71a1b0be9f..36249b35f858 100644
--- a/drivers/scsi/ufs/ufs-qcom.h
+++ b/drivers/scsi/ufs/ufs-qcom.h
@@ -35,8 +35,8 @@
 
 #define UFS_QCOM_LIMIT_NUM_LANES_RX     2
 #define UFS_QCOM_LIMIT_NUM_LANES_TX     2
-#define UFS_QCOM_LIMIT_HSGEAR_RX        UFS_HS_G2
-#define UFS_QCOM_LIMIT_HSGEAR_TX        UFS_HS_G2
+#define UFS_QCOM_LIMIT_HSGEAR_RX        UFS_HS_G3
+#define UFS_QCOM_LIMIT_HSGEAR_TX        UFS_HS_G3
 #define UFS_QCOM_LIMIT_PWMGEAR_RX       UFS_PWM_G4
 #define UFS_QCOM_LIMIT_PWMGEAR_TX       UFS_PWM_G4
 #define UFS_QCOM_LIMIT_RX_PWR_PWM       SLOW_MODE
@@ -64,6 +64,11 @@ enum {
         UFS_TEST_BUS_CTRL_2                     = 0xF4,
         UFS_UNIPRO_CFG                          = 0xF8,
 
+        /*
+         * QCOM UFS host controller vendor specific registers
+         * added in HW Version 3.0.0
+         */
+        UFS_AH8_CFG                             = 0xFC,
 };
 
 /* QCOM UFS host controller vendor specific debug registers */
@@ -83,6 +88,11 @@ enum {
         UFS_UFS_DBG_RD_EDTL_RAM                 = 0x1900,
 };
 
+#define UFS_CNTLR_2_x_x_VEN_REGS_OFFSET(x)      (0x000 + x)
+#define UFS_CNTLR_3_x_x_VEN_REGS_OFFSET(x)      (0x400 + x)
+
+/* bit definitions for REG_UFS_CFG1 register */
+#define QUNIPRO_SEL     UFS_BIT(0)
 #define TEST_BUS_EN             BIT(18)
 #define TEST_BUS_SEL            GENMASK(22, 19)
 
@@ -131,6 +141,12 @@ enum ufs_qcom_phy_init_type {
         (UFS_QCOM_DBG_PRINT_REGS_EN | UFS_QCOM_DBG_PRINT_ICE_REGS_EN | \
          UFS_QCOM_DBG_PRINT_TEST_BUS_EN)
 
+/* QUniPro Vendor specific attributes */
+#define DME_VS_CORE_CLK_CTRL    0xD002
+/* bit and mask definitions for DME_VS_CORE_CLK_CTRL attribute */
+#define DME_VS_CORE_CLK_CTRL_CORE_CLK_DIV_EN_BIT                BIT(8)
+#define DME_VS_CORE_CLK_CTRL_MAX_CORE_CLK_1US_CYCLES_MASK       0xFF
+
 static inline void
 ufs_qcom_get_controller_revision(struct ufs_hba *hba,
                                  u8 *major, u16 *minor, u16 *step)
@@ -196,6 +212,12 @@ struct ufs_qcom_host {
          * controller supports the QUniPro mode.
          */
         #define UFS_QCOM_CAP_QUNIPRO    UFS_BIT(0)
+
+        /*
+         * Set this capability if host controller can retain the secure
+         * configuration even after UFS controller core power collapse.
+         */
+        #define UFS_QCOM_CAP_RETAIN_SEC_CFG_AFTER_PWR_COLLAPSE  UFS_BIT(1)
         u32 caps;
 
         struct phy *generic_phy;
@@ -208,7 +230,12 @@ struct ufs_qcom_host {
         struct clk *tx_l1_sync_clk;
         bool is_lane_clks_enabled;
 
+        void __iomem *dev_ref_clk_ctrl_mmio;
+        bool is_dev_ref_clk_enabled;
         struct ufs_hw_version hw_ver;
+
+        u32 dev_ref_clk_en_mask;
+
         /* Bitmask for enabling debug prints */
         u32 dbg_print_en;
         struct ufs_qcom_testbus testbus;