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authorLinus Torvalds <torvalds@linux-foundation.org>2015-06-24 22:21:02 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2015-06-24 22:21:02 -0400
commit93a4b1b9465d92e8be031b57166afa3d5611e142 (patch)
tree0ac95e35f24a754e01bdc40c56d71068eed49e4c /drivers/pinctrl/mediatek
parentd59b92f93df2d545d87d2341eb0705cc926ea22a (diff)
parentdaecdc66968f122fe53038ded8cb7abe93e0aa8c (diff)
Merge tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij: "Here is the bulk of pin control changes for the v4.2 series: Quite a lot of new SoC subdrivers and two new main drivers this time, apart from that business as usual. Details: Core functionality: - Enable exclusive pin ownership: it is possible to flag a pin controller so that GPIO and other functions cannot use a single pin simultaneously. New drivers: - NXP LPC18xx System Control Unit pin controller - Imagination Pistachio SoC pin controller New subdrivers: - Freescale i.MX7d SoC - Intel Sunrisepoint-H PCH - Renesas PFC R8A7793 - Renesas PFC R8A7794 - Mediatek MT6397, MT8127 - SiRF Atlas 7 - Allwinner A33 - Qualcomm MSM8660 - Marvell Armada 395 - Rockchip RK3368 Cleanups: - A big cleanup of the Marvell MVEBU driver rectifying it to correspond to reality - Drop platform device probing from the SH PFC driver, we are now a DT only shop for SuperH - Drop obsolte multi-platform check for SH PFC - Various janitorial: constification, grammar etc Improvements: - The AT91 GPIO portions now supports the set_multiple() feature - Split out SPI pins on the Xilinx Zynq - Support DTs without specific function nodes in the i.MX driver" * tag 'pinctrl-v4.2-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: rockchip: add support for the rk3368 pinctrl: rockchip: generalize perpin driver-strength setting pinctrl: sh-pfc: r8a7794: add SDHI pin groups pinctrl: sh-pfc: r8a7794: add MMCIF pin groups pinctrl: sh-pfc: add R8A7794 PFC support pinctrl: make pinctrl_register() return proper error code pinctrl: mvebu: armada-39x: add support for Armada 395 variant pinctrl: mvebu: armada-39x: add missing SATA functions pinctrl: mvebu: armada-39x: add missing PCIe functions pinctrl: mvebu: armada-38x: add ptp functions pinctrl: mvebu: armada-38x: add ua1 functions pinctrl: mvebu: armada-38x: add nand functions pinctrl: mvebu: armada-38x: add sata functions pinctrl: mvebu: armada-xp: add dram functions pinctrl: mvebu: armada-xp: add nand rb function pinctrl: mvebu: armada-xp: add spi1 function pinctrl: mvebu: armada-39x: normalize ref clock naming pinctrl: mvebu: armada-xp: rename spi to spi0 pinctrl: mvebu: armada-370: align spi1 clock pin naming pinctrl: mvebu: armada-370: align VDD cpu-pd pin naming with datasheet ...
Diffstat (limited to 'drivers/pinctrl/mediatek')
-rw-r--r--drivers/pinctrl/mediatek/Kconfig13
-rw-r--r--drivers/pinctrl/mediatek/Makefile2
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt6397.c77
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8127.c358
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8135.c13
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mt8173.c377
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.c161
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-common.h75
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h424
-rw-r--r--drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h1318
10 files changed, 2558 insertions, 260 deletions
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 6b3551cad111..02f6f92df86c 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -15,6 +15,12 @@ config PINCTRL_MT8135
15 default MACH_MT8135 15 default MACH_MT8135
16 select PINCTRL_MTK_COMMON 16 select PINCTRL_MTK_COMMON
17 17
18config PINCTRL_MT8127
19 bool "Mediatek MT8127 pin control" if COMPILE_TEST && !MACH_MT8127
20 depends on OF
21 default MACH_MT8127
22 select PINCTRL_MTK_COMMON
23
18# For ARMv8 SoCs 24# For ARMv8 SoCs
19config PINCTRL_MT8173 25config PINCTRL_MT8173
20 bool "Mediatek MT8173 pin control" 26 bool "Mediatek MT8173 pin control"
@@ -23,4 +29,11 @@ config PINCTRL_MT8173
23 default ARM64 && ARCH_MEDIATEK 29 default ARM64 && ARCH_MEDIATEK
24 select PINCTRL_MTK_COMMON 30 select PINCTRL_MTK_COMMON
25 31
32# For PMIC
33config PINCTRL_MT6397
34 bool "Mediatek MT6397 pin control" if COMPILE_TEST && !MFD_MT6397
35 depends on OF
36 default MFD_MT6397
37 select PINCTRL_MTK_COMMON
38
26endif 39endif
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index d8606a2179cf..eb923d64d387 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,4 +3,6 @@ obj-$(CONFIG_PINCTRL_MTK_COMMON) += pinctrl-mtk-common.o
3 3
4# SoC Drivers 4# SoC Drivers
5obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o 5obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
6obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
6obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o 7obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
8obj-$(CONFIG_PINCTRL_MT6397) += pinctrl-mt6397.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6397.c b/drivers/pinctrl/mediatek/pinctrl-mt6397.c
new file mode 100644
index 000000000000..f9751ae28e32
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6397.c
@@ -0,0 +1,77 @@
1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/module.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinconf-generic.h>
21#include <linux/mfd/mt6397/core.h>
22
23#include "pinctrl-mtk-common.h"
24#include "pinctrl-mtk-mt6397.h"
25
26#define MT6397_PIN_REG_BASE 0xc000
27
28static const struct mtk_pinctrl_devdata mt6397_pinctrl_data = {
29 .pins = mtk_pins_mt6397,
30 .npins = ARRAY_SIZE(mtk_pins_mt6397),
31 .dir_offset = (MT6397_PIN_REG_BASE + 0x000),
32 .ies_offset = MTK_PINCTRL_NOT_SUPPORT,
33 .smt_offset = MTK_PINCTRL_NOT_SUPPORT,
34 .pullen_offset = (MT6397_PIN_REG_BASE + 0x020),
35 .pullsel_offset = (MT6397_PIN_REG_BASE + 0x040),
36 .dout_offset = (MT6397_PIN_REG_BASE + 0x080),
37 .din_offset = (MT6397_PIN_REG_BASE + 0x0a0),
38 .pinmux_offset = (MT6397_PIN_REG_BASE + 0x0c0),
39 .type1_start = 41,
40 .type1_end = 41,
41 .port_shf = 3,
42 .port_mask = 0x3,
43 .port_align = 2,
44};
45
46static int mt6397_pinctrl_probe(struct platform_device *pdev)
47{
48 struct mt6397_chip *mt6397;
49
50 mt6397 = dev_get_drvdata(pdev->dev.parent);
51 return mtk_pctrl_init(pdev, &mt6397_pinctrl_data, mt6397->regmap);
52}
53
54static const struct of_device_id mt6397_pctrl_match[] = {
55 { .compatible = "mediatek,mt6397-pinctrl", },
56 { }
57};
58MODULE_DEVICE_TABLE(of, mt6397_pctrl_match);
59
60static struct platform_driver mtk_pinctrl_driver = {
61 .probe = mt6397_pinctrl_probe,
62 .driver = {
63 .name = "mediatek-mt6397-pinctrl",
64 .of_match_table = mt6397_pctrl_match,
65 },
66};
67
68static int __init mtk_pinctrl_init(void)
69{
70 return platform_driver_register(&mtk_pinctrl_driver);
71}
72
73module_init(mtk_pinctrl_init);
74
75MODULE_LICENSE("GPL v2");
76MODULE_DESCRIPTION("MediaTek MT6397 Pinctrl Driver");
77MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8127.c b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
new file mode 100644
index 000000000000..b317b0b664ea
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8127.c
@@ -0,0 +1,358 @@
1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
4 * Yingjoe Chen <yingjoe.chen@mediatek.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/module.h>
17#include <linux/platform_device.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/pinctrl.h>
21#include <linux/regmap.h>
22#include <dt-bindings/pinctrl/mt65xx.h>
23
24#include "pinctrl-mtk-common.h"
25#include "pinctrl-mtk-mt8127.h"
26
27static const struct mtk_drv_group_desc mt8127_drv_grp[] = {
28 /* 0E4E8SR 4/8/12/16 */
29 MTK_DRV_GRP(4, 16, 1, 2, 4),
30 /* 0E2E4SR 2/4/6/8 */
31 MTK_DRV_GRP(2, 8, 1, 2, 2),
32 /* E8E4E2 2/4/6/8/10/12/14/16 */
33 MTK_DRV_GRP(2, 16, 0, 2, 2)
34};
35
36static const struct mtk_pin_drv_grp mt8127_pin_drv[] = {
37 MTK_PIN_DRV_GRP(0, 0xb00, 0, 1),
38 MTK_PIN_DRV_GRP(1, 0xb00, 0, 1),
39 MTK_PIN_DRV_GRP(2, 0xb00, 0, 1),
40 MTK_PIN_DRV_GRP(3, 0xb00, 0, 1),
41 MTK_PIN_DRV_GRP(4, 0xb00, 0, 1),
42 MTK_PIN_DRV_GRP(5, 0xb00, 0, 1),
43 MTK_PIN_DRV_GRP(6, 0xb00, 0, 1),
44 MTK_PIN_DRV_GRP(7, 0xb00, 12, 1),
45 MTK_PIN_DRV_GRP(8, 0xb00, 12, 1),
46 MTK_PIN_DRV_GRP(9, 0xb00, 12, 1),
47 MTK_PIN_DRV_GRP(10, 0xb00, 8, 1),
48 MTK_PIN_DRV_GRP(11, 0xb00, 8, 1),
49 MTK_PIN_DRV_GRP(12, 0xb00, 8, 1),
50 MTK_PIN_DRV_GRP(13, 0xb00, 8, 1),
51 MTK_PIN_DRV_GRP(14, 0xb10, 4, 0),
52 MTK_PIN_DRV_GRP(15, 0xb10, 4, 0),
53 MTK_PIN_DRV_GRP(16, 0xb10, 4, 0),
54 MTK_PIN_DRV_GRP(17, 0xb10, 4, 0),
55 MTK_PIN_DRV_GRP(18, 0xb10, 8, 0),
56 MTK_PIN_DRV_GRP(19, 0xb10, 8, 0),
57 MTK_PIN_DRV_GRP(20, 0xb10, 8, 0),
58 MTK_PIN_DRV_GRP(21, 0xb10, 8, 0),
59 MTK_PIN_DRV_GRP(22, 0xb20, 0, 0),
60 MTK_PIN_DRV_GRP(23, 0xb20, 0, 0),
61 MTK_PIN_DRV_GRP(24, 0xb20, 0, 0),
62 MTK_PIN_DRV_GRP(25, 0xb20, 0, 0),
63 MTK_PIN_DRV_GRP(26, 0xb20, 0, 0),
64 MTK_PIN_DRV_GRP(27, 0xb20, 4, 0),
65 MTK_PIN_DRV_GRP(28, 0xb20, 4, 0),
66 MTK_PIN_DRV_GRP(29, 0xb20, 4, 0),
67 MTK_PIN_DRV_GRP(30, 0xb20, 4, 0),
68 MTK_PIN_DRV_GRP(31, 0xb20, 4, 0),
69 MTK_PIN_DRV_GRP(32, 0xb20, 4, 0),
70 MTK_PIN_DRV_GRP(33, 0xb30, 4, 1),
71 MTK_PIN_DRV_GRP(34, 0xb30, 8, 1),
72 MTK_PIN_DRV_GRP(35, 0xb30, 8, 1),
73 MTK_PIN_DRV_GRP(36, 0xb30, 8, 1),
74 MTK_PIN_DRV_GRP(37, 0xb30, 8, 1),
75 MTK_PIN_DRV_GRP(38, 0xb30, 8, 1),
76 MTK_PIN_DRV_GRP(39, 0xb30, 12, 1),
77 MTK_PIN_DRV_GRP(40, 0xb30, 12, 1),
78 MTK_PIN_DRV_GRP(41, 0xb30, 12, 1),
79 MTK_PIN_DRV_GRP(42, 0xb30, 12, 1),
80 MTK_PIN_DRV_GRP(43, 0xb40, 12, 0),
81 MTK_PIN_DRV_GRP(44, 0xb40, 12, 0),
82 MTK_PIN_DRV_GRP(45, 0xb40, 12, 0),
83 MTK_PIN_DRV_GRP(46, 0xb50, 0, 2),
84 MTK_PIN_DRV_GRP(47, 0xb50, 0, 2),
85 MTK_PIN_DRV_GRP(48, 0xb50, 0, 2),
86 MTK_PIN_DRV_GRP(49, 0xb50, 0, 2),
87 MTK_PIN_DRV_GRP(50, 0xb70, 0, 1),
88 MTK_PIN_DRV_GRP(51, 0xb70, 0, 1),
89 MTK_PIN_DRV_GRP(52, 0xb70, 0, 1),
90 MTK_PIN_DRV_GRP(53, 0xb50, 12, 1),
91 MTK_PIN_DRV_GRP(54, 0xb50, 12, 1),
92 MTK_PIN_DRV_GRP(55, 0xb50, 12, 1),
93 MTK_PIN_DRV_GRP(56, 0xb50, 12, 1),
94 MTK_PIN_DRV_GRP(59, 0xb40, 4, 1),
95 MTK_PIN_DRV_GRP(60, 0xb40, 0, 1),
96 MTK_PIN_DRV_GRP(61, 0xb40, 0, 1),
97 MTK_PIN_DRV_GRP(62, 0xb40, 0, 1),
98 MTK_PIN_DRV_GRP(63, 0xb40, 4, 1),
99 MTK_PIN_DRV_GRP(64, 0xb40, 4, 1),
100 MTK_PIN_DRV_GRP(65, 0xb40, 4, 1),
101 MTK_PIN_DRV_GRP(66, 0xb40, 8, 1),
102 MTK_PIN_DRV_GRP(67, 0xb40, 8, 1),
103 MTK_PIN_DRV_GRP(68, 0xb40, 8, 1),
104 MTK_PIN_DRV_GRP(69, 0xb40, 8, 1),
105 MTK_PIN_DRV_GRP(70, 0xb40, 8, 1),
106 MTK_PIN_DRV_GRP(71, 0xb40, 8, 1),
107 MTK_PIN_DRV_GRP(72, 0xb50, 4, 1),
108 MTK_PIN_DRV_GRP(73, 0xb50, 4, 1),
109 MTK_PIN_DRV_GRP(74, 0xb50, 4, 1),
110 MTK_PIN_DRV_GRP(79, 0xb50, 8, 1),
111 MTK_PIN_DRV_GRP(80, 0xb50, 8, 1),
112 MTK_PIN_DRV_GRP(81, 0xb50, 8, 1),
113 MTK_PIN_DRV_GRP(82, 0xb50, 8, 1),
114 MTK_PIN_DRV_GRP(83, 0xb50, 8, 1),
115 MTK_PIN_DRV_GRP(84, 0xb50, 8, 1),
116 MTK_PIN_DRV_GRP(85, 0xce0, 0, 2),
117 MTK_PIN_DRV_GRP(86, 0xcd0, 0, 2),
118 MTK_PIN_DRV_GRP(87, 0xcf0, 0, 2),
119 MTK_PIN_DRV_GRP(88, 0xcf0, 0, 2),
120 MTK_PIN_DRV_GRP(89, 0xcf0, 0, 2),
121 MTK_PIN_DRV_GRP(90, 0xcf0, 0, 2),
122 MTK_PIN_DRV_GRP(117, 0xb60, 12, 1),
123 MTK_PIN_DRV_GRP(118, 0xb60, 12, 1),
124 MTK_PIN_DRV_GRP(119, 0xb60, 12, 1),
125 MTK_PIN_DRV_GRP(120, 0xb60, 12, 1),
126 MTK_PIN_DRV_GRP(121, 0xc80, 0, 2),
127 MTK_PIN_DRV_GRP(122, 0xc70, 0, 2),
128 MTK_PIN_DRV_GRP(123, 0xc90, 0, 2),
129 MTK_PIN_DRV_GRP(124, 0xc90, 0, 2),
130 MTK_PIN_DRV_GRP(125, 0xc90, 0, 2),
131 MTK_PIN_DRV_GRP(126, 0xc90, 0, 2),
132 MTK_PIN_DRV_GRP(127, 0xc20, 0, 2),
133 MTK_PIN_DRV_GRP(128, 0xc20, 0, 2),
134 MTK_PIN_DRV_GRP(129, 0xc20, 0, 2),
135 MTK_PIN_DRV_GRP(130, 0xc20, 0, 2),
136 MTK_PIN_DRV_GRP(131, 0xc20, 0, 2),
137 MTK_PIN_DRV_GRP(132, 0xc10, 0, 2),
138 MTK_PIN_DRV_GRP(133, 0xc00, 0, 2),
139 MTK_PIN_DRV_GRP(134, 0xc20, 0, 2),
140 MTK_PIN_DRV_GRP(135, 0xc20, 0, 2),
141 MTK_PIN_DRV_GRP(136, 0xc20, 0, 2),
142 MTK_PIN_DRV_GRP(137, 0xc20, 0, 2),
143 MTK_PIN_DRV_GRP(142, 0xb50, 0, 2),
144};
145
146static const struct mtk_pin_spec_pupd_set_samereg mt8127_spec_pupd[] = {
147 MTK_PIN_PUPD_SPEC_SR(33, 0xd90, 2, 0, 1), /* KPROW0 */
148 MTK_PIN_PUPD_SPEC_SR(34, 0xd90, 6, 4, 5), /* KPROW1 */
149 MTK_PIN_PUPD_SPEC_SR(35, 0xd90, 10, 8, 9), /* KPROW2 */
150 MTK_PIN_PUPD_SPEC_SR(36, 0xda0, 2, 0, 1), /* KPCOL0 */
151 MTK_PIN_PUPD_SPEC_SR(37, 0xda0, 6, 4, 5), /* KPCOL1 */
152 MTK_PIN_PUPD_SPEC_SR(38, 0xda0, 10, 8, 9), /* KPCOL2 */
153 MTK_PIN_PUPD_SPEC_SR(46, 0xdb0, 2, 0, 1), /* EINT14 */
154 MTK_PIN_PUPD_SPEC_SR(47, 0xdb0, 6, 4, 5), /* EINT15 */
155 MTK_PIN_PUPD_SPEC_SR(48, 0xdb0, 10, 8, 9), /* EINT16 */
156 MTK_PIN_PUPD_SPEC_SR(49, 0xdb0, 14, 12, 13), /* EINT17 */
157 MTK_PIN_PUPD_SPEC_SR(85, 0xce0, 8, 10, 9), /* MSDC2_CMD */
158 MTK_PIN_PUPD_SPEC_SR(86, 0xcd0, 8, 10, 9), /* MSDC2_CLK */
159 MTK_PIN_PUPD_SPEC_SR(87, 0xd00, 0, 2, 1), /* MSDC2_DAT0 */
160 MTK_PIN_PUPD_SPEC_SR(88, 0xd00, 4, 6, 5), /* MSDC2_DAT1 */
161 MTK_PIN_PUPD_SPEC_SR(89, 0xd00, 8, 10, 9), /* MSDC2_DAT2 */
162 MTK_PIN_PUPD_SPEC_SR(90, 0xd00, 12, 14, 13), /* MSDC2_DAT3 */
163 MTK_PIN_PUPD_SPEC_SR(121, 0xc80, 8, 10, 9), /* MSDC1_CMD */
164 MTK_PIN_PUPD_SPEC_SR(122, 0xc70, 8, 10, 9), /* MSDC1_CLK */
165 MTK_PIN_PUPD_SPEC_SR(123, 0xca0, 0, 2, 1), /* MSDC1_DAT0 */
166 MTK_PIN_PUPD_SPEC_SR(124, 0xca0, 4, 6, 5), /* MSDC1_DAT1 */
167 MTK_PIN_PUPD_SPEC_SR(125, 0xca0, 8, 10, 9), /* MSDC1_DAT2 */
168 MTK_PIN_PUPD_SPEC_SR(126, 0xca0, 12, 14, 13), /* MSDC1_DAT3 */
169 MTK_PIN_PUPD_SPEC_SR(127, 0xc40, 12, 14, 13), /* MSDC0_DAT7 */
170 MTK_PIN_PUPD_SPEC_SR(128, 0xc40, 8, 10, 9), /* MSDC0_DAT6 */
171 MTK_PIN_PUPD_SPEC_SR(129, 0xc40, 4, 6, 5), /* MSDC0_DAT5 */
172 MTK_PIN_PUPD_SPEC_SR(130, 0xc40, 0, 2, 1), /* MSDC0_DAT4 */
173 MTK_PIN_PUPD_SPEC_SR(131, 0xc50, 0, 2, 1), /* MSDC0_RSTB */
174 MTK_PIN_PUPD_SPEC_SR(132, 0xc10, 8, 10, 9), /* MSDC0_CMD */
175 MTK_PIN_PUPD_SPEC_SR(133, 0xc00, 8, 10, 9), /* MSDC0_CLK */
176 MTK_PIN_PUPD_SPEC_SR(134, 0xc30, 12, 14, 13), /* MSDC0_DAT3 */
177 MTK_PIN_PUPD_SPEC_SR(135, 0xc30, 8, 10, 9), /* MSDC0_DAT2 */
178 MTK_PIN_PUPD_SPEC_SR(136, 0xc30, 4, 6, 5), /* MSDC0_DAT1 */
179 MTK_PIN_PUPD_SPEC_SR(137, 0xc30, 0, 2, 1), /* MSDC0_DAT0 */
180 MTK_PIN_PUPD_SPEC_SR(142, 0xdc0, 2, 0, 1), /* EINT21 */
181};
182
183static int mt8127_spec_pull_set(struct regmap *regmap, unsigned int pin,
184 unsigned char align, bool isup, unsigned int r1r0)
185{
186 return mtk_pctrl_spec_pull_set_samereg(regmap, mt8127_spec_pupd,
187 ARRAY_SIZE(mt8127_spec_pupd), pin, align, isup, r1r0);
188}
189
190static const struct mtk_pin_ies_smt_set mt8127_ies_set[] = {
191 MTK_PIN_IES_SMT_SPEC(0, 9, 0x900, 0),
192 MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 1),
193 MTK_PIN_IES_SMT_SPEC(14, 28, 0x900, 2),
194 MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
195 MTK_PIN_IES_SMT_SPEC(33, 33, 0x910, 11),
196 MTK_PIN_IES_SMT_SPEC(34, 38, 0x900, 10),
197 MTK_PIN_IES_SMT_SPEC(39, 42, 0x900, 11),
198 MTK_PIN_IES_SMT_SPEC(43, 45, 0x900, 12),
199 MTK_PIN_IES_SMT_SPEC(46, 49, 0x900, 13),
200 MTK_PIN_IES_SMT_SPEC(50, 52, 0x910, 10),
201 MTK_PIN_IES_SMT_SPEC(53, 56, 0x900, 14),
202 MTK_PIN_IES_SMT_SPEC(57, 58, 0x910, 0),
203 MTK_PIN_IES_SMT_SPEC(59, 65, 0x910, 2),
204 MTK_PIN_IES_SMT_SPEC(66, 71, 0x910, 3),
205 MTK_PIN_IES_SMT_SPEC(72, 74, 0x910, 4),
206 MTK_PIN_IES_SMT_SPEC(75, 76, 0x900, 15),
207 MTK_PIN_IES_SMT_SPEC(77, 78, 0x910, 1),
208 MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 5),
209 MTK_PIN_IES_SMT_SPEC(83, 84, 0x910, 6),
210 MTK_PIN_IES_SMT_SPEC(117, 120, 0x910, 7),
211 MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 4),
212 MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 4),
213 MTK_PIN_IES_SMT_SPEC(123, 126, 0xc90, 4),
214 MTK_PIN_IES_SMT_SPEC(127, 131, 0xc20, 4),
215 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 4),
216 MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 4),
217 MTK_PIN_IES_SMT_SPEC(134, 137, 0xc20, 4),
218 MTK_PIN_IES_SMT_SPEC(138, 141, 0x910, 9),
219 MTK_PIN_IES_SMT_SPEC(142, 142, 0x900, 13),
220};
221
222static const struct mtk_pin_ies_smt_set mt8127_smt_set[] = {
223 MTK_PIN_IES_SMT_SPEC(0, 9, 0x920, 0),
224 MTK_PIN_IES_SMT_SPEC(10, 13, 0x920, 1),
225 MTK_PIN_IES_SMT_SPEC(14, 28, 0x920, 2),
226 MTK_PIN_IES_SMT_SPEC(29, 32, 0x920, 3),
227 MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 11),
228 MTK_PIN_IES_SMT_SPEC(34, 38, 0x920, 10),
229 MTK_PIN_IES_SMT_SPEC(39, 42, 0x920, 11),
230 MTK_PIN_IES_SMT_SPEC(43, 45, 0x920, 12),
231 MTK_PIN_IES_SMT_SPEC(46, 49, 0x920, 13),
232 MTK_PIN_IES_SMT_SPEC(50, 52, 0x930, 10),
233 MTK_PIN_IES_SMT_SPEC(53, 56, 0x920, 14),
234 MTK_PIN_IES_SMT_SPEC(57, 58, 0x930, 0),
235 MTK_PIN_IES_SMT_SPEC(59, 65, 0x930, 2),
236 MTK_PIN_IES_SMT_SPEC(66, 71, 0x930, 3),
237 MTK_PIN_IES_SMT_SPEC(72, 74, 0x930, 4),
238 MTK_PIN_IES_SMT_SPEC(75, 76, 0x920, 15),
239 MTK_PIN_IES_SMT_SPEC(77, 78, 0x930, 1),
240 MTK_PIN_IES_SMT_SPEC(79, 82, 0x930, 5),
241 MTK_PIN_IES_SMT_SPEC(83, 84, 0x930, 6),
242 MTK_PIN_IES_SMT_SPEC(85, 85, 0xce0, 11),
243 MTK_PIN_IES_SMT_SPEC(86, 86, 0xcd0, 11),
244 MTK_PIN_IES_SMT_SPEC(87, 87, 0xd00, 3),
245 MTK_PIN_IES_SMT_SPEC(88, 88, 0xd00, 7),
246 MTK_PIN_IES_SMT_SPEC(89, 89, 0xd00, 11),
247 MTK_PIN_IES_SMT_SPEC(90, 90, 0xd00, 15),
248 MTK_PIN_IES_SMT_SPEC(117, 120, 0x930, 7),
249 MTK_PIN_IES_SMT_SPEC(121, 121, 0xc80, 11),
250 MTK_PIN_IES_SMT_SPEC(122, 122, 0xc70, 11),
251 MTK_PIN_IES_SMT_SPEC(123, 123, 0xca0, 3),
252 MTK_PIN_IES_SMT_SPEC(124, 124, 0xca0, 7),
253 MTK_PIN_IES_SMT_SPEC(125, 125, 0xca0, 11),
254 MTK_PIN_IES_SMT_SPEC(126, 126, 0xca0, 15),
255 MTK_PIN_IES_SMT_SPEC(127, 127, 0xc40, 15),
256 MTK_PIN_IES_SMT_SPEC(128, 128, 0xc40, 11),
257 MTK_PIN_IES_SMT_SPEC(129, 129, 0xc40, 7),
258 MTK_PIN_IES_SMT_SPEC(130, 130, 0xc40, 3),
259 MTK_PIN_IES_SMT_SPEC(131, 131, 0xc50, 3),
260 MTK_PIN_IES_SMT_SPEC(132, 132, 0xc10, 11),
261 MTK_PIN_IES_SMT_SPEC(133, 133, 0xc00, 11),
262 MTK_PIN_IES_SMT_SPEC(134, 134, 0xc30, 15),
263 MTK_PIN_IES_SMT_SPEC(135, 135, 0xc30, 11),
264 MTK_PIN_IES_SMT_SPEC(136, 136, 0xc30, 7),
265 MTK_PIN_IES_SMT_SPEC(137, 137, 0xc30, 3),
266 MTK_PIN_IES_SMT_SPEC(138, 141, 0x930, 9),
267 MTK_PIN_IES_SMT_SPEC(142, 142, 0x920, 13),
268};
269
270static int mt8127_ies_smt_set(struct regmap *regmap, unsigned int pin,
271 unsigned char align, int value, enum pin_config_param arg)
272{
273 if (arg == PIN_CONFIG_INPUT_ENABLE)
274 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_ies_set,
275 ARRAY_SIZE(mt8127_ies_set), pin, align, value);
276 else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
277 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8127_smt_set,
278 ARRAY_SIZE(mt8127_smt_set), pin, align, value);
279 return -EINVAL;
280}
281
282
283static const struct mtk_pinctrl_devdata mt8127_pinctrl_data = {
284 .pins = mtk_pins_mt8127,
285 .npins = ARRAY_SIZE(mtk_pins_mt8127),
286 .grp_desc = mt8127_drv_grp,
287 .n_grp_cls = ARRAY_SIZE(mt8127_drv_grp),
288 .pin_drv_grp = mt8127_pin_drv,
289 .n_pin_drv_grps = ARRAY_SIZE(mt8127_pin_drv),
290 .spec_pull_set = mt8127_spec_pull_set,
291 .spec_ies_smt_set = mt8127_ies_smt_set,
292 .dir_offset = 0x0000,
293 .pullen_offset = 0x0100,
294 .pullsel_offset = 0x0200,
295 .dout_offset = 0x0400,
296 .din_offset = 0x0500,
297 .pinmux_offset = 0x0600,
298 .type1_start = 143,
299 .type1_end = 143,
300 .port_shf = 4,
301 .port_mask = 0xf,
302 .port_align = 4,
303 .eint_offsets = {
304 .name = "mt8127_eint",
305 .stat = 0x000,
306 .ack = 0x040,
307 .mask = 0x080,
308 .mask_set = 0x0c0,
309 .mask_clr = 0x100,
310 .sens = 0x140,
311 .sens_set = 0x180,
312 .sens_clr = 0x1c0,
313 .soft = 0x200,
314 .soft_set = 0x240,
315 .soft_clr = 0x280,
316 .pol = 0x300,
317 .pol_set = 0x340,
318 .pol_clr = 0x380,
319 .dom_en = 0x400,
320 .dbnc_ctrl = 0x500,
321 .dbnc_set = 0x600,
322 .dbnc_clr = 0x700,
323 .port_mask = 7,
324 .ports = 6,
325 },
326 .ap_num = 143,
327 .db_cnt = 16,
328};
329
330static int mt8127_pinctrl_probe(struct platform_device *pdev)
331{
332 return mtk_pctrl_init(pdev, &mt8127_pinctrl_data, NULL);
333}
334
335static const struct of_device_id mt8127_pctrl_match[] = {
336 { .compatible = "mediatek,mt8127-pinctrl", },
337 { }
338};
339MODULE_DEVICE_TABLE(of, mt8127_pctrl_match);
340
341static struct platform_driver mtk_pinctrl_driver = {
342 .probe = mt8127_pinctrl_probe,
343 .driver = {
344 .name = "mediatek-mt8127-pinctrl",
345 .of_match_table = mt8127_pctrl_match,
346 },
347};
348
349static int __init mtk_pinctrl_init(void)
350{
351 return platform_driver_register(&mtk_pinctrl_driver);
352}
353
354module_init(mtk_pinctrl_init);
355
356MODULE_LICENSE("GPL v2");
357MODULE_DESCRIPTION("MediaTek MT8127 Pinctrl Driver");
358MODULE_AUTHOR("Yingjoe Chen <yingjoe.chen@mediatek.com>");
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8135.c b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
index f1e1e187ce96..404f1178511d 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8135.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8135.c
@@ -32,12 +32,12 @@
32#define R1_BASE2 0x250 32#define R1_BASE2 0x250
33 33
34struct mtk_spec_pull_set { 34struct mtk_spec_pull_set {
35 unsigned int pin; 35 unsigned char pin;
36 unsigned int pupd_offset;
37 unsigned char pupd_bit; 36 unsigned char pupd_bit;
38 unsigned int r0_offset; 37 unsigned short pupd_offset;
38 unsigned short r0_offset;
39 unsigned short r1_offset;
39 unsigned char r0_bit; 40 unsigned char r0_bit;
40 unsigned int r1_offset;
41 unsigned char r1_bit; 41 unsigned char r1_bit;
42}; 42};
43 43
@@ -305,7 +305,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
305 .pullen_offset = 0x0200, 305 .pullen_offset = 0x0200,
306 .smt_offset = 0x0300, 306 .smt_offset = 0x0300,
307 .pullsel_offset = 0x0400, 307 .pullsel_offset = 0x0400,
308 .invser_offset = 0x0600,
309 .dout_offset = 0x0800, 308 .dout_offset = 0x0800,
310 .din_offset = 0x0A00, 309 .din_offset = 0x0A00,
311 .pinmux_offset = 0x0C00, 310 .pinmux_offset = 0x0C00,
@@ -314,7 +313,6 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
314 .port_shf = 4, 313 .port_shf = 4,
315 .port_mask = 0xf, 314 .port_mask = 0xf,
316 .port_align = 4, 315 .port_align = 4,
317 .chip_type = MTK_CHIP_TYPE_BASE,
318 .eint_offsets = { 316 .eint_offsets = {
319 .name = "mt8135_eint", 317 .name = "mt8135_eint",
320 .stat = 0x000, 318 .stat = 0x000,
@@ -344,7 +342,7 @@ static const struct mtk_pinctrl_devdata mt8135_pinctrl_data = {
344 342
345static int mt8135_pinctrl_probe(struct platform_device *pdev) 343static int mt8135_pinctrl_probe(struct platform_device *pdev)
346{ 344{
347 return mtk_pctrl_init(pdev, &mt8135_pinctrl_data); 345 return mtk_pctrl_init(pdev, &mt8135_pinctrl_data, NULL);
348} 346}
349 347
350static const struct of_device_id mt8135_pctrl_match[] = { 348static const struct of_device_id mt8135_pctrl_match[] = {
@@ -359,7 +357,6 @@ static struct platform_driver mtk_pinctrl_driver = {
359 .probe = mt8135_pinctrl_probe, 357 .probe = mt8135_pinctrl_probe,
360 .driver = { 358 .driver = {
361 .name = "mediatek-mt8135-pinctrl", 359 .name = "mediatek-mt8135-pinctrl",
362 .owner = THIS_MODULE,
363 .of_match_table = mt8135_pctrl_match, 360 .of_match_table = mt8135_pctrl_match,
364 }, 361 },
365}; 362};
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8173.c b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
index 412ea84836a1..d0c811d5f07b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8173.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8173.c
@@ -18,6 +18,7 @@
18#include <linux/of_device.h> 18#include <linux/of_device.h>
19#include <linux/pinctrl/pinctrl.h> 19#include <linux/pinctrl/pinctrl.h>
20#include <linux/regmap.h> 20#include <linux/regmap.h>
21#include <linux/pinctrl/pinconf-generic.h>
21#include <dt-bindings/pinctrl/mt65xx.h> 22#include <dt-bindings/pinctrl/mt65xx.h>
22 23
23#include "pinctrl-mtk-common.h" 24#include "pinctrl-mtk-common.h"
@@ -25,228 +26,172 @@
25 26
26#define DRV_BASE 0xb00 27#define DRV_BASE 0xb00
27 28
28/** 29static const struct mtk_pin_spec_pupd_set_samereg mt8173_spec_pupd[] = {
29 * struct mtk_pin_ies_smt_set - For special pins' ies and smt setting. 30 MTK_PIN_PUPD_SPEC_SR(119, 0xe00, 2, 1, 0), /* KROW0 */
30 * @start: The start pin number of those special pins. 31 MTK_PIN_PUPD_SPEC_SR(120, 0xe00, 6, 5, 4), /* KROW1 */
31 * @end: The end pin number of those special pins. 32 MTK_PIN_PUPD_SPEC_SR(121, 0xe00, 10, 9, 8), /* KROW2 */
32 * @offset: The offset of special setting register. 33 MTK_PIN_PUPD_SPEC_SR(122, 0xe10, 2, 1, 0), /* KCOL0 */
33 * @bit: The bit of special setting register. 34 MTK_PIN_PUPD_SPEC_SR(123, 0xe10, 6, 5, 4), /* KCOL1 */
34 */ 35 MTK_PIN_PUPD_SPEC_SR(124, 0xe10, 10, 9, 8), /* KCOL2 */
35struct mtk_pin_ies_smt_set { 36
36 unsigned int start; 37 MTK_PIN_PUPD_SPEC_SR(67, 0xd10, 2, 1, 0), /* ms0 DS */
37 unsigned int end; 38 MTK_PIN_PUPD_SPEC_SR(68, 0xd00, 2, 1, 0), /* ms0 RST */
38 unsigned int offset; 39 MTK_PIN_PUPD_SPEC_SR(66, 0xc10, 2, 1, 0), /* ms0 cmd */
39 unsigned char bit; 40 MTK_PIN_PUPD_SPEC_SR(65, 0xc00, 2, 1, 0), /* ms0 clk */
41 MTK_PIN_PUPD_SPEC_SR(57, 0xc20, 2, 1, 0), /* ms0 data0 */
42 MTK_PIN_PUPD_SPEC_SR(58, 0xc20, 2, 1, 0), /* ms0 data1 */
43 MTK_PIN_PUPD_SPEC_SR(59, 0xc20, 2, 1, 0), /* ms0 data2 */
44 MTK_PIN_PUPD_SPEC_SR(60, 0xc20, 2, 1, 0), /* ms0 data3 */
45 MTK_PIN_PUPD_SPEC_SR(61, 0xc20, 2, 1, 0), /* ms0 data4 */
46 MTK_PIN_PUPD_SPEC_SR(62, 0xc20, 2, 1, 0), /* ms0 data5 */
47 MTK_PIN_PUPD_SPEC_SR(63, 0xc20, 2, 1, 0), /* ms0 data6 */
48 MTK_PIN_PUPD_SPEC_SR(64, 0xc20, 2, 1, 0), /* ms0 data7 */
49
50 MTK_PIN_PUPD_SPEC_SR(78, 0xc50, 2, 1, 0), /* ms1 cmd */
51 MTK_PIN_PUPD_SPEC_SR(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
52 MTK_PIN_PUPD_SPEC_SR(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
53 MTK_PIN_PUPD_SPEC_SR(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
54 MTK_PIN_PUPD_SPEC_SR(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
55 MTK_PIN_PUPD_SPEC_SR(77, 0xc40, 2, 1, 0), /* ms1 clk */
56
57 MTK_PIN_PUPD_SPEC_SR(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
58 MTK_PIN_PUPD_SPEC_SR(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
59 MTK_PIN_PUPD_SPEC_SR(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
60 MTK_PIN_PUPD_SPEC_SR(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
61 MTK_PIN_PUPD_SPEC_SR(104, 0xc80, 2, 1, 0), /* ms2 clk */
62 MTK_PIN_PUPD_SPEC_SR(105, 0xc90, 2, 1, 0), /* ms2 cmd */
63
64 MTK_PIN_PUPD_SPEC_SR(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
65 MTK_PIN_PUPD_SPEC_SR(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
66 MTK_PIN_PUPD_SPEC_SR(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
67 MTK_PIN_PUPD_SPEC_SR(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
68 MTK_PIN_PUPD_SPEC_SR(26, 0xcc0, 2, 1, 0), /* ms3 clk */
69 MTK_PIN_PUPD_SPEC_SR(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
40}; 70};
41 71
42#define MTK_PIN_IES_SMT_SET(_start, _end, _offset, _bit) \ 72static int mt8173_spec_pull_set(struct regmap *regmap, unsigned int pin,
43 { \
44 .start = _start, \
45 .end = _end, \
46 .bit = _bit, \
47 .offset = _offset, \
48 }
49
50/**
51 * struct mtk_pin_spec_pupd_set - For special pins' pull up/down setting.
52 * @pin: The pin number.
53 * @offset: The offset of special pull up/down setting register.
54 * @pupd_bit: The pull up/down bit in this register.
55 * @r0_bit: The r0 bit of pull resistor.
56 * @r1_bit: The r1 bit of pull resistor.
57 */
58struct mtk_pin_spec_pupd_set {
59 unsigned int pin;
60 unsigned int offset;
61 unsigned char pupd_bit;
62 unsigned char r1_bit;
63 unsigned char r0_bit;
64};
65
66#define MTK_PIN_PUPD_SPEC(_pin, _offset, _pupd, _r1, _r0) \
67 { \
68 .pin = _pin, \
69 .offset = _offset, \
70 .pupd_bit = _pupd, \
71 .r1_bit = _r1, \
72 .r0_bit = _r0, \
73 }
74
75static const struct mtk_pin_spec_pupd_set mt8173_spec_pupd[] = {
76 MTK_PIN_PUPD_SPEC(119, 0xe00, 2, 1, 0), /* KROW0 */
77 MTK_PIN_PUPD_SPEC(120, 0xe00, 6, 5, 4), /* KROW1 */
78 MTK_PIN_PUPD_SPEC(121, 0xe00, 10, 9, 8), /* KROW2 */
79 MTK_PIN_PUPD_SPEC(122, 0xe10, 2, 1, 0), /* KCOL0 */
80 MTK_PIN_PUPD_SPEC(123, 0xe10, 6, 5, 4), /* KCOL1 */
81 MTK_PIN_PUPD_SPEC(124, 0xe10, 10, 9, 8), /* KCOL2 */
82
83 MTK_PIN_PUPD_SPEC(67, 0xd10, 2, 1, 0), /* ms0 DS */
84 MTK_PIN_PUPD_SPEC(68, 0xd00, 2, 1, 0), /* ms0 RST */
85 MTK_PIN_PUPD_SPEC(66, 0xc10, 2, 1, 0), /* ms0 cmd */
86 MTK_PIN_PUPD_SPEC(65, 0xc00, 2, 1, 0), /* ms0 clk */
87 MTK_PIN_PUPD_SPEC(57, 0xc20, 2, 1, 0), /* ms0 data0 */
88 MTK_PIN_PUPD_SPEC(58, 0xc20, 2, 1, 0), /* ms0 data1 */
89 MTK_PIN_PUPD_SPEC(59, 0xc20, 2, 1, 0), /* ms0 data2 */
90 MTK_PIN_PUPD_SPEC(60, 0xc20, 2, 1, 0), /* ms0 data3 */
91 MTK_PIN_PUPD_SPEC(61, 0xc20, 2, 1, 0), /* ms0 data4 */
92 MTK_PIN_PUPD_SPEC(62, 0xc20, 2, 1, 0), /* ms0 data5 */
93 MTK_PIN_PUPD_SPEC(63, 0xc20, 2, 1, 0), /* ms0 data6 */
94 MTK_PIN_PUPD_SPEC(64, 0xc20, 2, 1, 0), /* ms0 data7 */
95
96 MTK_PIN_PUPD_SPEC(78, 0xc50, 2, 1, 0), /* ms1 cmd */
97 MTK_PIN_PUPD_SPEC(73, 0xd20, 2, 1, 0), /* ms1 dat0 */
98 MTK_PIN_PUPD_SPEC(74, 0xd20, 6, 5, 4), /* ms1 dat1 */
99 MTK_PIN_PUPD_SPEC(75, 0xd20, 10, 9, 8), /* ms1 dat2 */
100 MTK_PIN_PUPD_SPEC(76, 0xd20, 14, 13, 12), /* ms1 dat3 */
101 MTK_PIN_PUPD_SPEC(77, 0xc40, 2, 1, 0), /* ms1 clk */
102
103 MTK_PIN_PUPD_SPEC(100, 0xd40, 2, 1, 0), /* ms2 dat0 */
104 MTK_PIN_PUPD_SPEC(101, 0xd40, 6, 5, 4), /* ms2 dat1 */
105 MTK_PIN_PUPD_SPEC(102, 0xd40, 10, 9, 8), /* ms2 dat2 */
106 MTK_PIN_PUPD_SPEC(103, 0xd40, 14, 13, 12), /* ms2 dat3 */
107 MTK_PIN_PUPD_SPEC(104, 0xc80, 2, 1, 0), /* ms2 clk */
108 MTK_PIN_PUPD_SPEC(105, 0xc90, 2, 1, 0), /* ms2 cmd */
109
110 MTK_PIN_PUPD_SPEC(22, 0xd60, 2, 1, 0), /* ms3 dat0 */
111 MTK_PIN_PUPD_SPEC(23, 0xd60, 6, 5, 4), /* ms3 dat1 */
112 MTK_PIN_PUPD_SPEC(24, 0xd60, 10, 9, 8), /* ms3 dat2 */
113 MTK_PIN_PUPD_SPEC(25, 0xd60, 14, 13, 12), /* ms3 dat3 */
114 MTK_PIN_PUPD_SPEC(26, 0xcc0, 2, 1, 0), /* ms3 clk */
115 MTK_PIN_PUPD_SPEC(27, 0xcd0, 2, 1, 0) /* ms3 cmd */
116};
117
118static int spec_pull_set(struct regmap *regmap, unsigned int pin,
119 unsigned char align, bool isup, unsigned int r1r0) 73 unsigned char align, bool isup, unsigned int r1r0)
120{ 74{
121 unsigned int i; 75 return mtk_pctrl_spec_pull_set_samereg(regmap, mt8173_spec_pupd,
122 unsigned int reg_pupd, reg_set, reg_rst; 76 ARRAY_SIZE(mt8173_spec_pupd), pin, align, isup, r1r0);
123 unsigned int bit_pupd, bit_r0, bit_r1;
124 const struct mtk_pin_spec_pupd_set *spec_pupd_pin;
125 bool find = false;
126
127 for (i = 0; i < ARRAY_SIZE(mt8173_spec_pupd); i++) {
128 if (pin == mt8173_spec_pupd[i].pin) {
129 find = true;
130 break;
131 }
132 }
133
134 if (!find)
135 return -EINVAL;
136
137 spec_pupd_pin = mt8173_spec_pupd + i;
138 reg_set = spec_pupd_pin->offset + align;
139 reg_rst = spec_pupd_pin->offset + (align << 1);
140
141 if (isup)
142 reg_pupd = reg_rst;
143 else
144 reg_pupd = reg_set;
145
146 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
147 regmap_write(regmap, reg_pupd, bit_pupd);
148
149 bit_r0 = BIT(spec_pupd_pin->r0_bit);
150 bit_r1 = BIT(spec_pupd_pin->r1_bit);
151
152 switch (r1r0) {
153 case MTK_PUPD_SET_R1R0_00:
154 regmap_write(regmap, reg_rst, bit_r0);
155 regmap_write(regmap, reg_rst, bit_r1);
156 break;
157 case MTK_PUPD_SET_R1R0_01:
158 regmap_write(regmap, reg_set, bit_r0);
159 regmap_write(regmap, reg_rst, bit_r1);
160 break;
161 case MTK_PUPD_SET_R1R0_10:
162 regmap_write(regmap, reg_rst, bit_r0);
163 regmap_write(regmap, reg_set, bit_r1);
164 break;
165 case MTK_PUPD_SET_R1R0_11:
166 regmap_write(regmap, reg_set, bit_r0);
167 regmap_write(regmap, reg_set, bit_r1);
168 break;
169 default:
170 return -EINVAL;
171 }
172
173 return 0;
174} 77}
175 78
176static const struct mtk_pin_ies_smt_set mt8173_ies_smt_set[] = { 79static const struct mtk_pin_ies_smt_set mt8173_smt_set[] = {
177 MTK_PIN_IES_SMT_SET(0, 4, 0x930, 1), 80 MTK_PIN_IES_SMT_SPEC(0, 4, 0x930, 1),
178 MTK_PIN_IES_SMT_SET(5, 9, 0x930, 2), 81 MTK_PIN_IES_SMT_SPEC(5, 9, 0x930, 2),
179 MTK_PIN_IES_SMT_SET(10, 13, 0x930, 10), 82 MTK_PIN_IES_SMT_SPEC(10, 13, 0x930, 10),
180 MTK_PIN_IES_SMT_SET(14, 15, 0x940, 10), 83 MTK_PIN_IES_SMT_SPEC(14, 15, 0x940, 10),
181 MTK_PIN_IES_SMT_SET(16, 16, 0x930, 0), 84 MTK_PIN_IES_SMT_SPEC(16, 16, 0x930, 0),
182 MTK_PIN_IES_SMT_SET(17, 17, 0x950, 2), 85 MTK_PIN_IES_SMT_SPEC(17, 17, 0x950, 2),
183 MTK_PIN_IES_SMT_SET(18, 21, 0x940, 3), 86 MTK_PIN_IES_SMT_SPEC(18, 21, 0x940, 3),
184 MTK_PIN_IES_SMT_SET(29, 32, 0x930, 3), 87 MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 13),
185 MTK_PIN_IES_SMT_SET(33, 33, 0x930, 4), 88 MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 13),
186 MTK_PIN_IES_SMT_SET(34, 36, 0x930, 5), 89 MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 13),
187 MTK_PIN_IES_SMT_SET(37, 38, 0x930, 6), 90 MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 13),
188 MTK_PIN_IES_SMT_SET(39, 39, 0x930, 7), 91 MTK_PIN_IES_SMT_SPEC(29, 32, 0x930, 3),
189 MTK_PIN_IES_SMT_SET(40, 41, 0x930, 9), 92 MTK_PIN_IES_SMT_SPEC(33, 33, 0x930, 4),
190 MTK_PIN_IES_SMT_SET(42, 42, 0x940, 0), 93 MTK_PIN_IES_SMT_SPEC(34, 36, 0x930, 5),
191 MTK_PIN_IES_SMT_SET(43, 44, 0x930, 11), 94 MTK_PIN_IES_SMT_SPEC(37, 38, 0x930, 6),
192 MTK_PIN_IES_SMT_SET(45, 46, 0x930, 12), 95 MTK_PIN_IES_SMT_SPEC(39, 39, 0x930, 7),
193 MTK_PIN_IES_SMT_SET(57, 64, 0xc20, 13), 96 MTK_PIN_IES_SMT_SPEC(40, 41, 0x930, 9),
194 MTK_PIN_IES_SMT_SET(65, 65, 0xc10, 13), 97 MTK_PIN_IES_SMT_SPEC(42, 42, 0x940, 0),
195 MTK_PIN_IES_SMT_SET(66, 66, 0xc00, 13), 98 MTK_PIN_IES_SMT_SPEC(43, 44, 0x930, 11),
196 MTK_PIN_IES_SMT_SET(67, 67, 0xd10, 13), 99 MTK_PIN_IES_SMT_SPEC(45, 46, 0x930, 12),
197 MTK_PIN_IES_SMT_SET(68, 68, 0xd00, 13), 100 MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 13),
198 MTK_PIN_IES_SMT_SET(69, 72, 0x940, 14), 101 MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 13),
199 MTK_PIN_IES_SMT_SET(73, 76, 0xc60, 13), 102 MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 13),
200 MTK_PIN_IES_SMT_SET(77, 77, 0xc40, 13), 103 MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 13),
201 MTK_PIN_IES_SMT_SET(78, 78, 0xc50, 13), 104 MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 13),
202 MTK_PIN_IES_SMT_SET(79, 82, 0x940, 15), 105 MTK_PIN_IES_SMT_SPEC(69, 72, 0x940, 14),
203 MTK_PIN_IES_SMT_SET(83, 83, 0x950, 0), 106 MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 13),
204 MTK_PIN_IES_SMT_SET(84, 85, 0x950, 1), 107 MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 13),
205 MTK_PIN_IES_SMT_SET(86, 91, 0x950, 2), 108 MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 13),
206 MTK_PIN_IES_SMT_SET(92, 92, 0x930, 13), 109 MTK_PIN_IES_SMT_SPEC(79, 82, 0x940, 15),
207 MTK_PIN_IES_SMT_SET(93, 95, 0x930, 14), 110 MTK_PIN_IES_SMT_SPEC(83, 83, 0x950, 0),
208 MTK_PIN_IES_SMT_SET(96, 99, 0x930, 15), 111 MTK_PIN_IES_SMT_SPEC(84, 85, 0x950, 1),
209 MTK_PIN_IES_SMT_SET(100, 103, 0xca0, 13), 112 MTK_PIN_IES_SMT_SPEC(86, 91, 0x950, 2),
210 MTK_PIN_IES_SMT_SET(104, 104, 0xc80, 13), 113 MTK_PIN_IES_SMT_SPEC(92, 92, 0x930, 13),
211 MTK_PIN_IES_SMT_SET(105, 105, 0xc90, 13), 114 MTK_PIN_IES_SMT_SPEC(93, 95, 0x930, 14),
212 MTK_PIN_IES_SMT_SET(106, 107, 0x940, 4), 115 MTK_PIN_IES_SMT_SPEC(96, 99, 0x930, 15),
213 MTK_PIN_IES_SMT_SET(108, 112, 0x940, 1), 116 MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 13),
214 MTK_PIN_IES_SMT_SET(113, 116, 0x940, 2), 117 MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 13),
215 MTK_PIN_IES_SMT_SET(117, 118, 0x940, 5), 118 MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 13),
216 MTK_PIN_IES_SMT_SET(119, 124, 0x940, 6), 119 MTK_PIN_IES_SMT_SPEC(106, 107, 0x940, 4),
217 MTK_PIN_IES_SMT_SET(125, 126, 0x940, 7), 120 MTK_PIN_IES_SMT_SPEC(108, 112, 0x940, 1),
218 MTK_PIN_IES_SMT_SET(127, 127, 0x940, 0), 121 MTK_PIN_IES_SMT_SPEC(113, 116, 0x940, 2),
219 MTK_PIN_IES_SMT_SET(128, 128, 0x950, 8), 122 MTK_PIN_IES_SMT_SPEC(117, 118, 0x940, 5),
220 MTK_PIN_IES_SMT_SET(129, 130, 0x950, 9), 123 MTK_PIN_IES_SMT_SPEC(119, 124, 0x940, 6),
221 MTK_PIN_IES_SMT_SET(131, 132, 0x950, 8), 124 MTK_PIN_IES_SMT_SPEC(125, 126, 0x940, 7),
222 MTK_PIN_IES_SMT_SET(133, 134, 0x910, 8) 125 MTK_PIN_IES_SMT_SPEC(127, 127, 0x940, 0),
126 MTK_PIN_IES_SMT_SPEC(128, 128, 0x950, 8),
127 MTK_PIN_IES_SMT_SPEC(129, 130, 0x950, 9),
128 MTK_PIN_IES_SMT_SPEC(131, 132, 0x950, 8),
129 MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
223}; 130};
224 131
225static int spec_ies_smt_set(struct regmap *regmap, unsigned int pin, 132static const struct mtk_pin_ies_smt_set mt8173_ies_set[] = {
226 unsigned char align, int value) 133 MTK_PIN_IES_SMT_SPEC(0, 4, 0x900, 1),
227{ 134 MTK_PIN_IES_SMT_SPEC(5, 9, 0x900, 2),
228 unsigned int i, reg_addr, bit; 135 MTK_PIN_IES_SMT_SPEC(10, 13, 0x900, 10),
229 bool find = false; 136 MTK_PIN_IES_SMT_SPEC(14, 15, 0x910, 10),
230 137 MTK_PIN_IES_SMT_SPEC(16, 16, 0x900, 0),
231 for (i = 0; i < ARRAY_SIZE(mt8173_ies_smt_set); i++) { 138 MTK_PIN_IES_SMT_SPEC(17, 17, 0x920, 2),
232 if (pin >= mt8173_ies_smt_set[i].start && 139 MTK_PIN_IES_SMT_SPEC(18, 21, 0x910, 3),
233 pin <= mt8173_ies_smt_set[i].end) { 140 MTK_PIN_IES_SMT_SPEC(22, 25, 0xce0, 14),
234 find = true; 141 MTK_PIN_IES_SMT_SPEC(26, 26, 0xcc0, 14),
235 break; 142 MTK_PIN_IES_SMT_SPEC(27, 27, 0xcd0, 14),
236 } 143 MTK_PIN_IES_SMT_SPEC(28, 28, 0xd70, 14),
237 } 144 MTK_PIN_IES_SMT_SPEC(29, 32, 0x900, 3),
238 145 MTK_PIN_IES_SMT_SPEC(33, 33, 0x900, 4),
239 if (!find) 146 MTK_PIN_IES_SMT_SPEC(34, 36, 0x900, 5),
240 return -EINVAL; 147 MTK_PIN_IES_SMT_SPEC(37, 38, 0x900, 6),
241 148 MTK_PIN_IES_SMT_SPEC(39, 39, 0x900, 7),
242 if (value) 149 MTK_PIN_IES_SMT_SPEC(40, 41, 0x900, 9),
243 reg_addr = mt8173_ies_smt_set[i].offset + align; 150 MTK_PIN_IES_SMT_SPEC(42, 42, 0x910, 0),
244 else 151 MTK_PIN_IES_SMT_SPEC(43, 44, 0x900, 11),
245 reg_addr = mt8173_ies_smt_set[i].offset + (align << 1); 152 MTK_PIN_IES_SMT_SPEC(45, 46, 0x900, 12),
153 MTK_PIN_IES_SMT_SPEC(57, 64, 0xc20, 14),
154 MTK_PIN_IES_SMT_SPEC(65, 65, 0xc10, 14),
155 MTK_PIN_IES_SMT_SPEC(66, 66, 0xc00, 14),
156 MTK_PIN_IES_SMT_SPEC(67, 67, 0xd10, 14),
157 MTK_PIN_IES_SMT_SPEC(68, 68, 0xd00, 14),
158 MTK_PIN_IES_SMT_SPEC(69, 72, 0x910, 14),
159 MTK_PIN_IES_SMT_SPEC(73, 76, 0xc60, 14),
160 MTK_PIN_IES_SMT_SPEC(77, 77, 0xc40, 14),
161 MTK_PIN_IES_SMT_SPEC(78, 78, 0xc50, 14),
162 MTK_PIN_IES_SMT_SPEC(79, 82, 0x910, 15),
163 MTK_PIN_IES_SMT_SPEC(83, 83, 0x920, 0),
164 MTK_PIN_IES_SMT_SPEC(84, 85, 0x920, 1),
165 MTK_PIN_IES_SMT_SPEC(86, 91, 0x920, 2),
166 MTK_PIN_IES_SMT_SPEC(92, 92, 0x900, 13),
167 MTK_PIN_IES_SMT_SPEC(93, 95, 0x900, 14),
168 MTK_PIN_IES_SMT_SPEC(96, 99, 0x900, 15),
169 MTK_PIN_IES_SMT_SPEC(100, 103, 0xca0, 14),
170 MTK_PIN_IES_SMT_SPEC(104, 104, 0xc80, 14),
171 MTK_PIN_IES_SMT_SPEC(105, 105, 0xc90, 14),
172 MTK_PIN_IES_SMT_SPEC(106, 107, 0x910, 4),
173 MTK_PIN_IES_SMT_SPEC(108, 112, 0x910, 1),
174 MTK_PIN_IES_SMT_SPEC(113, 116, 0x910, 2),
175 MTK_PIN_IES_SMT_SPEC(117, 118, 0x910, 5),
176 MTK_PIN_IES_SMT_SPEC(119, 124, 0x910, 6),
177 MTK_PIN_IES_SMT_SPEC(125, 126, 0x910, 7),
178 MTK_PIN_IES_SMT_SPEC(127, 127, 0x910, 0),
179 MTK_PIN_IES_SMT_SPEC(128, 128, 0x920, 8),
180 MTK_PIN_IES_SMT_SPEC(129, 130, 0x920, 9),
181 MTK_PIN_IES_SMT_SPEC(131, 132, 0x920, 8),
182 MTK_PIN_IES_SMT_SPEC(133, 134, 0x910, 8)
183};
246 184
247 bit = BIT(mt8173_ies_smt_set[i].bit); 185static int mt8173_ies_smt_set(struct regmap *regmap, unsigned int pin,
248 regmap_write(regmap, reg_addr, bit); 186 unsigned char align, int value, enum pin_config_param arg)
249 return 0; 187{
188 if (arg == PIN_CONFIG_INPUT_ENABLE)
189 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_ies_set,
190 ARRAY_SIZE(mt8173_ies_set), pin, align, value);
191 else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
192 return mtk_pconf_spec_set_ies_smt_range(regmap, mt8173_smt_set,
193 ARRAY_SIZE(mt8173_smt_set), pin, align, value);
194 return -EINVAL;
250} 195}
251 196
252static const struct mtk_drv_group_desc mt8173_drv_grp[] = { 197static const struct mtk_drv_group_desc mt8173_drv_grp[] = {
@@ -382,8 +327,8 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
382 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp), 327 .n_grp_cls = ARRAY_SIZE(mt8173_drv_grp),
383 .pin_drv_grp = mt8173_pin_drv, 328 .pin_drv_grp = mt8173_pin_drv,
384 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv), 329 .n_pin_drv_grps = ARRAY_SIZE(mt8173_pin_drv),
385 .spec_pull_set = spec_pull_set, 330 .spec_pull_set = mt8173_spec_pull_set,
386 .spec_ies_smt_set = spec_ies_smt_set, 331 .spec_ies_smt_set = mt8173_ies_smt_set,
387 .dir_offset = 0x0000, 332 .dir_offset = 0x0000,
388 .pullen_offset = 0x0100, 333 .pullen_offset = 0x0100,
389 .pullsel_offset = 0x0200, 334 .pullsel_offset = 0x0200,
@@ -424,7 +369,7 @@ static const struct mtk_pinctrl_devdata mt8173_pinctrl_data = {
424 369
425static int mt8173_pinctrl_probe(struct platform_device *pdev) 370static int mt8173_pinctrl_probe(struct platform_device *pdev)
426{ 371{
427 return mtk_pctrl_init(pdev, &mt8173_pinctrl_data); 372 return mtk_pctrl_init(pdev, &mt8173_pinctrl_data, NULL);
428} 373}
429 374
430static const struct of_device_id mt8173_pctrl_match[] = { 375static const struct of_device_id mt8173_pctrl_match[] = {
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 474812e2b0cb..c4fc77aa766e 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -107,28 +107,38 @@ static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
107 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit); 107 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
108} 108}
109 109
110static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin, 110static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
111 int value, enum pin_config_param param) 111 int value, enum pin_config_param arg)
112{ 112{
113 unsigned int reg_addr, offset; 113 unsigned int reg_addr, offset;
114 unsigned int bit; 114 unsigned int bit;
115 int ret; 115
116 /**
117 * Due to some soc are not support ies/smt config, add this special
118 * control to handle it.
119 */
120 if (!pctl->devdata->spec_ies_smt_set &&
121 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
122 arg == PIN_CONFIG_INPUT_ENABLE)
123 return -EINVAL;
124
125 if (!pctl->devdata->spec_ies_smt_set &&
126 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
127 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
128 return -EINVAL;
116 129
117 /* 130 /*
118 * Due to some pins are irregular, their input enable and smt 131 * Due to some pins are irregular, their input enable and smt
119 * control register are discontinuous, but they are mapping together. 132 * control register are discontinuous, so we need this special handle.
120 * So we need this special handle.
121 */ 133 */
122 if (pctl->devdata->spec_ies_smt_set) { 134 if (pctl->devdata->spec_ies_smt_set) {
123 ret = pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin), 135 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
124 pin, pctl->devdata->port_align, value); 136 pin, pctl->devdata->port_align, value, arg);
125 if (!ret)
126 return;
127 } 137 }
128 138
129 bit = BIT(pin & 0xf); 139 bit = BIT(pin & 0xf);
130 140
131 if (param == PIN_CONFIG_INPUT_ENABLE) 141 if (arg == PIN_CONFIG_INPUT_ENABLE)
132 offset = pctl->devdata->ies_offset; 142 offset = pctl->devdata->ies_offset;
133 else 143 else
134 offset = pctl->devdata->smt_offset; 144 offset = pctl->devdata->smt_offset;
@@ -139,6 +149,33 @@ static void mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
139 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl); 149 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
140 150
141 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit); 151 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
152 return 0;
153}
154
155int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
156 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
157 unsigned int pin, unsigned char align, int value)
158{
159 unsigned int i, reg_addr, bit;
160
161 for (i = 0; i < info_num; i++) {
162 if (pin >= ies_smt_infos[i].start &&
163 pin <= ies_smt_infos[i].end) {
164 break;
165 }
166 }
167
168 if (i == info_num)
169 return -EINVAL;
170
171 if (value)
172 reg_addr = ies_smt_infos[i].offset + align;
173 else
174 reg_addr = ies_smt_infos[i].offset + (align << 1);
175
176 bit = BIT(ies_smt_infos[i].bit);
177 regmap_write(regmap, reg_addr, bit);
178 return 0;
142} 179}
143 180
144static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin( 181static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
@@ -186,6 +223,66 @@ static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
186 return -EINVAL; 223 return -EINVAL;
187} 224}
188 225
226int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
227 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
228 unsigned int info_num, unsigned int pin,
229 unsigned char align, bool isup, unsigned int r1r0)
230{
231 unsigned int i;
232 unsigned int reg_pupd, reg_set, reg_rst;
233 unsigned int bit_pupd, bit_r0, bit_r1;
234 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
235 bool find = false;
236
237 for (i = 0; i < info_num; i++) {
238 if (pin == pupd_infos[i].pin) {
239 find = true;
240 break;
241 }
242 }
243
244 if (!find)
245 return -EINVAL;
246
247 spec_pupd_pin = pupd_infos + i;
248 reg_set = spec_pupd_pin->offset + align;
249 reg_rst = spec_pupd_pin->offset + (align << 1);
250
251 if (isup)
252 reg_pupd = reg_rst;
253 else
254 reg_pupd = reg_set;
255
256 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
257 regmap_write(regmap, reg_pupd, bit_pupd);
258
259 bit_r0 = BIT(spec_pupd_pin->r0_bit);
260 bit_r1 = BIT(spec_pupd_pin->r1_bit);
261
262 switch (r1r0) {
263 case MTK_PUPD_SET_R1R0_00:
264 regmap_write(regmap, reg_rst, bit_r0);
265 regmap_write(regmap, reg_rst, bit_r1);
266 break;
267 case MTK_PUPD_SET_R1R0_01:
268 regmap_write(regmap, reg_set, bit_r0);
269 regmap_write(regmap, reg_rst, bit_r1);
270 break;
271 case MTK_PUPD_SET_R1R0_10:
272 regmap_write(regmap, reg_rst, bit_r0);
273 regmap_write(regmap, reg_set, bit_r1);
274 break;
275 case MTK_PUPD_SET_R1R0_11:
276 regmap_write(regmap, reg_set, bit_r0);
277 regmap_write(regmap, reg_set, bit_r1);
278 break;
279 default:
280 return -EINVAL;
281 }
282
283 return 0;
284}
285
189static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl, 286static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
190 unsigned int pin, bool enable, bool isup, unsigned int arg) 287 unsigned int pin, bool enable, bool isup, unsigned int arg)
191{ 288{
@@ -235,36 +332,37 @@ static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
235 unsigned int pin, enum pin_config_param param, 332 unsigned int pin, enum pin_config_param param,
236 enum pin_config_param arg) 333 enum pin_config_param arg)
237{ 334{
335 int ret = 0;
238 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 336 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
239 337
240 switch (param) { 338 switch (param) {
241 case PIN_CONFIG_BIAS_DISABLE: 339 case PIN_CONFIG_BIAS_DISABLE:
242 mtk_pconf_set_pull_select(pctl, pin, false, false, arg); 340 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
243 break; 341 break;
244 case PIN_CONFIG_BIAS_PULL_UP: 342 case PIN_CONFIG_BIAS_PULL_UP:
245 mtk_pconf_set_pull_select(pctl, pin, true, true, arg); 343 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
246 break; 344 break;
247 case PIN_CONFIG_BIAS_PULL_DOWN: 345 case PIN_CONFIG_BIAS_PULL_DOWN:
248 mtk_pconf_set_pull_select(pctl, pin, true, false, arg); 346 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
249 break; 347 break;
250 case PIN_CONFIG_INPUT_ENABLE: 348 case PIN_CONFIG_INPUT_ENABLE:
251 mtk_pconf_set_ies_smt(pctl, pin, arg, param); 349 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
252 break; 350 break;
253 case PIN_CONFIG_OUTPUT: 351 case PIN_CONFIG_OUTPUT:
254 mtk_gpio_set(pctl->chip, pin, arg); 352 mtk_gpio_set(pctl->chip, pin, arg);
255 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false); 353 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
256 break; 354 break;
257 case PIN_CONFIG_INPUT_SCHMITT_ENABLE: 355 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
258 mtk_pconf_set_ies_smt(pctl, pin, arg, param); 356 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
259 break; 357 break;
260 case PIN_CONFIG_DRIVE_STRENGTH: 358 case PIN_CONFIG_DRIVE_STRENGTH:
261 mtk_pconf_set_driving(pctl, pin, arg); 359 ret = mtk_pconf_set_driving(pctl, pin, arg);
262 break; 360 break;
263 default: 361 default:
264 return -EINVAL; 362 ret = -EINVAL;
265 } 363 }
266 364
267 return 0; 365 return ret;
268} 366}
269 367
270static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, 368static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
@@ -283,12 +381,14 @@ static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
283{ 381{
284 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev); 382 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
285 struct mtk_pinctrl_group *g = &pctl->groups[group]; 383 struct mtk_pinctrl_group *g = &pctl->groups[group];
286 int i; 384 int i, ret;
287 385
288 for (i = 0; i < num_configs; i++) { 386 for (i = 0; i < num_configs; i++) {
289 mtk_pconf_parse_conf(pctldev, g->pin, 387 ret = mtk_pconf_parse_conf(pctldev, g->pin,
290 pinconf_to_config_param(configs[i]), 388 pinconf_to_config_param(configs[i]),
291 pinconf_to_config_argument(configs[i])); 389 pinconf_to_config_argument(configs[i]));
390 if (ret < 0)
391 return ret;
292 392
293 g->config = configs[i]; 393 g->config = configs[i];
294 } 394 }
@@ -1109,7 +1209,8 @@ static struct pinctrl_desc mtk_pctrl_desc = {
1109}; 1209};
1110 1210
1111int mtk_pctrl_init(struct platform_device *pdev, 1211int mtk_pctrl_init(struct platform_device *pdev,
1112 const struct mtk_pinctrl_devdata *data) 1212 const struct mtk_pinctrl_devdata *data,
1213 struct regmap *regmap)
1113{ 1214{
1114 struct pinctrl_pin_desc *pins; 1215 struct pinctrl_pin_desc *pins;
1115 struct mtk_pinctrl *pctl; 1216 struct mtk_pinctrl *pctl;
@@ -1135,6 +1236,11 @@ int mtk_pctrl_init(struct platform_device *pdev,
1135 pctl->regmap1 = syscon_node_to_regmap(node); 1236 pctl->regmap1 = syscon_node_to_regmap(node);
1136 if (IS_ERR(pctl->regmap1)) 1237 if (IS_ERR(pctl->regmap1))
1137 return PTR_ERR(pctl->regmap1); 1238 return PTR_ERR(pctl->regmap1);
1239 } else if (regmap) {
1240 pctl->regmap1 = regmap;
1241 } else {
1242 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1243 return -EINVAL;
1138 } 1244 }
1139 1245
1140 /* Only 8135 has two base addr, other SoCs have only one. */ 1246 /* Only 8135 has two base addr, other SoCs have only one. */
@@ -1165,9 +1271,9 @@ int mtk_pctrl_init(struct platform_device *pdev,
1165 mtk_pctrl_desc.npins = pctl->devdata->npins; 1271 mtk_pctrl_desc.npins = pctl->devdata->npins;
1166 pctl->dev = &pdev->dev; 1272 pctl->dev = &pdev->dev;
1167 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl); 1273 pctl->pctl_dev = pinctrl_register(&mtk_pctrl_desc, &pdev->dev, pctl);
1168 if (!pctl->pctl_dev) { 1274 if (IS_ERR(pctl->pctl_dev)) {
1169 dev_err(&pdev->dev, "couldn't register pinctrl driver\n"); 1275 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1170 return -EINVAL; 1276 return PTR_ERR(pctl->pctl_dev);
1171 } 1277 }
1172 1278
1173 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL); 1279 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
@@ -1176,11 +1282,11 @@ int mtk_pctrl_init(struct platform_device *pdev,
1176 goto pctrl_error; 1282 goto pctrl_error;
1177 } 1283 }
1178 1284
1179 pctl->chip = &mtk_gpio_chip; 1285 *pctl->chip = mtk_gpio_chip;
1180 pctl->chip->ngpio = pctl->devdata->npins; 1286 pctl->chip->ngpio = pctl->devdata->npins;
1181 pctl->chip->label = dev_name(&pdev->dev); 1287 pctl->chip->label = dev_name(&pdev->dev);
1182 pctl->chip->dev = &pdev->dev; 1288 pctl->chip->dev = &pdev->dev;
1183 pctl->chip->base = 0; 1289 pctl->chip->base = -1;
1184 1290
1185 ret = gpiochip_add(pctl->chip); 1291 ret = gpiochip_add(pctl->chip);
1186 if (ret) { 1292 if (ret) {
@@ -1196,6 +1302,9 @@ int mtk_pctrl_init(struct platform_device *pdev,
1196 goto chip_error; 1302 goto chip_error;
1197 } 1303 }
1198 1304
1305 if (!of_property_read_bool(np, "interrupt-controller"))
1306 return 0;
1307
1199 /* Get EINT register base from dts. */ 1308 /* Get EINT register base from dts. */
1200 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1309 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1201 if (!res) { 1310 if (!res) {
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 375771db9bd0..30213e514c2f 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -17,16 +17,17 @@
17 17
18#include <linux/pinctrl/pinctrl.h> 18#include <linux/pinctrl/pinctrl.h>
19#include <linux/regmap.h> 19#include <linux/regmap.h>
20#include <linux/pinctrl/pinconf-generic.h>
20 21
21#define NO_EINT_SUPPORT 255 22#define NO_EINT_SUPPORT 255
22#define MTK_CHIP_TYPE_BASE 0
23#define MTK_CHIP_TYPE_PMIC 1
24#define MT_EDGE_SENSITIVE 0 23#define MT_EDGE_SENSITIVE 0
25#define MT_LEVEL_SENSITIVE 1 24#define MT_LEVEL_SENSITIVE 1
26#define EINT_DBNC_SET_DBNC_BITS 4 25#define EINT_DBNC_SET_DBNC_BITS 4
27#define EINT_DBNC_RST_BIT (0x1 << 1) 26#define EINT_DBNC_RST_BIT (0x1 << 1)
28#define EINT_DBNC_SET_EN (0x1 << 0) 27#define EINT_DBNC_SET_EN (0x1 << 0)
29 28
29#define MTK_PINCTRL_NOT_SUPPORT (0xffff)
30
30struct mtk_desc_function { 31struct mtk_desc_function {
31 const char *name; 32 const char *name;
32 unsigned char muxval; 33 unsigned char muxval;
@@ -39,7 +40,6 @@ struct mtk_desc_eint {
39 40
40struct mtk_desc_pin { 41struct mtk_desc_pin {
41 struct pinctrl_pin_desc pin; 42 struct pinctrl_pin_desc pin;
42 const char *chip;
43 const struct mtk_desc_eint eint; 43 const struct mtk_desc_eint eint;
44 const struct mtk_desc_function *functions; 44 const struct mtk_desc_function *functions;
45}; 45};
@@ -47,7 +47,6 @@ struct mtk_desc_pin {
47#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \ 47#define MTK_PIN(_pin, _pad, _chip, _eint, ...) \
48 { \ 48 { \
49 .pin = _pin, \ 49 .pin = _pin, \
50 .chip = _chip, \
51 .eint = _eint, \ 50 .eint = _eint, \
52 .functions = (struct mtk_desc_function[]){ \ 51 .functions = (struct mtk_desc_function[]){ \
53 __VA_ARGS__, { } }, \ 52 __VA_ARGS__, { } }, \
@@ -107,8 +106,8 @@ struct mtk_drv_group_desc {
107 * @grp: The group for this pin belongs to. 106 * @grp: The group for this pin belongs to.
108 */ 107 */
109struct mtk_pin_drv_grp { 108struct mtk_pin_drv_grp {
110 unsigned int pin; 109 unsigned short pin;
111 unsigned int offset; 110 unsigned short offset;
112 unsigned char bit; 111 unsigned char bit;
113 unsigned char grp; 112 unsigned char grp;
114}; 113};
@@ -121,6 +120,54 @@ struct mtk_pin_drv_grp {
121 .grp = _grp, \ 120 .grp = _grp, \
122 } 121 }
123 122
123/**
124 * struct mtk_pin_spec_pupd_set_samereg
125 * - For special pins' pull up/down setting which resides in same register
126 * @pin: The pin number.
127 * @offset: The offset of special pull up/down setting register.
128 * @pupd_bit: The pull up/down bit in this register.
129 * @r0_bit: The r0 bit of pull resistor.
130 * @r1_bit: The r1 bit of pull resistor.
131 */
132struct mtk_pin_spec_pupd_set_samereg {
133 unsigned short pin;
134 unsigned short offset;
135 unsigned char pupd_bit;
136 unsigned char r1_bit;
137 unsigned char r0_bit;
138};
139
140#define MTK_PIN_PUPD_SPEC_SR(_pin, _offset, _pupd, _r1, _r0) \
141 { \
142 .pin = _pin, \
143 .offset = _offset, \
144 .pupd_bit = _pupd, \
145 .r1_bit = _r1, \
146 .r0_bit = _r0, \
147 }
148
149/**
150 * struct mtk_pin_ies_set - For special pins' ies and smt setting.
151 * @start: The start pin number of those special pins.
152 * @end: The end pin number of those special pins.
153 * @offset: The offset of special setting register.
154 * @bit: The bit of special setting register.
155 */
156struct mtk_pin_ies_smt_set {
157 unsigned short start;
158 unsigned short end;
159 unsigned short offset;
160 unsigned char bit;
161};
162
163#define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \
164 { \
165 .start = _start, \
166 .end = _end, \
167 .bit = _bit, \
168 .offset = _offset, \
169 }
170
124struct mtk_eint_offsets { 171struct mtk_eint_offsets {
125 const char *name; 172 const char *name;
126 unsigned int stat; 173 unsigned int stat;
@@ -186,14 +233,13 @@ struct mtk_pinctrl_devdata {
186 int (*spec_pull_set)(struct regmap *reg, unsigned int pin, 233 int (*spec_pull_set)(struct regmap *reg, unsigned int pin,
187 unsigned char align, bool isup, unsigned int arg); 234 unsigned char align, bool isup, unsigned int arg);
188 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin, 235 int (*spec_ies_smt_set)(struct regmap *reg, unsigned int pin,
189 unsigned char align, int value); 236 unsigned char align, int value, enum pin_config_param arg);
190 unsigned int dir_offset; 237 unsigned int dir_offset;
191 unsigned int ies_offset; 238 unsigned int ies_offset;
192 unsigned int smt_offset; 239 unsigned int smt_offset;
193 unsigned int pullen_offset; 240 unsigned int pullen_offset;
194 unsigned int pullsel_offset; 241 unsigned int pullsel_offset;
195 unsigned int drv_offset; 242 unsigned int drv_offset;
196 unsigned int invser_offset;
197 unsigned int dout_offset; 243 unsigned int dout_offset;
198 unsigned int din_offset; 244 unsigned int din_offset;
199 unsigned int pinmux_offset; 245 unsigned int pinmux_offset;
@@ -202,7 +248,6 @@ struct mtk_pinctrl_devdata {
202 unsigned char port_shf; 248 unsigned char port_shf;
203 unsigned char port_mask; 249 unsigned char port_mask;
204 unsigned char port_align; 250 unsigned char port_align;
205 unsigned char chip_type;
206 struct mtk_eint_offsets eint_offsets; 251 struct mtk_eint_offsets eint_offsets;
207 unsigned int ap_num; 252 unsigned int ap_num;
208 unsigned int db_cnt; 253 unsigned int db_cnt;
@@ -224,6 +269,16 @@ struct mtk_pinctrl {
224}; 269};
225 270
226int mtk_pctrl_init(struct platform_device *pdev, 271int mtk_pctrl_init(struct platform_device *pdev,
227 const struct mtk_pinctrl_devdata *data); 272 const struct mtk_pinctrl_devdata *data,
273 struct regmap *regmap);
274
275int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
276 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
277 unsigned int info_num, unsigned int pin,
278 unsigned char align, bool isup, unsigned int r1r0);
279
280int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
281 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
282 unsigned int pin, unsigned char align, int value);
228 283
229#endif /* __PINCTRL_MTK_COMMON_H */ 284#endif /* __PINCTRL_MTK_COMMON_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
new file mode 100644
index 000000000000..4eb98ddb40a4
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt6397.h
@@ -0,0 +1,424 @@
1#ifndef __PINCTRL_MTK_MT6397_H
2#define __PINCTRL_MTK_MT6397_H
3
4#include <linux/pinctrl/pinctrl.h>
5#include "pinctrl-mtk-common.h"
6
7static const struct mtk_desc_pin mtk_pins_mt6397[] = {
8 MTK_PIN(
9 PINCTRL_PIN(0, "INT"),
10 "N2", "mt6397",
11 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
12 MTK_FUNCTION(0, "GPIO0"),
13 MTK_FUNCTION(1, "INT")
14 ),
15 MTK_PIN(
16 PINCTRL_PIN(1, "SRCVOLTEN"),
17 "M4", "mt6397",
18 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
19 MTK_FUNCTION(0, "GPIO1"),
20 MTK_FUNCTION(1, "SRCVOLTEN"),
21 MTK_FUNCTION(6, "TEST_CK1")
22 ),
23 MTK_PIN(
24 PINCTRL_PIN(2, "SRCLKEN_PERI"),
25 "M2", "mt6397",
26 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
27 MTK_FUNCTION(0, "GPIO2"),
28 MTK_FUNCTION(1, "SRCLKEN_PERI"),
29 MTK_FUNCTION(6, "TEST_CK2")
30 ),
31 MTK_PIN(
32 PINCTRL_PIN(3, "RTC_32K1V8"),
33 "K3", "mt6397",
34 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
35 MTK_FUNCTION(0, "GPIO3"),
36 MTK_FUNCTION(1, "RTC_32K1V8"),
37 MTK_FUNCTION(6, "TEST_CK3")
38 ),
39 MTK_PIN(
40 PINCTRL_PIN(4, "WRAP_EVENT"),
41 "J2", "mt6397",
42 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
43 MTK_FUNCTION(0, "GPIO4"),
44 MTK_FUNCTION(1, "WRAP_EVENT")
45 ),
46 MTK_PIN(
47 PINCTRL_PIN(5, "SPI_CLK"),
48 "L4", "mt6397",
49 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
50 MTK_FUNCTION(0, "GPIO5"),
51 MTK_FUNCTION(1, "SPI_CLK")
52 ),
53 MTK_PIN(
54 PINCTRL_PIN(6, "SPI_CSN"),
55 "J3", "mt6397",
56 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
57 MTK_FUNCTION(0, "GPIO6"),
58 MTK_FUNCTION(1, "SPI_CSN")
59 ),
60 MTK_PIN(
61 PINCTRL_PIN(7, "SPI_MOSI"),
62 "J1", "mt6397",
63 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
64 MTK_FUNCTION(0, "GPIO7"),
65 MTK_FUNCTION(1, "SPI_MOSI")
66 ),
67 MTK_PIN(
68 PINCTRL_PIN(8, "SPI_MISO"),
69 "L3", "mt6397",
70 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
71 MTK_FUNCTION(0, "GPIO8"),
72 MTK_FUNCTION(1, "SPI_MISO")
73 ),
74 MTK_PIN(
75 PINCTRL_PIN(9, "AUD_CLK_MOSI"),
76 "H2", "mt6397",
77 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
78 MTK_FUNCTION(0, "GPIO9"),
79 MTK_FUNCTION(1, "AUD_CLK"),
80 MTK_FUNCTION(6, "TEST_IN0"),
81 MTK_FUNCTION(7, "TEST_OUT0")
82 ),
83 MTK_PIN(
84 PINCTRL_PIN(10, "AUD_DAT_MISO"),
85 "H3", "mt6397",
86 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
87 MTK_FUNCTION(0, "GPIO10"),
88 MTK_FUNCTION(1, "AUD_MISO"),
89 MTK_FUNCTION(6, "TEST_IN1"),
90 MTK_FUNCTION(7, "TEST_OUT1")
91 ),
92 MTK_PIN(
93 PINCTRL_PIN(11, "AUD_DAT_MOSI"),
94 "H1", "mt6397",
95 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
96 MTK_FUNCTION(0, "GPIO11"),
97 MTK_FUNCTION(1, "AUD_MOSI"),
98 MTK_FUNCTION(6, "TEST_IN2"),
99 MTK_FUNCTION(7, "TEST_OUT2")
100 ),
101 MTK_PIN(
102 PINCTRL_PIN(12, "COL0"),
103 "F3", "mt6397",
104 MTK_EINT_FUNCTION(2, 10),
105 MTK_FUNCTION(0, "GPIO12"),
106 MTK_FUNCTION(1, "COL0_USBDL"),
107 MTK_FUNCTION(2, "EINT10_1X"),
108 MTK_FUNCTION(3, "PWM1_3X"),
109 MTK_FUNCTION(6, "TEST_IN3"),
110 MTK_FUNCTION(7, "TEST_OUT3")
111 ),
112 MTK_PIN(
113 PINCTRL_PIN(13, "COL1"),
114 "G8", "mt6397",
115 MTK_EINT_FUNCTION(2, 11),
116 MTK_FUNCTION(0, "GPIO13"),
117 MTK_FUNCTION(1, "COL1"),
118 MTK_FUNCTION(2, "EINT11_1X"),
119 MTK_FUNCTION(3, "SCL0_2X"),
120 MTK_FUNCTION(6, "TEST_IN4"),
121 MTK_FUNCTION(7, "TEST_OUT4")
122 ),
123 MTK_PIN(
124 PINCTRL_PIN(14, "COL2"),
125 "H4", "mt6397",
126 MTK_EINT_FUNCTION(2, 12),
127 MTK_FUNCTION(0, "GPIO14"),
128 MTK_FUNCTION(1, "COL2"),
129 MTK_FUNCTION(2, "EINT12_1X"),
130 MTK_FUNCTION(3, "SDA0_2X"),
131 MTK_FUNCTION(6, "TEST_IN5"),
132 MTK_FUNCTION(7, "TEST_OUT5")
133 ),
134 MTK_PIN(
135 PINCTRL_PIN(15, "COL3"),
136 "G2", "mt6397",
137 MTK_EINT_FUNCTION(2, 13),
138 MTK_FUNCTION(0, "GPIO15"),
139 MTK_FUNCTION(1, "COL3"),
140 MTK_FUNCTION(2, "EINT13_1X"),
141 MTK_FUNCTION(3, "SCL1_2X"),
142 MTK_FUNCTION(6, "TEST_IN6"),
143 MTK_FUNCTION(7, "TEST_OUT6")
144 ),
145 MTK_PIN(
146 PINCTRL_PIN(16, "COL4"),
147 "F2", "mt6397",
148 MTK_EINT_FUNCTION(2, 14),
149 MTK_FUNCTION(0, "GPIO16"),
150 MTK_FUNCTION(1, "COL4"),
151 MTK_FUNCTION(2, "EINT14_1X"),
152 MTK_FUNCTION(3, "SDA1_2X"),
153 MTK_FUNCTION(6, "TEST_IN7"),
154 MTK_FUNCTION(7, "TEST_OUT7")
155 ),
156 MTK_PIN(
157 PINCTRL_PIN(17, "COL5"),
158 "G7", "mt6397",
159 MTK_EINT_FUNCTION(2, 15),
160 MTK_FUNCTION(0, "GPIO17"),
161 MTK_FUNCTION(1, "COL5"),
162 MTK_FUNCTION(2, "EINT15_1X"),
163 MTK_FUNCTION(3, "SCL2_2X"),
164 MTK_FUNCTION(6, "TEST_IN8"),
165 MTK_FUNCTION(7, "TEST_OUT8")
166 ),
167 MTK_PIN(
168 PINCTRL_PIN(18, "COL6"),
169 "J6", "mt6397",
170 MTK_EINT_FUNCTION(2, 16),
171 MTK_FUNCTION(0, "GPIO18"),
172 MTK_FUNCTION(1, "COL6"),
173 MTK_FUNCTION(2, "EINT16_1X"),
174 MTK_FUNCTION(3, "SDA2_2X"),
175 MTK_FUNCTION(4, "GPIO32K_0"),
176 MTK_FUNCTION(5, "GPIO26M_0"),
177 MTK_FUNCTION(6, "TEST_IN9"),
178 MTK_FUNCTION(7, "TEST_OUT9")
179 ),
180 MTK_PIN(
181 PINCTRL_PIN(19, "COL7"),
182 "J5", "mt6397",
183 MTK_EINT_FUNCTION(2, 17),
184 MTK_FUNCTION(0, "GPIO19"),
185 MTK_FUNCTION(1, "COL7"),
186 MTK_FUNCTION(2, "EINT17_1X"),
187 MTK_FUNCTION(3, "PWM2_3X"),
188 MTK_FUNCTION(4, "GPIO32K_1"),
189 MTK_FUNCTION(5, "GPIO26M_1"),
190 MTK_FUNCTION(6, "TEST_IN10"),
191 MTK_FUNCTION(7, "TEST_OUT10")
192 ),
193 MTK_PIN(
194 PINCTRL_PIN(20, "ROW0"),
195 "L7", "mt6397",
196 MTK_EINT_FUNCTION(2, 18),
197 MTK_FUNCTION(0, "GPIO20"),
198 MTK_FUNCTION(1, "ROW0"),
199 MTK_FUNCTION(2, "EINT18_1X"),
200 MTK_FUNCTION(3, "SCL0_3X"),
201 MTK_FUNCTION(6, "TEST_IN11"),
202 MTK_FUNCTION(7, "TEST_OUT11")
203 ),
204 MTK_PIN(
205 PINCTRL_PIN(21, "ROW1"),
206 "P1", "mt6397",
207 MTK_EINT_FUNCTION(2, 19),
208 MTK_FUNCTION(0, "GPIO21"),
209 MTK_FUNCTION(1, "ROW1"),
210 MTK_FUNCTION(2, "EINT19_1X"),
211 MTK_FUNCTION(3, "SDA0_3X"),
212 MTK_FUNCTION(4, "AUD_TSTCK"),
213 MTK_FUNCTION(6, "TEST_IN12"),
214 MTK_FUNCTION(7, "TEST_OUT12")
215 ),
216 MTK_PIN(
217 PINCTRL_PIN(22, "ROW2"),
218 "J8", "mt6397",
219 MTK_EINT_FUNCTION(2, 20),
220 MTK_FUNCTION(0, "GPIO22"),
221 MTK_FUNCTION(1, "ROW2"),
222 MTK_FUNCTION(2, "EINT20_1X"),
223 MTK_FUNCTION(3, "SCL1_3X"),
224 MTK_FUNCTION(6, "TEST_IN13"),
225 MTK_FUNCTION(7, "TEST_OUT13")
226 ),
227 MTK_PIN(
228 PINCTRL_PIN(23, "ROW3"),
229 "J7", "mt6397",
230 MTK_EINT_FUNCTION(2, 21),
231 MTK_FUNCTION(0, "GPIO23"),
232 MTK_FUNCTION(1, "ROW3"),
233 MTK_FUNCTION(2, "EINT21_1X"),
234 MTK_FUNCTION(3, "SDA1_3X"),
235 MTK_FUNCTION(6, "TEST_IN14"),
236 MTK_FUNCTION(7, "TEST_OUT14")
237 ),
238 MTK_PIN(
239 PINCTRL_PIN(24, "ROW4"),
240 "L5", "mt6397",
241 MTK_EINT_FUNCTION(2, 22),
242 MTK_FUNCTION(0, "GPIO24"),
243 MTK_FUNCTION(1, "ROW4"),
244 MTK_FUNCTION(2, "EINT22_1X"),
245 MTK_FUNCTION(3, "SCL2_3X"),
246 MTK_FUNCTION(6, "TEST_IN15"),
247 MTK_FUNCTION(7, "TEST_OUT15")
248 ),
249 MTK_PIN(
250 PINCTRL_PIN(25, "ROW5"),
251 "N6", "mt6397",
252 MTK_EINT_FUNCTION(2, 23),
253 MTK_FUNCTION(0, "GPIO25"),
254 MTK_FUNCTION(1, "ROW5"),
255 MTK_FUNCTION(2, "EINT23_1X"),
256 MTK_FUNCTION(3, "SDA2_3X"),
257 MTK_FUNCTION(6, "TEST_IN16"),
258 MTK_FUNCTION(7, "TEST_OUT16")
259 ),
260 MTK_PIN(
261 PINCTRL_PIN(26, "ROW6"),
262 "L6", "mt6397",
263 MTK_EINT_FUNCTION(2, 24),
264 MTK_FUNCTION(0, "GPIO26"),
265 MTK_FUNCTION(1, "ROW6"),
266 MTK_FUNCTION(2, "EINT24_1X"),
267 MTK_FUNCTION(3, "PWM3_3X"),
268 MTK_FUNCTION(4, "GPIO32K_2"),
269 MTK_FUNCTION(5, "GPIO26M_2"),
270 MTK_FUNCTION(6, "TEST_IN17"),
271 MTK_FUNCTION(7, "TEST_OUT17")
272 ),
273 MTK_PIN(
274 PINCTRL_PIN(27, "ROW7"),
275 "P2", "mt6397",
276 MTK_EINT_FUNCTION(2, 3),
277 MTK_FUNCTION(0, "GPIO27"),
278 MTK_FUNCTION(1, "ROW7"),
279 MTK_FUNCTION(2, "EINT3_1X"),
280 MTK_FUNCTION(3, "CBUS"),
281 MTK_FUNCTION(4, "GPIO32K_3"),
282 MTK_FUNCTION(5, "GPIO26M_3"),
283 MTK_FUNCTION(6, "TEST_IN18"),
284 MTK_FUNCTION(7, "TEST_OUT18")
285 ),
286 MTK_PIN(
287 PINCTRL_PIN(28, "PWM1(VMSEL1)"),
288 "J4", "mt6397",
289 MTK_EINT_FUNCTION(2, 4),
290 MTK_FUNCTION(0, "GPIO28"),
291 MTK_FUNCTION(1, "PWM1"),
292 MTK_FUNCTION(2, "EINT4_1X"),
293 MTK_FUNCTION(4, "GPIO32K_4"),
294 MTK_FUNCTION(5, "GPIO26M_4"),
295 MTK_FUNCTION(6, "TEST_IN19"),
296 MTK_FUNCTION(7, "TEST_OUT19")
297 ),
298 MTK_PIN(
299 PINCTRL_PIN(29, "PWM2(VMSEL2)"),
300 "N5", "mt6397",
301 MTK_EINT_FUNCTION(2, 5),
302 MTK_FUNCTION(0, "GPIO29"),
303 MTK_FUNCTION(1, "PWM2"),
304 MTK_FUNCTION(2, "EINT5_1X"),
305 MTK_FUNCTION(4, "GPIO32K_5"),
306 MTK_FUNCTION(5, "GPIO26M_5"),
307 MTK_FUNCTION(6, "TEST_IN20"),
308 MTK_FUNCTION(7, "TEST_OUT20")
309 ),
310 MTK_PIN(
311 PINCTRL_PIN(30, "PWM3(PWM)"),
312 "R3", "mt6397",
313 MTK_EINT_FUNCTION(2, 6),
314 MTK_FUNCTION(0, "GPIO30"),
315 MTK_FUNCTION(1, "PWM3"),
316 MTK_FUNCTION(2, "EINT6_1X"),
317 MTK_FUNCTION(3, "COL0"),
318 MTK_FUNCTION(4, "GPIO32K_6"),
319 MTK_FUNCTION(5, "GPIO26M_6"),
320 MTK_FUNCTION(6, "TEST_IN21"),
321 MTK_FUNCTION(7, "TEST_OUT21")
322 ),
323 MTK_PIN(
324 PINCTRL_PIN(31, "SCL0"),
325 "N1", "mt6397",
326 MTK_EINT_FUNCTION(2, 7),
327 MTK_FUNCTION(0, "GPIO31"),
328 MTK_FUNCTION(1, "SCL0"),
329 MTK_FUNCTION(2, "EINT7_1X"),
330 MTK_FUNCTION(3, "PWM1_2X"),
331 MTK_FUNCTION(6, "TEST_IN22"),
332 MTK_FUNCTION(7, "TEST_OUT22")
333 ),
334 MTK_PIN(
335 PINCTRL_PIN(32, "SDA0"),
336 "N3", "mt6397",
337 MTK_EINT_FUNCTION(2, 8),
338 MTK_FUNCTION(0, "GPIO32"),
339 MTK_FUNCTION(1, "SDA0"),
340 MTK_FUNCTION(2, "EINT8_1X"),
341 MTK_FUNCTION(6, "TEST_IN23"),
342 MTK_FUNCTION(7, "TEST_OUT23")
343 ),
344 MTK_PIN(
345 PINCTRL_PIN(33, "SCL1"),
346 "T1", "mt6397",
347 MTK_EINT_FUNCTION(2, 9),
348 MTK_FUNCTION(0, "GPIO33"),
349 MTK_FUNCTION(1, "SCL1"),
350 MTK_FUNCTION(2, "EINT9_1X"),
351 MTK_FUNCTION(3, "PWM2_2X"),
352 MTK_FUNCTION(6, "TEST_IN24"),
353 MTK_FUNCTION(7, "TEST_OUT24")
354 ),
355 MTK_PIN(
356 PINCTRL_PIN(34, "SDA1"),
357 "T2", "mt6397",
358 MTK_EINT_FUNCTION(2, 0),
359 MTK_FUNCTION(0, "GPIO34"),
360 MTK_FUNCTION(1, "SDA1"),
361 MTK_FUNCTION(2, "EINT0_1X"),
362 MTK_FUNCTION(6, "TEST_IN25"),
363 MTK_FUNCTION(7, "TEST_OUT25")
364 ),
365 MTK_PIN(
366 PINCTRL_PIN(35, "SCL2"),
367 "T3", "mt6397",
368 MTK_EINT_FUNCTION(2, 1),
369 MTK_FUNCTION(0, "GPIO35"),
370 MTK_FUNCTION(1, "SCL2"),
371 MTK_FUNCTION(2, "EINT1_1X"),
372 MTK_FUNCTION(3, "PWM3_2X"),
373 MTK_FUNCTION(6, "TEST_IN26"),
374 MTK_FUNCTION(7, "TEST_OUT26")
375 ),
376 MTK_PIN(
377 PINCTRL_PIN(36, "SDA2"),
378 "U2", "mt6397",
379 MTK_EINT_FUNCTION(2, 2),
380 MTK_FUNCTION(0, "GPIO36"),
381 MTK_FUNCTION(1, "SDA2"),
382 MTK_FUNCTION(2, "EINT2_1X"),
383 MTK_FUNCTION(6, "TEST_IN27"),
384 MTK_FUNCTION(7, "TEST_OUT27")
385 ),
386 MTK_PIN(
387 PINCTRL_PIN(37, "HDMISD"),
388 "H6", "mt6397",
389 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
390 MTK_FUNCTION(0, "GPIO37"),
391 MTK_FUNCTION(1, "HDMISD"),
392 MTK_FUNCTION(6, "TEST_IN28"),
393 MTK_FUNCTION(7, "TEST_OUT28")
394 ),
395 MTK_PIN(
396 PINCTRL_PIN(38, "HDMISCK"),
397 "H5", "mt6397",
398 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
399 MTK_FUNCTION(0, "GPIO38"),
400 MTK_FUNCTION(1, "HDMISCK"),
401 MTK_FUNCTION(6, "TEST_IN29"),
402 MTK_FUNCTION(7, "TEST_OUT29")
403 ),
404 MTK_PIN(
405 PINCTRL_PIN(39, "HTPLG"),
406 "H7", "mt6397",
407 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
408 MTK_FUNCTION(0, "GPIO39"),
409 MTK_FUNCTION(1, "HTPLG"),
410 MTK_FUNCTION(6, "TEST_IN30"),
411 MTK_FUNCTION(7, "TEST_OUT30")
412 ),
413 MTK_PIN(
414 PINCTRL_PIN(40, "CEC"),
415 "J9", "mt6397",
416 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
417 MTK_FUNCTION(0, "GPIO40"),
418 MTK_FUNCTION(1, "CEC"),
419 MTK_FUNCTION(6, "TEST_IN31"),
420 MTK_FUNCTION(7, "TEST_OUT31")
421 ),
422};
423
424#endif /* __PINCTRL_MTK_MT6397_H */
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
new file mode 100644
index 000000000000..212559c147f8
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-mt8127.h
@@ -0,0 +1,1318 @@
1#ifndef __PINCTRL_MTK_MT8127_H
2#define __PINCTRL_MTK_MT8127_H
3
4#include <linux/pinctrl/pinctrl.h>
5#include "pinctrl-mtk-common.h"
6
7static const struct mtk_desc_pin mtk_pins_mt8127[] = {
8 MTK_PIN(
9 PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
10 "P22", "mt8127",
11 MTK_EINT_FUNCTION(0, 22),
12 MTK_FUNCTION(0, "GPIO0"),
13 MTK_FUNCTION(1, "PWRAP_SPIDO"),
14 MTK_FUNCTION(2, "PWRAP_SPIDI")
15 ),
16 MTK_PIN(
17 PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
18 "M22", "mt8127",
19 MTK_EINT_FUNCTION(0, 23),
20 MTK_FUNCTION(0, "GPIO1"),
21 MTK_FUNCTION(1, "PWRAP_SPIDI"),
22 MTK_FUNCTION(2, "PWRAP_SPIDO")
23 ),
24 MTK_PIN(
25 PINCTRL_PIN(2, "PWRAP_INT"),
26 "L23", "mt8127",
27 MTK_EINT_FUNCTION(0, 24),
28 MTK_FUNCTION(0, "GPIO2")
29 ),
30 MTK_PIN(
31 PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
32 "N23", "mt8127",
33 MTK_EINT_FUNCTION(0, 25),
34 MTK_FUNCTION(0, "GPIO3"),
35 MTK_FUNCTION(1, "PWRAP_SPICK_I")
36 ),
37 MTK_PIN(
38 PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
39 "N22", "mt8127",
40 MTK_EINT_FUNCTION(0, 26),
41 MTK_FUNCTION(0, "GPIO4"),
42 MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
43 ),
44 MTK_PIN(
45 PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
46 "L19", "mt8127",
47 MTK_EINT_FUNCTION(0, 27),
48 MTK_FUNCTION(0, "GPIO5"),
49 MTK_FUNCTION(1, "PWRAP_SPICK2_I"),
50 MTK_FUNCTION(2, "ANT_SEL1"),
51 MTK_FUNCTION(3, "VDEC_TEST_CK"),
52 MTK_FUNCTION(7, "DBG_MON_B[0]")
53 ),
54 MTK_PIN(
55 PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
56 "M23", "mt8127",
57 MTK_EINT_FUNCTION(0, 28),
58 MTK_FUNCTION(0, "GPIO6"),
59 MTK_FUNCTION(1, "PWRAP_SPICS2_B_I"),
60 MTK_FUNCTION(2, "ANT_SEL0"),
61 MTK_FUNCTION(3, "MM_TEST_CK"),
62 MTK_FUNCTION(7, "DBG_MON_B[1]")
63 ),
64 MTK_PIN(
65 PINCTRL_PIN(7, "AUD_CLK_MOSI"),
66 "K23", "mt8127",
67 MTK_EINT_FUNCTION(0, 29),
68 MTK_FUNCTION(0, "GPIO7"),
69 MTK_FUNCTION(1, "AUD_CLK"),
70 MTK_FUNCTION(2, "ADC_CK")
71 ),
72 MTK_PIN(
73 PINCTRL_PIN(8, "AUD_DAT_MISO"),
74 "K24", "mt8127",
75 MTK_EINT_FUNCTION(0, 30),
76 MTK_FUNCTION(0, "GPIO8"),
77 MTK_FUNCTION(1, "AUD_MISO"),
78 MTK_FUNCTION(2, "ADC_DAT_IN"),
79 MTK_FUNCTION(3, "AUD_MOSI")
80 ),
81 MTK_PIN(
82 PINCTRL_PIN(9, "AUD_DAT_MOSI"),
83 "K22", "mt8127",
84 MTK_EINT_FUNCTION(0, 31),
85 MTK_FUNCTION(0, "GPIO9"),
86 MTK_FUNCTION(1, "AUD_MOSI"),
87 MTK_FUNCTION(2, "ADC_WS"),
88 MTK_FUNCTION(3, "AUD_MISO")
89 ),
90 MTK_PIN(
91 PINCTRL_PIN(10, "RTC32K_CK"),
92 "R21", "mt8127",
93 MTK_EINT_FUNCTION(0, 32),
94 MTK_FUNCTION(0, "GPIO10"),
95 MTK_FUNCTION(1, "RTC32K_CK")
96 ),
97 MTK_PIN(
98 PINCTRL_PIN(11, "WATCHDOG"),
99 "P24", "mt8127",
100 MTK_EINT_FUNCTION(0, 33),
101 MTK_FUNCTION(0, "GPIO11"),
102 MTK_FUNCTION(1, "WATCHDOG")
103 ),
104 MTK_PIN(
105 PINCTRL_PIN(12, "SRCLKENA"),
106 "R22", "mt8127",
107 MTK_EINT_FUNCTION(0, 34),
108 MTK_FUNCTION(0, "GPIO12"),
109 MTK_FUNCTION(1, "SRCLKENA")
110 ),
111 MTK_PIN(
112 PINCTRL_PIN(13, "SRCLKENAI"),
113 "P23", "mt8127",
114 MTK_EINT_FUNCTION(0, 35),
115 MTK_FUNCTION(0, "GPIO13"),
116 MTK_FUNCTION(1, "SRCLKENAI")
117 ),
118 MTK_PIN(
119 PINCTRL_PIN(14, "URXD2"),
120 "U19", "mt8127",
121 MTK_EINT_FUNCTION(0, 36),
122 MTK_FUNCTION(0, "GPIO14"),
123 MTK_FUNCTION(1, "URXD2"),
124 MTK_FUNCTION(2, "DPI_D5"),
125 MTK_FUNCTION(3, "UTXD2"),
126 MTK_FUNCTION(5, "SRCCLKENAI2"),
127 MTK_FUNCTION(6, "KROW4")
128 ),
129 MTK_PIN(
130 PINCTRL_PIN(15, "UTXD2"),
131 "U20", "mt8127",
132 MTK_EINT_FUNCTION(0, 37),
133 MTK_FUNCTION(0, "GPIO15"),
134 MTK_FUNCTION(1, "UTXD2"),
135 MTK_FUNCTION(2, "DPI_HSYNC"),
136 MTK_FUNCTION(3, "URXD2"),
137 MTK_FUNCTION(6, "KROW5")
138 ),
139 MTK_PIN(
140 PINCTRL_PIN(16, "URXD3"),
141 "U18", "mt8127",
142 MTK_EINT_FUNCTION(0, 38),
143 MTK_FUNCTION(0, "GPIO16"),
144 MTK_FUNCTION(1, "URXD3"),
145 MTK_FUNCTION(2, "DPI_DE"),
146 MTK_FUNCTION(3, "UTXD3"),
147 MTK_FUNCTION(4, "UCTS2"),
148 MTK_FUNCTION(5, "PWM3"),
149 MTK_FUNCTION(6, "KROW6")
150 ),
151 MTK_PIN(
152 PINCTRL_PIN(17, "UTXD3"),
153 "R18", "mt8127",
154 MTK_EINT_FUNCTION(0, 39),
155 MTK_FUNCTION(0, "GPIO17"),
156 MTK_FUNCTION(1, "UTXD3"),
157 MTK_FUNCTION(2, "DPI_VSYNC"),
158 MTK_FUNCTION(3, "URXD3"),
159 MTK_FUNCTION(4, "URTS2"),
160 MTK_FUNCTION(5, "PWM4"),
161 MTK_FUNCTION(6, "KROW7")
162 ),
163 MTK_PIN(
164 PINCTRL_PIN(18, "PCM_CLK"),
165 "U22", "mt8127",
166 MTK_EINT_FUNCTION(0, 40),
167 MTK_FUNCTION(0, "GPIO18"),
168 MTK_FUNCTION(1, "PCM_CLK0"),
169 MTK_FUNCTION(2, "DPI_D4"),
170 MTK_FUNCTION(3, "I2SIN1_BCK0"),
171 MTK_FUNCTION(4, "I2SOUT_BCK"),
172 MTK_FUNCTION(5, "CONN_DSP_JCK"),
173 MTK_FUNCTION(6, "IR"),
174 MTK_FUNCTION(7, "DBG_MON_A[0]")
175 ),
176 MTK_PIN(
177 PINCTRL_PIN(19, "PCM_SYNC"),
178 "U23", "mt8127",
179 MTK_EINT_FUNCTION(0, 41),
180 MTK_FUNCTION(0, "GPIO19"),
181 MTK_FUNCTION(1, "PCM_SYNC"),
182 MTK_FUNCTION(2, "DPI_D3"),
183 MTK_FUNCTION(3, "I2SIN1_LRCK"),
184 MTK_FUNCTION(4, "I2SOUT_LRCK"),
185 MTK_FUNCTION(5, "CONN_DSP_JINTP"),
186 MTK_FUNCTION(6, "EXT_COL"),
187 MTK_FUNCTION(7, "DBG_MON_A[1]")
188 ),
189 MTK_PIN(
190 PINCTRL_PIN(20, "PCM_RX"),
191 "V22", "mt8127",
192 MTK_EINT_FUNCTION(0, 42),
193 MTK_FUNCTION(0, "GPIO20"),
194 MTK_FUNCTION(1, "PCM_RX"),
195 MTK_FUNCTION(2, "DPI_D1"),
196 MTK_FUNCTION(3, "I2SIN1_DATA_IN"),
197 MTK_FUNCTION(4, "PCM_TX"),
198 MTK_FUNCTION(5, "CONN_DSP_JDI"),
199 MTK_FUNCTION(6, "EXT_MDIO"),
200 MTK_FUNCTION(7, "DBG_MON_A[2]")
201 ),
202 MTK_PIN(
203 PINCTRL_PIN(21, "PCM_TX"),
204 "U21", "mt8127",
205 MTK_EINT_FUNCTION(0, 43),
206 MTK_FUNCTION(0, "GPIO21"),
207 MTK_FUNCTION(1, "PCM_TX"),
208 MTK_FUNCTION(2, "DPI_D2"),
209 MTK_FUNCTION(3, "I2SOUT_DATA_OUT"),
210 MTK_FUNCTION(4, "PCM_RX"),
211 MTK_FUNCTION(5, "CONN_DSP_JMS"),
212 MTK_FUNCTION(6, "EXT_MDC"),
213 MTK_FUNCTION(7, "DBG_MON_A[3]")
214 ),
215 MTK_PIN(
216 PINCTRL_PIN(22, "EINT0"),
217 "AB19", "mt8127",
218 MTK_EINT_FUNCTION(0, 0),
219 MTK_FUNCTION(0, "GPIO22"),
220 MTK_FUNCTION(1, "PWM1"),
221 MTK_FUNCTION(2, "DPI_CK"),
222 MTK_FUNCTION(4, "EXT_TXD0"),
223 MTK_FUNCTION(5, "CONN_DSP_JDO"),
224 MTK_FUNCTION(7, "DBG_MON_A[4]")
225 ),
226 MTK_PIN(
227 PINCTRL_PIN(23, "EINT1"),
228 "AA21", "mt8127",
229 MTK_EINT_FUNCTION(0, 1),
230 MTK_FUNCTION(0, "GPIO23"),
231 MTK_FUNCTION(1, "PWM2"),
232 MTK_FUNCTION(2, "DPI_D12"),
233 MTK_FUNCTION(4, "EXT_TXD1"),
234 MTK_FUNCTION(5, "CONN_MCU_TDO"),
235 MTK_FUNCTION(7, "DBG_MON_A[5]")
236 ),
237 MTK_PIN(
238 PINCTRL_PIN(24, "EINT2"),
239 "AA19", "mt8127",
240 MTK_EINT_FUNCTION(0, 2),
241 MTK_FUNCTION(0, "GPIO24"),
242 MTK_FUNCTION(1, "CLKM0"),
243 MTK_FUNCTION(2, "DPI_D13"),
244 MTK_FUNCTION(4, "EXT_TXD2"),
245 MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
246 MTK_FUNCTION(6, "KCOL4"),
247 MTK_FUNCTION(7, "DBG_MON_A[6]")
248 ),
249 MTK_PIN(
250 PINCTRL_PIN(25, "EINT3"),
251 "Y19", "mt8127",
252 MTK_EINT_FUNCTION(0, 3),
253 MTK_FUNCTION(0, "GPIO25"),
254 MTK_FUNCTION(1, "CLKM1"),
255 MTK_FUNCTION(2, "DPI_D14"),
256 MTK_FUNCTION(3, "SPI_MI"),
257 MTK_FUNCTION(4, "EXT_TXD3"),
258 MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
259 MTK_FUNCTION(6, "KCOL5"),
260 MTK_FUNCTION(7, "DBG_MON_A[7]")
261 ),
262 MTK_PIN(
263 PINCTRL_PIN(26, "EINT4"),
264 "V21", "mt8127",
265 MTK_EINT_FUNCTION(0, 4),
266 MTK_FUNCTION(0, "GPIO26"),
267 MTK_FUNCTION(1, "CLKM2"),
268 MTK_FUNCTION(2, "DPI_D15"),
269 MTK_FUNCTION(3, "SPI_MO"),
270 MTK_FUNCTION(4, "EXT_TXC"),
271 MTK_FUNCTION(5, "CONN_MCU_TCK0"),
272 MTK_FUNCTION(6, "CONN_MCU_AICE_JCKC"),
273 MTK_FUNCTION(7, "DBG_MON_A[8]")
274 ),
275 MTK_PIN(
276 PINCTRL_PIN(27, "EINT5"),
277 "AB22", "mt8127",
278 MTK_EINT_FUNCTION(0, 5),
279 MTK_FUNCTION(0, "GPIO27"),
280 MTK_FUNCTION(1, "UCTS2"),
281 MTK_FUNCTION(2, "DPI_D16"),
282 MTK_FUNCTION(3, "SPI_CS"),
283 MTK_FUNCTION(4, "EXT_RXER"),
284 MTK_FUNCTION(5, "CONN_MCU_TDI"),
285 MTK_FUNCTION(6, "KCOL6"),
286 MTK_FUNCTION(7, "DBG_MON_A[9]")
287 ),
288 MTK_PIN(
289 PINCTRL_PIN(28, "EINT6"),
290 "AA23", "mt8127",
291 MTK_EINT_FUNCTION(0, 6),
292 MTK_FUNCTION(0, "GPIO28"),
293 MTK_FUNCTION(1, "URTS2"),
294 MTK_FUNCTION(2, "DPI_D17"),
295 MTK_FUNCTION(3, "SPI_CK"),
296 MTK_FUNCTION(4, "EXT_RXC"),
297 MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
298 MTK_FUNCTION(6, "KCOL7"),
299 MTK_FUNCTION(7, "DBG_MON_A[10]")
300 ),
301 MTK_PIN(
302 PINCTRL_PIN(29, "EINT7"),
303 "Y23", "mt8127",
304 MTK_EINT_FUNCTION(0, 7),
305 MTK_FUNCTION(0, "GPIO29"),
306 MTK_FUNCTION(1, "UCTS3"),
307 MTK_FUNCTION(2, "DPI_D6"),
308 MTK_FUNCTION(3, "SDA1"),
309 MTK_FUNCTION(4, "EXT_RXDV"),
310 MTK_FUNCTION(5, "CONN_MCU_TMS"),
311 MTK_FUNCTION(6, "CONN_MCU_AICE_JMSC"),
312 MTK_FUNCTION(7, "DBG_MON_A[11]")
313 ),
314 MTK_PIN(
315 PINCTRL_PIN(30, "EINT8"),
316 "Y24", "mt8127",
317 MTK_EINT_FUNCTION(0, 8),
318 MTK_FUNCTION(0, "GPIO30"),
319 MTK_FUNCTION(1, "URTS3"),
320 MTK_FUNCTION(2, "CLKM3"),
321 MTK_FUNCTION(3, "SCL1"),
322 MTK_FUNCTION(4, "EXT_RXD0"),
323 MTK_FUNCTION(5, "ANT_SEL0"),
324 MTK_FUNCTION(6, "DPI_D7"),
325 MTK_FUNCTION(7, "DBG_MON_B[2]")
326 ),
327 MTK_PIN(
328 PINCTRL_PIN(31, "EINT9"),
329 "W23", "mt8127",
330 MTK_EINT_FUNCTION(0, 9),
331 MTK_FUNCTION(0, "GPIO31"),
332 MTK_FUNCTION(1, "CLKM4"),
333 MTK_FUNCTION(2, "SDA2"),
334 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
335 MTK_FUNCTION(4, "EXT_RXD1"),
336 MTK_FUNCTION(5, "ANT_SEL1"),
337 MTK_FUNCTION(6, "DPI_D8"),
338 MTK_FUNCTION(7, "DBG_MON_B[3]")
339 ),
340 MTK_PIN(
341 PINCTRL_PIN(32, "EINT10"),
342 "W24", "mt8127",
343 MTK_EINT_FUNCTION(0, 10),
344 MTK_FUNCTION(0, "GPIO32"),
345 MTK_FUNCTION(1, "CLKM5"),
346 MTK_FUNCTION(2, "SCL2"),
347 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
348 MTK_FUNCTION(4, "EXT_RXD2"),
349 MTK_FUNCTION(5, "ANT_SEL2"),
350 MTK_FUNCTION(6, "DPI_D9"),
351 MTK_FUNCTION(7, "DBG_MON_B[4]")
352 ),
353 MTK_PIN(
354 PINCTRL_PIN(33, "KPROW0"),
355 "AB24", "mt8127",
356 MTK_EINT_FUNCTION(0, 44),
357 MTK_FUNCTION(0, "GPIO33"),
358 MTK_FUNCTION(1, "KROW0"),
359 MTK_FUNCTION(4, "IMG_TEST_CK"),
360 MTK_FUNCTION(7, "DBG_MON_A[12]")
361 ),
362 MTK_PIN(
363 PINCTRL_PIN(34, "KPROW1"),
364 "AC24", "mt8127",
365 MTK_EINT_FUNCTION(0, 45),
366 MTK_FUNCTION(0, "GPIO34"),
367 MTK_FUNCTION(1, "KROW1"),
368 MTK_FUNCTION(2, "IDDIG"),
369 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
370 MTK_FUNCTION(4, "MFG_TEST_CK"),
371 MTK_FUNCTION(7, "DBG_MON_B[5]")
372 ),
373 MTK_PIN(
374 PINCTRL_PIN(35, "KPROW2"),
375 "AD24", "mt8127",
376 MTK_EINT_FUNCTION(0, 46),
377 MTK_FUNCTION(0, "GPIO35"),
378 MTK_FUNCTION(1, "KROW2"),
379 MTK_FUNCTION(2, "DRV_VBUS"),
380 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
381 MTK_FUNCTION(4, "CONN_TEST_CK"),
382 MTK_FUNCTION(7, "DBG_MON_B[6]")
383 ),
384 MTK_PIN(
385 PINCTRL_PIN(36, "KPCOL0"),
386 "AB23", "mt8127",
387 MTK_EINT_FUNCTION(0, 47),
388 MTK_FUNCTION(0, "GPIO36"),
389 MTK_FUNCTION(1, "KCOL0"),
390 MTK_FUNCTION(7, "DBG_MON_A[13]")
391 ),
392 MTK_PIN(
393 PINCTRL_PIN(37, "KPCOL1"),
394 "AC22", "mt8127",
395 MTK_EINT_FUNCTION(0, 48),
396 MTK_FUNCTION(0, "GPIO37"),
397 MTK_FUNCTION(1, "KCOL1"),
398 MTK_FUNCTION(7, "DBG_MON_B[7]")
399 ),
400 MTK_PIN(
401 PINCTRL_PIN(38, "KPCOL2"),
402 "AC23", "mt8127",
403 MTK_EINT_FUNCTION(0, 49),
404 MTK_FUNCTION(0, "GPIO38"),
405 MTK_FUNCTION(1, "KCOL2"),
406 MTK_FUNCTION(2, "IDDIG"),
407 MTK_FUNCTION(3, "EXT_FRAME_SYNC"),
408 MTK_FUNCTION(7, "DBG_MON_B[8]")
409 ),
410 MTK_PIN(
411 PINCTRL_PIN(39, "JTMS"),
412 "V18", "mt8127",
413 MTK_EINT_FUNCTION(0, 50),
414 MTK_FUNCTION(0, "GPIO39"),
415 MTK_FUNCTION(1, "JTMS"),
416 MTK_FUNCTION(2, "CONN_MCU_TMS"),
417 MTK_FUNCTION(3, "CONN_MCU_AICE_JMSC")
418 ),
419 MTK_PIN(
420 PINCTRL_PIN(40, "JTCK"),
421 "AA18", "mt8127",
422 MTK_EINT_FUNCTION(0, 51),
423 MTK_FUNCTION(0, "GPIO40"),
424 MTK_FUNCTION(1, "JTCK"),
425 MTK_FUNCTION(2, "CONN_MCU_TCK1"),
426 MTK_FUNCTION(3, "CONN_MCU_AICE_JCKC")
427 ),
428 MTK_PIN(
429 PINCTRL_PIN(41, "JTDI"),
430 "W18", "mt8127",
431 MTK_EINT_FUNCTION(0, 52),
432 MTK_FUNCTION(0, "GPIO41"),
433 MTK_FUNCTION(1, "JTDI"),
434 MTK_FUNCTION(2, "CONN_MCU_TDI")
435 ),
436 MTK_PIN(
437 PINCTRL_PIN(42, "JTDO"),
438 "Y18", "mt8127",
439 MTK_EINT_FUNCTION(0, 53),
440 MTK_FUNCTION(0, "GPIO42"),
441 MTK_FUNCTION(1, "JTDO"),
442 MTK_FUNCTION(2, "CONN_MCU_TDO")
443 ),
444 MTK_PIN(
445 PINCTRL_PIN(43, "EINT11"),
446 "W22", "mt8127",
447 MTK_EINT_FUNCTION(0, 11),
448 MTK_FUNCTION(0, "GPIO43"),
449 MTK_FUNCTION(1, "CLKM4"),
450 MTK_FUNCTION(2, "PWM2"),
451 MTK_FUNCTION(3, "KROW3"),
452 MTK_FUNCTION(4, "ANT_SEL3"),
453 MTK_FUNCTION(5, "DPI_D10"),
454 MTK_FUNCTION(6, "EXT_RXD3"),
455 MTK_FUNCTION(7, "DBG_MON_B[9]")
456 ),
457 MTK_PIN(
458 PINCTRL_PIN(44, "EINT12"),
459 "V23", "mt8127",
460 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
461 MTK_FUNCTION(0, "GPIO44"),
462 MTK_FUNCTION(1, "CLKM5"),
463 MTK_FUNCTION(2, "PWM0"),
464 MTK_FUNCTION(3, "KCOL3"),
465 MTK_FUNCTION(4, "ANT_SEL4"),
466 MTK_FUNCTION(5, "DPI_D11"),
467 MTK_FUNCTION(6, "EXT_TXEN"),
468 MTK_FUNCTION(7, "DBG_MON_B[10]")
469 ),
470 MTK_PIN(
471 PINCTRL_PIN(45, "EINT13"),
472 "Y21", "mt8127",
473 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
474 MTK_FUNCTION(0, "GPIO45"),
475 MTK_FUNCTION(4, "ANT_SEL5"),
476 MTK_FUNCTION(5, "DPI_D0"),
477 MTK_FUNCTION(6, "SPDIF"),
478 MTK_FUNCTION(7, "DBG_MON_B[11]")
479 ),
480 MTK_PIN(
481 PINCTRL_PIN(46, "EINT14"),
482 "F23", "mt8127",
483 MTK_EINT_FUNCTION(0, 14),
484 MTK_FUNCTION(0, "GPIO46"),
485 MTK_FUNCTION(2, "DAC_DAT_OUT"),
486 MTK_FUNCTION(4, "ANT_SEL1"),
487 MTK_FUNCTION(5, "CONN_MCU_DBGACK_N"),
488 MTK_FUNCTION(6, "NCLE"),
489 MTK_FUNCTION(7, "DBG_MON_A[14]")
490 ),
491 MTK_PIN(
492 PINCTRL_PIN(47, "EINT15"),
493 "G23", "mt8127",
494 MTK_EINT_FUNCTION(0, 15),
495 MTK_FUNCTION(0, "GPIO47"),
496 MTK_FUNCTION(2, "DAC_WS"),
497 MTK_FUNCTION(4, "ANT_SEL2"),
498 MTK_FUNCTION(5, "CONN_MCU_DBGI_N"),
499 MTK_FUNCTION(6, "NCEB1"),
500 MTK_FUNCTION(7, "DBG_MON_A[15]")
501 ),
502 MTK_PIN(
503 PINCTRL_PIN(48, "EINT16"),
504 "H23", "mt8127",
505 MTK_EINT_FUNCTION(0, 16),
506 MTK_FUNCTION(0, "GPIO48"),
507 MTK_FUNCTION(2, "DAC_CK"),
508 MTK_FUNCTION(4, "ANT_SEL3"),
509 MTK_FUNCTION(5, "CONN_MCU_TRST_B"),
510 MTK_FUNCTION(6, "NCEB0"),
511 MTK_FUNCTION(7, "DBG_MON_A[16]")
512 ),
513 MTK_PIN(
514 PINCTRL_PIN(49, "EINT17"),
515 "J22", "mt8127",
516 MTK_EINT_FUNCTION(0, 17),
517 MTK_FUNCTION(0, "GPIO49"),
518 MTK_FUNCTION(1, "UCTS0"),
519 MTK_FUNCTION(3, "CLKM0"),
520 MTK_FUNCTION(4, "IDDIG"),
521 MTK_FUNCTION(5, "ANT_SEL4"),
522 MTK_FUNCTION(6, "NREB"),
523 MTK_FUNCTION(7, "DBG_MON_A[17]")
524 ),
525 MTK_PIN(
526 PINCTRL_PIN(50, "EINT18"),
527 "AD20", "mt8127",
528 MTK_EINT_FUNCTION(0, 18),
529 MTK_FUNCTION(0, "GPIO50"),
530 MTK_FUNCTION(1, "URTS0"),
531 MTK_FUNCTION(2, "CLKM3"),
532 MTK_FUNCTION(3, "I2SOUT_LRCK"),
533 MTK_FUNCTION(4, "DRV_VBUS"),
534 MTK_FUNCTION(5, "ANT_SEL3"),
535 MTK_FUNCTION(6, "ADC_CK"),
536 MTK_FUNCTION(7, "DBG_MON_B[12]")
537 ),
538 MTK_PIN(
539 PINCTRL_PIN(51, "EINT19"),
540 "AC21", "mt8127",
541 MTK_EINT_FUNCTION(0, 19),
542 MTK_FUNCTION(0, "GPIO51"),
543 MTK_FUNCTION(1, "UCTS1"),
544 MTK_FUNCTION(3, "I2SOUT_BCK"),
545 MTK_FUNCTION(4, "CLKM1"),
546 MTK_FUNCTION(5, "ANT_SEL4"),
547 MTK_FUNCTION(6, "ADC_DAT_IN"),
548 MTK_FUNCTION(7, "DBG_MON_B[13]")
549 ),
550 MTK_PIN(
551 PINCTRL_PIN(52, "EINT20"),
552 "V20", "mt8127",
553 MTK_EINT_FUNCTION(0, 20),
554 MTK_FUNCTION(0, "GPIO52"),
555 MTK_FUNCTION(1, "URTS1"),
556 MTK_FUNCTION(2, "PCM_TX"),
557 MTK_FUNCTION(3, "I2SOUT_DATA_OUT"),
558 MTK_FUNCTION(4, "CLKM2"),
559 MTK_FUNCTION(5, "ANT_SEL5"),
560 MTK_FUNCTION(6, "ADC_WS"),
561 MTK_FUNCTION(7, "DBG_MON_B[14]")
562 ),
563 MTK_PIN(
564 PINCTRL_PIN(53, "SPI_CS"),
565 "AD19", "mt8127",
566 MTK_EINT_FUNCTION(0, 54),
567 MTK_FUNCTION(0, "GPIO53"),
568 MTK_FUNCTION(1, "SPI_CS"),
569 MTK_FUNCTION(3, "I2SIN1_DATA_IN"),
570 MTK_FUNCTION(4, "ADC_CK"),
571 MTK_FUNCTION(7, "DBG_MON_B[15]")
572 ),
573 MTK_PIN(
574 PINCTRL_PIN(54, "SPI_CK"),
575 "AC18", "mt8127",
576 MTK_EINT_FUNCTION(0, 55),
577 MTK_FUNCTION(0, "GPIO54"),
578 MTK_FUNCTION(1, "SPI_CK"),
579 MTK_FUNCTION(3, "I2SIN1_LRCK"),
580 MTK_FUNCTION(4, "ADC_DAT_IN"),
581 MTK_FUNCTION(7, "DBG_MON_B[16]")
582 ),
583 MTK_PIN(
584 PINCTRL_PIN(55, "SPI_MI"),
585 "AC19", "mt8127",
586 MTK_EINT_FUNCTION(0, 56),
587 MTK_FUNCTION(0, "GPIO55"),
588 MTK_FUNCTION(1, "SPI_MI"),
589 MTK_FUNCTION(2, "SPI_MO"),
590 MTK_FUNCTION(3, "I2SIN1_BCK1"),
591 MTK_FUNCTION(4, "ADC_WS"),
592 MTK_FUNCTION(7, "DBG_MON_B[17]")
593 ),
594 MTK_PIN(
595 PINCTRL_PIN(56, "SPI_MO"),
596 "AD18", "mt8127",
597 MTK_EINT_FUNCTION(0, 57),
598 MTK_FUNCTION(0, "GPIO56"),
599 MTK_FUNCTION(1, "SPI_MO"),
600 MTK_FUNCTION(2, "SPI_MI"),
601 MTK_FUNCTION(7, "DBG_MON_B[18]")
602 ),
603 MTK_PIN(
604 PINCTRL_PIN(57, "SDA1"),
605 "AE23", "mt8127",
606 MTK_EINT_FUNCTION(0, 58),
607 MTK_FUNCTION(0, "GPIO57"),
608 MTK_FUNCTION(1, "SDA1")
609 ),
610 MTK_PIN(
611 PINCTRL_PIN(58, "SCL1"),
612 "AD23", "mt8127",
613 MTK_EINT_FUNCTION(0, 59),
614 MTK_FUNCTION(0, "GPIO58"),
615 MTK_FUNCTION(1, "SCL1")
616 ),
617 MTK_PIN(
618 PINCTRL_PIN(59, "DISP_PWM"),
619 "AC20", "mt8127",
620 MTK_EINT_FUNCTION(0, 60),
621 MTK_FUNCTION(0, "GPIO59"),
622 MTK_FUNCTION(1, "DISP_PWM"),
623 MTK_FUNCTION(2, "PWM1"),
624 MTK_FUNCTION(7, "DBG_MON_A[18]")
625 ),
626 MTK_PIN(
627 PINCTRL_PIN(60, "WB_RSTB"),
628 "AD7", "mt8127",
629 MTK_EINT_FUNCTION(0, 61),
630 MTK_FUNCTION(0, "GPIO60"),
631 MTK_FUNCTION(1, "WB_RSTB"),
632 MTK_FUNCTION(7, "DBG_MON_A[19]")
633 ),
634 MTK_PIN(
635 PINCTRL_PIN(61, "F2W_DATA"),
636 "Y10", "mt8127",
637 MTK_EINT_FUNCTION(0, 62),
638 MTK_FUNCTION(0, "GPIO61"),
639 MTK_FUNCTION(1, "F2W_DATA"),
640 MTK_FUNCTION(7, "DBG_MON_A[20]")
641 ),
642 MTK_PIN(
643 PINCTRL_PIN(62, "F2W_CLK"),
644 "W10", "mt8127",
645 MTK_EINT_FUNCTION(0, 63),
646 MTK_FUNCTION(0, "GPIO62"),
647 MTK_FUNCTION(1, "F2W_CK"),
648 MTK_FUNCTION(7, "DBG_MON_A[21]")
649 ),
650 MTK_PIN(
651 PINCTRL_PIN(63, "WB_SCLK"),
652 "AB7", "mt8127",
653 MTK_EINT_FUNCTION(0, 64),
654 MTK_FUNCTION(0, "GPIO63"),
655 MTK_FUNCTION(1, "WB_SCLK"),
656 MTK_FUNCTION(7, "DBG_MON_A[22]")
657 ),
658 MTK_PIN(
659 PINCTRL_PIN(64, "WB_SDATA"),
660 "AA7", "mt8127",
661 MTK_EINT_FUNCTION(0, 65),
662 MTK_FUNCTION(0, "GPIO64"),
663 MTK_FUNCTION(1, "WB_SDATA"),
664 MTK_FUNCTION(7, "DBG_MON_A[23]")
665 ),
666 MTK_PIN(
667 PINCTRL_PIN(65, "WB_SEN"),
668 "Y7", "mt8127",
669 MTK_EINT_FUNCTION(0, 66),
670 MTK_FUNCTION(0, "GPIO65"),
671 MTK_FUNCTION(1, "WB_SEN"),
672 MTK_FUNCTION(7, "DBG_MON_A[24]")
673 ),
674 MTK_PIN(
675 PINCTRL_PIN(66, "WB_CRTL0"),
676 "AA1", "mt8127",
677 MTK_EINT_FUNCTION(0, 67),
678 MTK_FUNCTION(0, "GPIO66"),
679 MTK_FUNCTION(1, "WB_CRTL0"),
680 MTK_FUNCTION(2, "DFD_NTRST_XI"),
681 MTK_FUNCTION(7, "DBG_MON_A[25]")
682 ),
683 MTK_PIN(
684 PINCTRL_PIN(67, "WB_CRTL1"),
685 "AA2", "mt8127",
686 MTK_EINT_FUNCTION(0, 68),
687 MTK_FUNCTION(0, "GPIO67"),
688 MTK_FUNCTION(1, "WB_CRTL1"),
689 MTK_FUNCTION(2, "DFD_TMS_XI"),
690 MTK_FUNCTION(7, "DBG_MON_A[26]")
691 ),
692 MTK_PIN(
693 PINCTRL_PIN(68, "WB_CRTL2"),
694 "Y1", "mt8127",
695 MTK_EINT_FUNCTION(0, 69),
696 MTK_FUNCTION(0, "GPIO68"),
697 MTK_FUNCTION(1, "WB_CRTL2"),
698 MTK_FUNCTION(2, "DFD_TCK_XI"),
699 MTK_FUNCTION(7, "DBG_MON_A[27]")
700 ),
701 MTK_PIN(
702 PINCTRL_PIN(69, "WB_CRTL3"),
703 "Y2", "mt8127",
704 MTK_EINT_FUNCTION(0, 70),
705 MTK_FUNCTION(0, "GPIO69"),
706 MTK_FUNCTION(1, "WB_CRTL3"),
707 MTK_FUNCTION(2, "DFD_TDI_XI"),
708 MTK_FUNCTION(7, "DBG_MON_A[28]")
709 ),
710 MTK_PIN(
711 PINCTRL_PIN(70, "WB_CRTL4"),
712 "Y3", "mt8127",
713 MTK_EINT_FUNCTION(0, 71),
714 MTK_FUNCTION(0, "GPIO70"),
715 MTK_FUNCTION(1, "WB_CRTL4"),
716 MTK_FUNCTION(2, "DFD_TDO"),
717 MTK_FUNCTION(7, "DBG_MON_A[29]")
718 ),
719 MTK_PIN(
720 PINCTRL_PIN(71, "WB_CRTL5"),
721 "Y4", "mt8127",
722 MTK_EINT_FUNCTION(0, 72),
723 MTK_FUNCTION(0, "GPIO71"),
724 MTK_FUNCTION(1, "WB_CRTL5"),
725 MTK_FUNCTION(7, "DBG_MON_A[30]")
726 ),
727 MTK_PIN(
728 PINCTRL_PIN(72, "I2S_DATA_IN"),
729 "K21", "mt8127",
730 MTK_EINT_FUNCTION(0, 73),
731 MTK_FUNCTION(0, "GPIO72"),
732 MTK_FUNCTION(1, "I2SIN1_DATA_IN"),
733 MTK_FUNCTION(2, "PCM_RX"),
734 MTK_FUNCTION(3, "I2SOUT_DATA_OUT"),
735 MTK_FUNCTION(4, "DAC_DAT_OUT"),
736 MTK_FUNCTION(5, "PWM0"),
737 MTK_FUNCTION(6, "ADC_CK"),
738 MTK_FUNCTION(7, "DBG_MON_B[19]")
739 ),
740 MTK_PIN(
741 PINCTRL_PIN(73, "I2S_LRCK"),
742 "L21", "mt8127",
743 MTK_EINT_FUNCTION(0, 74),
744 MTK_FUNCTION(0, "GPIO73"),
745 MTK_FUNCTION(1, "I2SIN1_LRCK"),
746 MTK_FUNCTION(2, "PCM_SYNC"),
747 MTK_FUNCTION(3, "I2SOUT_LRCK"),
748 MTK_FUNCTION(4, "DAC_WS"),
749 MTK_FUNCTION(5, "PWM3"),
750 MTK_FUNCTION(6, "ADC_DAT_IN"),
751 MTK_FUNCTION(7, "DBG_MON_B[20]")
752 ),
753 MTK_PIN(
754 PINCTRL_PIN(74, "I2S_BCK"),
755 "L20", "mt8127",
756 MTK_EINT_FUNCTION(0, 75),
757 MTK_FUNCTION(0, "GPIO74"),
758 MTK_FUNCTION(1, "I2SIN1_BCK2"),
759 MTK_FUNCTION(2, "PCM_CLK1"),
760 MTK_FUNCTION(3, "I2SOUT_BCK"),
761 MTK_FUNCTION(4, "DAC_CK"),
762 MTK_FUNCTION(5, "PWM4"),
763 MTK_FUNCTION(6, "ADC_WS"),
764 MTK_FUNCTION(7, "DBG_MON_B[21]")
765 ),
766 MTK_PIN(
767 PINCTRL_PIN(75, "SDA0"),
768 "W3", "mt8127",
769 MTK_EINT_FUNCTION(0, 76),
770 MTK_FUNCTION(0, "GPIO75"),
771 MTK_FUNCTION(1, "SDA0")
772 ),
773 MTK_PIN(
774 PINCTRL_PIN(76, "SCL0"),
775 "W4", "mt8127",
776 MTK_EINT_FUNCTION(0, 77),
777 MTK_FUNCTION(0, "GPIO76"),
778 MTK_FUNCTION(1, "SCL0")
779 ),
780 MTK_PIN(
781 PINCTRL_PIN(77, "SDA2"),
782 "K19", "mt8127",
783 MTK_EINT_FUNCTION(0, 78),
784 MTK_FUNCTION(0, "GPIO77"),
785 MTK_FUNCTION(1, "SDA2"),
786 MTK_FUNCTION(2, "PWM1")
787 ),
788 MTK_PIN(
789 PINCTRL_PIN(78, "SCL2"),
790 "K20", "mt8127",
791 MTK_EINT_FUNCTION(0, 79),
792 MTK_FUNCTION(0, "GPIO78"),
793 MTK_FUNCTION(1, "SCL2"),
794 MTK_FUNCTION(2, "PWM2")
795 ),
796 MTK_PIN(
797 PINCTRL_PIN(79, "URXD0"),
798 "K18", "mt8127",
799 MTK_EINT_FUNCTION(0, 80),
800 MTK_FUNCTION(0, "GPIO79"),
801 MTK_FUNCTION(1, "URXD0"),
802 MTK_FUNCTION(2, "UTXD0")
803 ),
804 MTK_PIN(
805 PINCTRL_PIN(80, "UTXD0"),
806 "K17", "mt8127",
807 MTK_EINT_FUNCTION(0, 81),
808 MTK_FUNCTION(0, "GPIO80"),
809 MTK_FUNCTION(1, "UTXD0"),
810 MTK_FUNCTION(2, "URXD0")
811 ),
812 MTK_PIN(
813 PINCTRL_PIN(81, "URXD1"),
814 "L17", "mt8127",
815 MTK_EINT_FUNCTION(0, 82),
816 MTK_FUNCTION(0, "GPIO81"),
817 MTK_FUNCTION(1, "URXD1"),
818 MTK_FUNCTION(2, "UTXD1")
819 ),
820 MTK_PIN(
821 PINCTRL_PIN(82, "UTXD1"),
822 "L18", "mt8127",
823 MTK_EINT_FUNCTION(0, 83),
824 MTK_FUNCTION(0, "GPIO82"),
825 MTK_FUNCTION(1, "UTXD1"),
826 MTK_FUNCTION(2, "URXD1")
827 ),
828 MTK_PIN(
829 PINCTRL_PIN(83, "LCM_RST"),
830 "W5", "mt8127",
831 MTK_EINT_FUNCTION(0, 84),
832 MTK_FUNCTION(0, "GPIO83"),
833 MTK_FUNCTION(1, "LCM_RST"),
834 MTK_FUNCTION(2, "VDAC_CK_XI"),
835 MTK_FUNCTION(7, "DBG_MON_A[31]")
836 ),
837 MTK_PIN(
838 PINCTRL_PIN(84, "DSI_TE"),
839 "W6", "mt8127",
840 MTK_EINT_FUNCTION(0, 85),
841 MTK_FUNCTION(0, "GPIO84"),
842 MTK_FUNCTION(1, "DSI_TE"),
843 MTK_FUNCTION(7, "DBG_MON_A[32]")
844 ),
845 MTK_PIN(
846 PINCTRL_PIN(85, "MSDC2_CMD"),
847 "U7", "mt8127",
848 MTK_EINT_FUNCTION(0, 86),
849 MTK_FUNCTION(0, "GPIO85"),
850 MTK_FUNCTION(1, "MSDC2_CMD"),
851 MTK_FUNCTION(2, "ANT_SEL0"),
852 MTK_FUNCTION(3, "SDA1"),
853 MTK_FUNCTION(6, "I2SOUT_BCK"),
854 MTK_FUNCTION(7, "DBG_MON_B[22]")
855 ),
856 MTK_PIN(
857 PINCTRL_PIN(86, "MSDC2_CLK"),
858 "T8", "mt8127",
859 MTK_EINT_FUNCTION(0, 87),
860 MTK_FUNCTION(0, "GPIO86"),
861 MTK_FUNCTION(1, "MSDC2_CLK"),
862 MTK_FUNCTION(2, "ANT_SEL1"),
863 MTK_FUNCTION(3, "SCL1"),
864 MTK_FUNCTION(6, "I2SOUT_LRCK"),
865 MTK_FUNCTION(7, "DBG_MON_B[23]")
866 ),
867 MTK_PIN(
868 PINCTRL_PIN(87, "MSDC2_DAT0"),
869 "V3", "mt8127",
870 MTK_EINT_FUNCTION(0, 88),
871 MTK_FUNCTION(0, "GPIO87"),
872 MTK_FUNCTION(1, "MSDC2_DAT0"),
873 MTK_FUNCTION(2, "ANT_SEL2"),
874 MTK_FUNCTION(5, "UTXD0"),
875 MTK_FUNCTION(6, "I2SOUT_DATA_OUT"),
876 MTK_FUNCTION(7, "DBG_MON_B[24]")
877 ),
878 MTK_PIN(
879 PINCTRL_PIN(88, "MSDC2_DAT1"),
880 "V4", "mt8127",
881 MTK_EINT_FUNCTION(0, 89),
882 MTK_FUNCTION(0, "GPIO88"),
883 MTK_FUNCTION(1, "MSDC2_DAT1"),
884 MTK_FUNCTION(2, "ANT_SEL3"),
885 MTK_FUNCTION(3, "PWM0"),
886 MTK_FUNCTION(5, "URXD0"),
887 MTK_FUNCTION(6, "PWM1"),
888 MTK_FUNCTION(7, "DBG_MON_B[25]")
889 ),
890 MTK_PIN(
891 PINCTRL_PIN(89, "MSDC2_DAT2"),
892 "U5", "mt8127",
893 MTK_EINT_FUNCTION(0, 90),
894 MTK_FUNCTION(0, "GPIO89"),
895 MTK_FUNCTION(1, "MSDC2_DAT2"),
896 MTK_FUNCTION(2, "ANT_SEL4"),
897 MTK_FUNCTION(3, "SDA2"),
898 MTK_FUNCTION(5, "UTXD1"),
899 MTK_FUNCTION(6, "PWM2"),
900 MTK_FUNCTION(7, "DBG_MON_B[26]")
901 ),
902 MTK_PIN(
903 PINCTRL_PIN(90, "MSDC2_DAT3"),
904 "U6", "mt8127",
905 MTK_EINT_FUNCTION(0, 91),
906 MTK_FUNCTION(0, "GPIO90"),
907 MTK_FUNCTION(1, "MSDC2_DAT3"),
908 MTK_FUNCTION(2, "ANT_SEL5"),
909 MTK_FUNCTION(3, "SCL2"),
910 MTK_FUNCTION(4, "EXT_FRAME_SYNC"),
911 MTK_FUNCTION(5, "URXD1"),
912 MTK_FUNCTION(6, "PWM3"),
913 MTK_FUNCTION(7, "DBG_MON_B[27]")
914 ),
915 MTK_PIN(
916 PINCTRL_PIN(91, "TDN3"),
917 "U2", "mt8127",
918 MTK_EINT_FUNCTION(0, 92),
919 MTK_FUNCTION(0, "GPI91"),
920 MTK_FUNCTION(1, "TDN3")
921 ),
922 MTK_PIN(
923 PINCTRL_PIN(92, "TDP3"),
924 "U1", "mt8127",
925 MTK_EINT_FUNCTION(0, 93),
926 MTK_FUNCTION(0, "GPI92"),
927 MTK_FUNCTION(1, "TDP3")
928 ),
929 MTK_PIN(
930 PINCTRL_PIN(93, "TDN2"),
931 "T2", "mt8127",
932 MTK_EINT_FUNCTION(0, 94),
933 MTK_FUNCTION(0, "GPI93"),
934 MTK_FUNCTION(1, "TDN2")
935 ),
936 MTK_PIN(
937 PINCTRL_PIN(94, "TDP2"),
938 "T1", "mt8127",
939 MTK_EINT_FUNCTION(0, 95),
940 MTK_FUNCTION(0, "GPI94"),
941 MTK_FUNCTION(1, "TDP2")
942 ),
943 MTK_PIN(
944 PINCTRL_PIN(95, "TCN"),
945 "R5", "mt8127",
946 MTK_EINT_FUNCTION(0, 96),
947 MTK_FUNCTION(0, "GPI95"),
948 MTK_FUNCTION(1, "TCN")
949 ),
950 MTK_PIN(
951 PINCTRL_PIN(96, "TCP"),
952 "R4", "mt8127",
953 MTK_EINT_FUNCTION(0, 97),
954 MTK_FUNCTION(0, "GPI96"),
955 MTK_FUNCTION(1, "TCP")
956 ),
957 MTK_PIN(
958 PINCTRL_PIN(97, "TDN1"),
959 "R3", "mt8127",
960 MTK_EINT_FUNCTION(0, 98),
961 MTK_FUNCTION(0, "GPI97"),
962 MTK_FUNCTION(1, "TDN1")
963 ),
964 MTK_PIN(
965 PINCTRL_PIN(98, "TDP1"),
966 "R2", "mt8127",
967 MTK_EINT_FUNCTION(0, 99),
968 MTK_FUNCTION(0, "GPI98"),
969 MTK_FUNCTION(1, "TDP1")
970 ),
971 MTK_PIN(
972 PINCTRL_PIN(99, "TDN0"),
973 "P3", "mt8127",
974 MTK_EINT_FUNCTION(0, 100),
975 MTK_FUNCTION(0, "GPI99"),
976 MTK_FUNCTION(1, "TDN0")
977 ),
978 MTK_PIN(
979 PINCTRL_PIN(100, "TDP0"),
980 "P2", "mt8127",
981 MTK_EINT_FUNCTION(0, 101),
982 MTK_FUNCTION(0, "GPI100"),
983 MTK_FUNCTION(1, "TDP0")
984 ),
985 MTK_PIN(
986 PINCTRL_PIN(101, "RDN0"),
987 "K1", "mt8127",
988 MTK_EINT_FUNCTION(0, 102),
989 MTK_FUNCTION(0, "GPI101"),
990 MTK_FUNCTION(1, "RDN0")
991 ),
992 MTK_PIN(
993 PINCTRL_PIN(102, "RDP0"),
994 "K2", "mt8127",
995 MTK_EINT_FUNCTION(0, 103),
996 MTK_FUNCTION(0, "GPI102"),
997 MTK_FUNCTION(1, "RDP0")
998 ),
999 MTK_PIN(
1000 PINCTRL_PIN(103, "RDN1"),
1001 "L2", "mt8127",
1002 MTK_EINT_FUNCTION(0, 104),
1003 MTK_FUNCTION(0, "GPI103"),
1004 MTK_FUNCTION(1, "RDN1")
1005 ),
1006 MTK_PIN(
1007 PINCTRL_PIN(104, "RDP1"),
1008 "L3", "mt8127",
1009 MTK_EINT_FUNCTION(0, 105),
1010 MTK_FUNCTION(0, "GPI104"),
1011 MTK_FUNCTION(1, "RDP1")
1012 ),
1013 MTK_PIN(
1014 PINCTRL_PIN(105, "RCN"),
1015 "M4", "mt8127",
1016 MTK_EINT_FUNCTION(0, 106),
1017 MTK_FUNCTION(0, "GPI105"),
1018 MTK_FUNCTION(1, "RCN")
1019 ),
1020 MTK_PIN(
1021 PINCTRL_PIN(106, "RCP"),
1022 "M5", "mt8127",
1023 MTK_EINT_FUNCTION(0, 107),
1024 MTK_FUNCTION(0, "GPI106"),
1025 MTK_FUNCTION(1, "RCP")
1026 ),
1027 MTK_PIN(
1028 PINCTRL_PIN(107, "RDN2"),
1029 "M2", "mt8127",
1030 MTK_EINT_FUNCTION(0, 108),
1031 MTK_FUNCTION(0, "GPI107"),
1032 MTK_FUNCTION(1, "RDN2"),
1033 MTK_FUNCTION(2, "CMDAT8")
1034 ),
1035 MTK_PIN(
1036 PINCTRL_PIN(108, "RDP2"),
1037 "M3", "mt8127",
1038 MTK_EINT_FUNCTION(0, 109),
1039 MTK_FUNCTION(0, "GPI108"),
1040 MTK_FUNCTION(1, "RDP2"),
1041 MTK_FUNCTION(2, "CMDAT9")
1042 ),
1043 MTK_PIN(
1044 PINCTRL_PIN(109, "RDN3"),
1045 "N2", "mt8127",
1046 MTK_EINT_FUNCTION(0, 110),
1047 MTK_FUNCTION(0, "GPI109"),
1048 MTK_FUNCTION(1, "RDN3"),
1049 MTK_FUNCTION(2, "CMDAT4")
1050 ),
1051 MTK_PIN(
1052 PINCTRL_PIN(110, "RDP3"),
1053 "N3", "mt8127",
1054 MTK_EINT_FUNCTION(0, 111),
1055 MTK_FUNCTION(0, "GPI110"),
1056 MTK_FUNCTION(1, "RDP3"),
1057 MTK_FUNCTION(2, "CMDAT5")
1058 ),
1059 MTK_PIN(
1060 PINCTRL_PIN(111, "RCN_A"),
1061 "J5", "mt8127",
1062 MTK_EINT_FUNCTION(0, 112),
1063 MTK_FUNCTION(0, "GPI111"),
1064 MTK_FUNCTION(1, "RCN_A"),
1065 MTK_FUNCTION(2, "CMDAT6")
1066 ),
1067 MTK_PIN(
1068 PINCTRL_PIN(112, "RCP_A"),
1069 "J4", "mt8127",
1070 MTK_EINT_FUNCTION(0, 113),
1071 MTK_FUNCTION(0, "GPI112"),
1072 MTK_FUNCTION(1, "RCP_A"),
1073 MTK_FUNCTION(2, "CMDAT7")
1074 ),
1075 MTK_PIN(
1076 PINCTRL_PIN(113, "RDN1_A"),
1077 "J2", "mt8127",
1078 MTK_EINT_FUNCTION(0, 114),
1079 MTK_FUNCTION(0, "GPI113"),
1080 MTK_FUNCTION(1, "RDN1_A"),
1081 MTK_FUNCTION(2, "CMDAT2"),
1082 MTK_FUNCTION(3, "CMCSD2")
1083 ),
1084 MTK_PIN(
1085 PINCTRL_PIN(114, "RDP1_A"),
1086 "J3", "mt8127",
1087 MTK_EINT_FUNCTION(0, 115),
1088 MTK_FUNCTION(0, "GPI114"),
1089 MTK_FUNCTION(1, "RDP1_A"),
1090 MTK_FUNCTION(2, "CMDAT3"),
1091 MTK_FUNCTION(3, "CMCSD3")
1092 ),
1093 MTK_PIN(
1094 PINCTRL_PIN(115, "RDN0_A"),
1095 "H2", "mt8127",
1096 MTK_EINT_FUNCTION(0, 116),
1097 MTK_FUNCTION(0, "GPI115"),
1098 MTK_FUNCTION(1, "RDN0_A"),
1099 MTK_FUNCTION(2, "CMHSYNC")
1100 ),
1101 MTK_PIN(
1102 PINCTRL_PIN(116, "RDP0_A"),
1103 "H3", "mt8127",
1104 MTK_EINT_FUNCTION(0, 117),
1105 MTK_FUNCTION(0, "GPI116"),
1106 MTK_FUNCTION(1, "RDP0_A"),
1107 MTK_FUNCTION(2, "CMVSYNC")
1108 ),
1109 MTK_PIN(
1110 PINCTRL_PIN(117, "CMDAT0"),
1111 "G5", "mt8127",
1112 MTK_EINT_FUNCTION(0, 118),
1113 MTK_FUNCTION(0, "GPIO117"),
1114 MTK_FUNCTION(1, "CMDAT0"),
1115 MTK_FUNCTION(2, "CMCSD0"),
1116 MTK_FUNCTION(3, "ANT_SEL2"),
1117 MTK_FUNCTION(7, "DBG_MON_B[28]")
1118 ),
1119 MTK_PIN(
1120 PINCTRL_PIN(118, "CMDAT1"),
1121 "G4", "mt8127",
1122 MTK_EINT_FUNCTION(0, 119),
1123 MTK_FUNCTION(0, "GPIO118"),
1124 MTK_FUNCTION(1, "CMDAT1"),
1125 MTK_FUNCTION(2, "CMCSD1"),
1126 MTK_FUNCTION(3, "ANT_SEL3"),
1127 MTK_FUNCTION(7, "DBG_MON_B[29]")
1128 ),
1129 MTK_PIN(
1130 PINCTRL_PIN(119, "CMMCLK"),
1131 "F3", "mt8127",
1132 MTK_EINT_FUNCTION(0, 120),
1133 MTK_FUNCTION(0, "GPIO119"),
1134 MTK_FUNCTION(1, "CMMCLK"),
1135 MTK_FUNCTION(3, "ANT_SEL4"),
1136 MTK_FUNCTION(7, "DBG_MON_B[30]")
1137 ),
1138 MTK_PIN(
1139 PINCTRL_PIN(120, "CMPCLK"),
1140 "G6", "mt8127",
1141 MTK_EINT_FUNCTION(0, 121),
1142 MTK_FUNCTION(0, "GPIO120"),
1143 MTK_FUNCTION(1, "CMPCLK"),
1144 MTK_FUNCTION(2, "CMCSK"),
1145 MTK_FUNCTION(3, "ANT_SEL5"),
1146 MTK_FUNCTION(7, "DBG_MON_B[31]")
1147 ),
1148 MTK_PIN(
1149 PINCTRL_PIN(121, "MSDC1_CMD"),
1150 "E3", "mt8127",
1151 MTK_EINT_FUNCTION(0, 122),
1152 MTK_FUNCTION(0, "GPIO121"),
1153 MTK_FUNCTION(1, "MSDC1_CMD")
1154 ),
1155 MTK_PIN(
1156 PINCTRL_PIN(122, "MSDC1_CLK"),
1157 "D1", "mt8127",
1158 MTK_EINT_FUNCTION(0, 123),
1159 MTK_FUNCTION(0, "GPIO122"),
1160 MTK_FUNCTION(1, "MSDC1_CLK")
1161 ),
1162 MTK_PIN(
1163 PINCTRL_PIN(123, "MSDC1_DAT0"),
1164 "D2", "mt8127",
1165 MTK_EINT_FUNCTION(0, 124),
1166 MTK_FUNCTION(0, "GPIO123"),
1167 MTK_FUNCTION(1, "MSDC1_DAT0")
1168 ),
1169 MTK_PIN(
1170 PINCTRL_PIN(124, "MSDC1_DAT1"),
1171 "D3", "mt8127",
1172 MTK_EINT_FUNCTION(0, 125),
1173 MTK_FUNCTION(0, "GPIO124"),
1174 MTK_FUNCTION(1, "MSDC1_DAT1")
1175 ),
1176 MTK_PIN(
1177 PINCTRL_PIN(125, "MSDC1_DAT2"),
1178 "F2", "mt8127",
1179 MTK_EINT_FUNCTION(0, 126),
1180 MTK_FUNCTION(0, "GPIO125"),
1181 MTK_FUNCTION(1, "MSDC1_DAT2")
1182 ),
1183 MTK_PIN(
1184 PINCTRL_PIN(126, "MSDC1_DAT3"),
1185 "E2", "mt8127",
1186 MTK_EINT_FUNCTION(0, 127),
1187 MTK_FUNCTION(0, "GPIO126"),
1188 MTK_FUNCTION(1, "MSDC1_DAT3")
1189 ),
1190 MTK_PIN(
1191 PINCTRL_PIN(127, "MSDC0_DAT7"),
1192 "C23", "mt8127",
1193 MTK_EINT_FUNCTION(0, 128),
1194 MTK_FUNCTION(0, "GPIO127"),
1195 MTK_FUNCTION(1, "MSDC0_DAT7"),
1196 MTK_FUNCTION(4, "NLD7")
1197 ),
1198 MTK_PIN(
1199 PINCTRL_PIN(128, "MSDC0_DAT6"),
1200 "C24", "mt8127",
1201 MTK_EINT_FUNCTION(0, 129),
1202 MTK_FUNCTION(0, "GPIO128"),
1203 MTK_FUNCTION(1, "MSDC0_DAT6"),
1204 MTK_FUNCTION(4, "NLD6")
1205 ),
1206 MTK_PIN(
1207 PINCTRL_PIN(129, "MSDC0_DAT5"),
1208 "D22", "mt8127",
1209 MTK_EINT_FUNCTION(0, 130),
1210 MTK_FUNCTION(0, "GPIO129"),
1211 MTK_FUNCTION(1, "MSDC0_DAT5"),
1212 MTK_FUNCTION(4, "NLD4")
1213 ),
1214 MTK_PIN(
1215 PINCTRL_PIN(130, "MSDC0_DAT4"),
1216 "D24", "mt8127",
1217 MTK_EINT_FUNCTION(0, 131),
1218 MTK_FUNCTION(0, "GPIO130"),
1219 MTK_FUNCTION(1, "MSDC0_DAT4"),
1220 MTK_FUNCTION(4, "NLD3")
1221 ),
1222 MTK_PIN(
1223 PINCTRL_PIN(131, "MSDC0_RSTB"),
1224 "F24", "mt8127",
1225 MTK_EINT_FUNCTION(0, 132),
1226 MTK_FUNCTION(0, "GPIO131"),
1227 MTK_FUNCTION(1, "MSDC0_RSTB"),
1228 MTK_FUNCTION(4, "NLD0")
1229 ),
1230 MTK_PIN(
1231 PINCTRL_PIN(132, "MSDC0_CMD"),
1232 "G20", "mt8127",
1233 MTK_EINT_FUNCTION(0, 133),
1234 MTK_FUNCTION(0, "GPIO132"),
1235 MTK_FUNCTION(1, "MSDC0_CMD"),
1236 MTK_FUNCTION(4, "NALE")
1237 ),
1238 MTK_PIN(
1239 PINCTRL_PIN(133, "MSDC0_CLK"),
1240 "G21", "mt8127",
1241 MTK_EINT_FUNCTION(0, 134),
1242 MTK_FUNCTION(0, "GPIO133"),
1243 MTK_FUNCTION(1, "MSDC0_CLK"),
1244 MTK_FUNCTION(4, "NWEB")
1245 ),
1246 MTK_PIN(
1247 PINCTRL_PIN(134, "MSDC0_DAT3"),
1248 "D23", "mt8127",
1249 MTK_EINT_FUNCTION(0, 135),
1250 MTK_FUNCTION(0, "GPIO134"),
1251 MTK_FUNCTION(1, "MSDC0_DAT3"),
1252 MTK_FUNCTION(4, "NLD1")
1253 ),
1254 MTK_PIN(
1255 PINCTRL_PIN(135, "MSDC0_DAT2"),
1256 "E22", "mt8127",
1257 MTK_EINT_FUNCTION(0, 136),
1258 MTK_FUNCTION(0, "GPIO135"),
1259 MTK_FUNCTION(1, "MSDC0_DAT2"),
1260 MTK_FUNCTION(4, "NLD5")
1261 ),
1262 MTK_PIN(
1263 PINCTRL_PIN(136, "MSDC0_DAT1"),
1264 "E23", "mt8127",
1265 MTK_EINT_FUNCTION(0, 137),
1266 MTK_FUNCTION(0, "GPIO136"),
1267 MTK_FUNCTION(1, "MSDC0_DAT1"),
1268 MTK_FUNCTION(4, "NLD8")
1269 ),
1270 MTK_PIN(
1271 PINCTRL_PIN(137, "MSDC0_DAT0"),
1272 "F22", "mt8127",
1273 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1274 MTK_FUNCTION(0, "GPIO137"),
1275 MTK_FUNCTION(1, "MSDC0_DAT0"),
1276 MTK_FUNCTION(4, "WATCHDOG"),
1277 MTK_FUNCTION(5, "NLD2")
1278 ),
1279 MTK_PIN(
1280 PINCTRL_PIN(138, "CEC"),
1281 "AE21", "mt8127",
1282 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1283 MTK_FUNCTION(0, "GPIO138"),
1284 MTK_FUNCTION(1, "CEC")
1285 ),
1286 MTK_PIN(
1287 PINCTRL_PIN(139, "HTPLG"),
1288 "AD21", "mt8127",
1289 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1290 MTK_FUNCTION(0, "GPIO139"),
1291 MTK_FUNCTION(1, "HTPLG")
1292 ),
1293 MTK_PIN(
1294 PINCTRL_PIN(140, "HDMISCK"),
1295 "AE22", "mt8127",
1296 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1297 MTK_FUNCTION(0, "GPIO140"),
1298 MTK_FUNCTION(1, "HDMISCK")
1299 ),
1300 MTK_PIN(
1301 PINCTRL_PIN(141, "HDMISD"),
1302 "AD22", "mt8127",
1303 MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
1304 MTK_FUNCTION(0, "GPIO141"),
1305 MTK_FUNCTION(1, "HDMISD")
1306 ),
1307 MTK_PIN(
1308 PINCTRL_PIN(142, "EINT21"),
1309 "J23", "mt8127",
1310 MTK_EINT_FUNCTION(0, 21),
1311 MTK_FUNCTION(0, "GPIO142"),
1312 MTK_FUNCTION(1, "NRNB"),
1313 MTK_FUNCTION(2, "ANT_SEL0"),
1314 MTK_FUNCTION(7, "DBG_MON_B[32]")
1315 ),
1316};
1317
1318#endif /* __PINCTRL_MTK_MT8127_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 22:34:40 -0400