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authorVivien Didelot <vivien.didelot@savoirfairelinux.com>2016-06-21 12:28:20 -0400
committerDavid S. Miller <davem@davemloft.net>2016-06-25 11:29:47 -0400
commitfad09c73c27020001cd472343efdacf60a93f8ea (patch)
treedcb99d5ce2bf93b1bd7959ce1a7a69f4ad45c57b /drivers/net/dsa
parent0d3cd4b6b49865e83ae648b66cf815d466085914 (diff)
net: dsa: mv88e6xxx: rename single-chip support
With the upcoming support for cross-chip operations, it will be hard to distinguish portions of code supporting a single-chip or a switch fabric of interconnected chips. Make the code clearer now, by renaming the mv88e6xxx_priv_state chip structure to mv88e6xxx_chip. This patch brings no functional changes. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/dsa')
-rw-r--r--drivers/net/dsa/mv88e6xxx/Makefile2
-rw-r--r--drivers/net/dsa/mv88e6xxx/chip.c (renamed from drivers/net/dsa/mv88e6xxx/mv88e6xxx.c)1437
-rw-r--r--drivers/net/dsa/mv88e6xxx/mv88e6xxx.h12
3 files changed, 731 insertions, 720 deletions
diff --git a/drivers/net/dsa/mv88e6xxx/Makefile b/drivers/net/dsa/mv88e6xxx/Makefile
index 1128fc719672..6e29a75ee2f7 100644
--- a/drivers/net/dsa/mv88e6xxx/Makefile
+++ b/drivers/net/dsa/mv88e6xxx/Makefile
@@ -1 +1 @@
obj-$(CONFIG_NET_DSA_MV88E6XXX) += mv88e6xxx.o obj-$(CONFIG_NET_DSA_MV88E6XXX) += chip.o
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 2073f7b991a6..5cb06f7673af 100644
--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -31,10 +31,10 @@
31#include <net/switchdev.h> 31#include <net/switchdev.h>
32#include "mv88e6xxx.h" 32#include "mv88e6xxx.h"
33 33
34static void assert_reg_lock(struct mv88e6xxx_priv_state *ps) 34static void assert_reg_lock(struct mv88e6xxx_chip *chip)
35{ 35{
36 if (unlikely(!mutex_is_locked(&ps->reg_lock))) { 36 if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
37 dev_err(ps->dev, "Switch registers lock not held!\n"); 37 dev_err(chip->dev, "Switch registers lock not held!\n");
38 dump_stack(); 38 dump_stack();
39 } 39 }
40} 40}
@@ -51,30 +51,30 @@ static void assert_reg_lock(struct mv88e6xxx_priv_state *ps)
51 * 2 registers, used to indirectly access the internal SMI devices. 51 * 2 registers, used to indirectly access the internal SMI devices.
52 */ 52 */
53 53
54static int mv88e6xxx_smi_read(struct mv88e6xxx_priv_state *ps, 54static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
55 int addr, int reg, u16 *val) 55 int addr, int reg, u16 *val)
56{ 56{
57 if (!ps->smi_ops) 57 if (!chip->smi_ops)
58 return -EOPNOTSUPP; 58 return -EOPNOTSUPP;
59 59
60 return ps->smi_ops->read(ps, addr, reg, val); 60 return chip->smi_ops->read(chip, addr, reg, val);
61} 61}
62 62
63static int mv88e6xxx_smi_write(struct mv88e6xxx_priv_state *ps, 63static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
64 int addr, int reg, u16 val) 64 int addr, int reg, u16 val)
65{ 65{
66 if (!ps->smi_ops) 66 if (!chip->smi_ops)
67 return -EOPNOTSUPP; 67 return -EOPNOTSUPP;
68 68
69 return ps->smi_ops->write(ps, addr, reg, val); 69 return chip->smi_ops->write(chip, addr, reg, val);
70} 70}
71 71
72static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_priv_state *ps, 72static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
73 int addr, int reg, u16 *val) 73 int addr, int reg, u16 *val)
74{ 74{
75 int ret; 75 int ret;
76 76
77 ret = mdiobus_read_nested(ps->bus, addr, reg); 77 ret = mdiobus_read_nested(chip->bus, addr, reg);
78 if (ret < 0) 78 if (ret < 0)
79 return ret; 79 return ret;
80 80
@@ -83,12 +83,12 @@ static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_priv_state *ps,
83 return 0; 83 return 0;
84} 84}
85 85
86static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_priv_state *ps, 86static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
87 int addr, int reg, u16 val) 87 int addr, int reg, u16 val)
88{ 88{
89 int ret; 89 int ret;
90 90
91 ret = mdiobus_write_nested(ps->bus, addr, reg, val); 91 ret = mdiobus_write_nested(chip->bus, addr, reg, val);
92 if (ret < 0) 92 if (ret < 0)
93 return ret; 93 return ret;
94 94
@@ -100,13 +100,13 @@ static const struct mv88e6xxx_ops mv88e6xxx_smi_single_chip_ops = {
100 .write = mv88e6xxx_smi_single_chip_write, 100 .write = mv88e6xxx_smi_single_chip_write,
101}; 101};
102 102
103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_priv_state *ps) 103static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
104{ 104{
105 int ret; 105 int ret;
106 int i; 106 int i;
107 107
108 for (i = 0; i < 16; i++) { 108 for (i = 0; i < 16; i++) {
109 ret = mdiobus_read_nested(ps->bus, ps->sw_addr, SMI_CMD); 109 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
110 if (ret < 0) 110 if (ret < 0)
111 return ret; 111 return ret;
112 112
@@ -117,29 +117,29 @@ static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_priv_state *ps)
117 return -ETIMEDOUT; 117 return -ETIMEDOUT;
118} 118}
119 119
120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_priv_state *ps, 120static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
121 int addr, int reg, u16 *val) 121 int addr, int reg, u16 *val)
122{ 122{
123 int ret; 123 int ret;
124 124
125 /* Wait for the bus to become free. */ 125 /* Wait for the bus to become free. */
126 ret = mv88e6xxx_smi_multi_chip_wait(ps); 126 ret = mv88e6xxx_smi_multi_chip_wait(chip);
127 if (ret < 0) 127 if (ret < 0)
128 return ret; 128 return ret;
129 129
130 /* Transmit the read command. */ 130 /* Transmit the read command. */
131 ret = mdiobus_write_nested(ps->bus, ps->sw_addr, SMI_CMD, 131 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
132 SMI_CMD_OP_22_READ | (addr << 5) | reg); 132 SMI_CMD_OP_22_READ | (addr << 5) | reg);
133 if (ret < 0) 133 if (ret < 0)
134 return ret; 134 return ret;
135 135
136 /* Wait for the read command to complete. */ 136 /* Wait for the read command to complete. */
137 ret = mv88e6xxx_smi_multi_chip_wait(ps); 137 ret = mv88e6xxx_smi_multi_chip_wait(chip);
138 if (ret < 0) 138 if (ret < 0)
139 return ret; 139 return ret;
140 140
141 /* Read the data. */ 141 /* Read the data. */
142 ret = mdiobus_read_nested(ps->bus, ps->sw_addr, SMI_DATA); 142 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
143 if (ret < 0) 143 if (ret < 0)
144 return ret; 144 return ret;
145 145
@@ -148,29 +148,29 @@ static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_priv_state *ps,
148 return 0; 148 return 0;
149} 149}
150 150
151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_priv_state *ps, 151static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
152 int addr, int reg, u16 val) 152 int addr, int reg, u16 val)
153{ 153{
154 int ret; 154 int ret;
155 155
156 /* Wait for the bus to become free. */ 156 /* Wait for the bus to become free. */
157 ret = mv88e6xxx_smi_multi_chip_wait(ps); 157 ret = mv88e6xxx_smi_multi_chip_wait(chip);
158 if (ret < 0) 158 if (ret < 0)
159 return ret; 159 return ret;
160 160
161 /* Transmit the data to write. */ 161 /* Transmit the data to write. */
162 ret = mdiobus_write_nested(ps->bus, ps->sw_addr, SMI_DATA, val); 162 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
163 if (ret < 0) 163 if (ret < 0)
164 return ret; 164 return ret;
165 165
166 /* Transmit the write command. */ 166 /* Transmit the write command. */
167 ret = mdiobus_write_nested(ps->bus, ps->sw_addr, SMI_CMD, 167 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 168 SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
169 if (ret < 0) 169 if (ret < 0)
170 return ret; 170 return ret;
171 171
172 /* Wait for the write command to complete. */ 172 /* Wait for the write command to complete. */
173 ret = mv88e6xxx_smi_multi_chip_wait(ps); 173 ret = mv88e6xxx_smi_multi_chip_wait(chip);
174 if (ret < 0) 174 if (ret < 0)
175 return ret; 175 return ret;
176 176
@@ -182,105 +182,103 @@ static const struct mv88e6xxx_ops mv88e6xxx_smi_multi_chip_ops = {
182 .write = mv88e6xxx_smi_multi_chip_write, 182 .write = mv88e6xxx_smi_multi_chip_write,
183}; 183};
184 184
185static int mv88e6xxx_read(struct mv88e6xxx_priv_state *ps, 185static int mv88e6xxx_read(struct mv88e6xxx_chip *chip,
186 int addr, int reg, u16 *val) 186 int addr, int reg, u16 *val)
187{ 187{
188 int err; 188 int err;
189 189
190 assert_reg_lock(ps); 190 assert_reg_lock(chip);
191 191
192 err = mv88e6xxx_smi_read(ps, addr, reg, val); 192 err = mv88e6xxx_smi_read(chip, addr, reg, val);
193 if (err) 193 if (err)
194 return err; 194 return err;
195 195
196 dev_dbg(ps->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 196 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
197 addr, reg, *val); 197 addr, reg, *val);
198 198
199 return 0; 199 return 0;
200} 200}
201 201
202static int mv88e6xxx_write(struct mv88e6xxx_priv_state *ps, 202static int mv88e6xxx_write(struct mv88e6xxx_chip *chip,
203 int addr, int reg, u16 val) 203 int addr, int reg, u16 val)
204{ 204{
205 int err; 205 int err;
206 206
207 assert_reg_lock(ps); 207 assert_reg_lock(chip);
208 208
209 err = mv88e6xxx_smi_write(ps, addr, reg, val); 209 err = mv88e6xxx_smi_write(chip, addr, reg, val);
210 if (err) 210 if (err)
211 return err; 211 return err;
212 212
213 dev_dbg(ps->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 213 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
214 addr, reg, val); 214 addr, reg, val);
215 215
216 return 0; 216 return 0;
217} 217}
218 218
219static int _mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, 219static int _mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
220 int addr, int reg)
221{ 220{
222 u16 val; 221 u16 val;
223 int err; 222 int err;
224 223
225 err = mv88e6xxx_read(ps, addr, reg, &val); 224 err = mv88e6xxx_read(chip, addr, reg, &val);
226 if (err) 225 if (err)
227 return err; 226 return err;
228 227
229 return val; 228 return val;
230} 229}
231 230
232static int mv88e6xxx_reg_read(struct mv88e6xxx_priv_state *ps, int addr, 231static int mv88e6xxx_reg_read(struct mv88e6xxx_chip *chip, int addr, int reg)
233 int reg)
234{ 232{
235 int ret; 233 int ret;
236 234
237 mutex_lock(&ps->reg_lock); 235 mutex_lock(&chip->reg_lock);
238 ret = _mv88e6xxx_reg_read(ps, addr, reg); 236 ret = _mv88e6xxx_reg_read(chip, addr, reg);
239 mutex_unlock(&ps->reg_lock); 237 mutex_unlock(&chip->reg_lock);
240 238
241 return ret; 239 return ret;
242} 240}
243 241
244static int _mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr, 242static int _mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
245 int reg, u16 val) 243 int reg, u16 val)
246{ 244{
247 return mv88e6xxx_write(ps, addr, reg, val); 245 return mv88e6xxx_write(chip, addr, reg, val);
248} 246}
249 247
250static int mv88e6xxx_reg_write(struct mv88e6xxx_priv_state *ps, int addr, 248static int mv88e6xxx_reg_write(struct mv88e6xxx_chip *chip, int addr,
251 int reg, u16 val) 249 int reg, u16 val)
252{ 250{
253 int ret; 251 int ret;
254 252
255 mutex_lock(&ps->reg_lock); 253 mutex_lock(&chip->reg_lock);
256 ret = _mv88e6xxx_reg_write(ps, addr, reg, val); 254 ret = _mv88e6xxx_reg_write(chip, addr, reg, val);
257 mutex_unlock(&ps->reg_lock); 255 mutex_unlock(&chip->reg_lock);
258 256
259 return ret; 257 return ret;
260} 258}
261 259
262static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr) 260static int mv88e6xxx_set_addr_direct(struct dsa_switch *ds, u8 *addr)
263{ 261{
264 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 262 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
265 int err; 263 int err;
266 264
267 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_01, 265 err = mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_01,
268 (addr[0] << 8) | addr[1]); 266 (addr[0] << 8) | addr[1]);
269 if (err) 267 if (err)
270 return err; 268 return err;
271 269
272 err = mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_23, 270 err = mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_23,
273 (addr[2] << 8) | addr[3]); 271 (addr[2] << 8) | addr[3]);
274 if (err) 272 if (err)
275 return err; 273 return err;
276 274
277 return mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MAC_45, 275 return mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MAC_45,
278 (addr[4] << 8) | addr[5]); 276 (addr[4] << 8) | addr[5]);
279} 277}
280 278
281static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr) 279static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
282{ 280{
283 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 281 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
284 int ret; 282 int ret;
285 int i; 283 int i;
286 284
@@ -288,7 +286,7 @@ static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
288 int j; 286 int j;
289 287
290 /* Write the MAC address byte. */ 288 /* Write the MAC address byte. */
291 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MAC, 289 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MAC,
292 GLOBAL2_SWITCH_MAC_BUSY | 290 GLOBAL2_SWITCH_MAC_BUSY |
293 (i << 8) | addr[i]); 291 (i << 8) | addr[i]);
294 if (ret) 292 if (ret)
@@ -296,7 +294,7 @@ static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
296 294
297 /* Wait for the write to complete. */ 295 /* Wait for the write to complete. */
298 for (j = 0; j < 16; j++) { 296 for (j = 0; j < 16; j++) {
299 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, 297 ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2,
300 GLOBAL2_SWITCH_MAC); 298 GLOBAL2_SWITCH_MAC);
301 if (ret < 0) 299 if (ret < 0)
302 return ret; 300 return ret;
@@ -313,47 +311,47 @@ static int mv88e6xxx_set_addr_indirect(struct dsa_switch *ds, u8 *addr)
313 311
314static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 312static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr)
315{ 313{
316 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 314 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
317 315
318 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SWITCH_MAC)) 316 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SWITCH_MAC))
319 return mv88e6xxx_set_addr_indirect(ds, addr); 317 return mv88e6xxx_set_addr_indirect(ds, addr);
320 else 318 else
321 return mv88e6xxx_set_addr_direct(ds, addr); 319 return mv88e6xxx_set_addr_direct(ds, addr);
322} 320}
323 321
324static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_priv_state *ps, 322static int mv88e6xxx_mdio_read_direct(struct mv88e6xxx_chip *chip,
325 int addr, int regnum) 323 int addr, int regnum)
326{ 324{
327 if (addr >= 0) 325 if (addr >= 0)
328 return _mv88e6xxx_reg_read(ps, addr, regnum); 326 return _mv88e6xxx_reg_read(chip, addr, regnum);
329 return 0xffff; 327 return 0xffff;
330} 328}
331 329
332static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_priv_state *ps, 330static int mv88e6xxx_mdio_write_direct(struct mv88e6xxx_chip *chip,
333 int addr, int regnum, u16 val) 331 int addr, int regnum, u16 val)
334{ 332{
335 if (addr >= 0) 333 if (addr >= 0)
336 return _mv88e6xxx_reg_write(ps, addr, regnum, val); 334 return _mv88e6xxx_reg_write(chip, addr, regnum, val);
337 return 0; 335 return 0;
338} 336}
339 337
340static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps) 338static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip)
341{ 339{
342 int ret; 340 int ret;
343 unsigned long timeout; 341 unsigned long timeout;
344 342
345 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL); 343 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
346 if (ret < 0) 344 if (ret < 0)
347 return ret; 345 return ret;
348 346
349 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, 347 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
350 ret & ~GLOBAL_CONTROL_PPU_ENABLE); 348 ret & ~GLOBAL_CONTROL_PPU_ENABLE);
351 if (ret) 349 if (ret)
352 return ret; 350 return ret;
353 351
354 timeout = jiffies + 1 * HZ; 352 timeout = jiffies + 1 * HZ;
355 while (time_before(jiffies, timeout)) { 353 while (time_before(jiffies, timeout)) {
356 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS); 354 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
357 if (ret < 0) 355 if (ret < 0)
358 return ret; 356 return ret;
359 357
@@ -366,23 +364,23 @@ static int mv88e6xxx_ppu_disable(struct mv88e6xxx_priv_state *ps)
366 return -ETIMEDOUT; 364 return -ETIMEDOUT;
367} 365}
368 366
369static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps) 367static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip)
370{ 368{
371 int ret, err; 369 int ret, err;
372 unsigned long timeout; 370 unsigned long timeout;
373 371
374 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_CONTROL); 372 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_CONTROL);
375 if (ret < 0) 373 if (ret < 0)
376 return ret; 374 return ret;
377 375
378 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, 376 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL,
379 ret | GLOBAL_CONTROL_PPU_ENABLE); 377 ret | GLOBAL_CONTROL_PPU_ENABLE);
380 if (err) 378 if (err)
381 return err; 379 return err;
382 380
383 timeout = jiffies + 1 * HZ; 381 timeout = jiffies + 1 * HZ;
384 while (time_before(jiffies, timeout)) { 382 while (time_before(jiffies, timeout)) {
385 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATUS); 383 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATUS);
386 if (ret < 0) 384 if (ret < 0)
387 return ret; 385 return ret;
388 386
@@ -397,148 +395,148 @@ static int mv88e6xxx_ppu_enable(struct mv88e6xxx_priv_state *ps)
397 395
398static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) 396static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly)
399{ 397{
400 struct mv88e6xxx_priv_state *ps; 398 struct mv88e6xxx_chip *chip;
401 399
402 ps = container_of(ugly, struct mv88e6xxx_priv_state, ppu_work); 400 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work);
403 401
404 mutex_lock(&ps->reg_lock); 402 mutex_lock(&chip->reg_lock);
405 403
406 if (mutex_trylock(&ps->ppu_mutex)) { 404 if (mutex_trylock(&chip->ppu_mutex)) {
407 if (mv88e6xxx_ppu_enable(ps) == 0) 405 if (mv88e6xxx_ppu_enable(chip) == 0)
408 ps->ppu_disabled = 0; 406 chip->ppu_disabled = 0;
409 mutex_unlock(&ps->ppu_mutex); 407 mutex_unlock(&chip->ppu_mutex);
410 } 408 }
411 409
412 mutex_unlock(&ps->reg_lock); 410 mutex_unlock(&chip->reg_lock);
413} 411}
414 412
415static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) 413static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps)
416{ 414{
417 struct mv88e6xxx_priv_state *ps = (void *)_ps; 415 struct mv88e6xxx_chip *chip = (void *)_ps;
418 416
419 schedule_work(&ps->ppu_work); 417 schedule_work(&chip->ppu_work);
420} 418}
421 419
422static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_priv_state *ps) 420static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip)
423{ 421{
424 int ret; 422 int ret;
425 423
426 mutex_lock(&ps->ppu_mutex); 424 mutex_lock(&chip->ppu_mutex);
427 425
428 /* If the PHY polling unit is enabled, disable it so that 426 /* If the PHY polling unit is enabled, disable it so that
429 * we can access the PHY registers. If it was already 427 * we can access the PHY registers. If it was already
430 * disabled, cancel the timer that is going to re-enable 428 * disabled, cancel the timer that is going to re-enable
431 * it. 429 * it.
432 */ 430 */
433 if (!ps->ppu_disabled) { 431 if (!chip->ppu_disabled) {
434 ret = mv88e6xxx_ppu_disable(ps); 432 ret = mv88e6xxx_ppu_disable(chip);
435 if (ret < 0) { 433 if (ret < 0) {
436 mutex_unlock(&ps->ppu_mutex); 434 mutex_unlock(&chip->ppu_mutex);
437 return ret; 435 return ret;
438 } 436 }
439 ps->ppu_disabled = 1; 437 chip->ppu_disabled = 1;
440 } else { 438 } else {
441 del_timer(&ps->ppu_timer); 439 del_timer(&chip->ppu_timer);
442 ret = 0; 440 ret = 0;
443 } 441 }
444 442
445 return ret; 443 return ret;
446} 444}
447 445
448static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_priv_state *ps) 446static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip)
449{ 447{
450 /* Schedule a timer to re-enable the PHY polling unit. */ 448 /* Schedule a timer to re-enable the PHY polling unit. */
451 mod_timer(&ps->ppu_timer, jiffies + msecs_to_jiffies(10)); 449 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10));
452 mutex_unlock(&ps->ppu_mutex); 450 mutex_unlock(&chip->ppu_mutex);
453} 451}
454 452
455static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_priv_state *ps) 453static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip)
456{ 454{
457 mutex_init(&ps->ppu_mutex); 455 mutex_init(&chip->ppu_mutex);
458 INIT_WORK(&ps->ppu_work, mv88e6xxx_ppu_reenable_work); 456 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work);
459 init_timer(&ps->ppu_timer); 457 init_timer(&chip->ppu_timer);
460 ps->ppu_timer.data = (unsigned long)ps; 458 chip->ppu_timer.data = (unsigned long)chip;
461 ps->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; 459 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer;
462} 460}
463 461
464static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_priv_state *ps, int addr, 462static int mv88e6xxx_mdio_read_ppu(struct mv88e6xxx_chip *chip, int addr,
465 int regnum) 463 int regnum)
466{ 464{
467 int ret; 465 int ret;
468 466
469 ret = mv88e6xxx_ppu_access_get(ps); 467 ret = mv88e6xxx_ppu_access_get(chip);
470 if (ret >= 0) { 468 if (ret >= 0) {
471 ret = _mv88e6xxx_reg_read(ps, addr, regnum); 469 ret = _mv88e6xxx_reg_read(chip, addr, regnum);
472 mv88e6xxx_ppu_access_put(ps); 470 mv88e6xxx_ppu_access_put(chip);
473 } 471 }
474 472
475 return ret; 473 return ret;
476} 474}
477 475
478static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_priv_state *ps, int addr, 476static int mv88e6xxx_mdio_write_ppu(struct mv88e6xxx_chip *chip, int addr,
479 int regnum, u16 val) 477 int regnum, u16 val)
480{ 478{
481 int ret; 479 int ret;
482 480
483 ret = mv88e6xxx_ppu_access_get(ps); 481 ret = mv88e6xxx_ppu_access_get(chip);
484 if (ret >= 0) { 482 if (ret >= 0) {
485 ret = _mv88e6xxx_reg_write(ps, addr, regnum, val); 483 ret = _mv88e6xxx_reg_write(chip, addr, regnum, val);
486 mv88e6xxx_ppu_access_put(ps); 484 mv88e6xxx_ppu_access_put(chip);
487 } 485 }
488 486
489 return ret; 487 return ret;
490} 488}
491 489
492static bool mv88e6xxx_6065_family(struct mv88e6xxx_priv_state *ps) 490static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip)
493{ 491{
494 return ps->info->family == MV88E6XXX_FAMILY_6065; 492 return chip->info->family == MV88E6XXX_FAMILY_6065;
495} 493}
496 494
497static bool mv88e6xxx_6095_family(struct mv88e6xxx_priv_state *ps) 495static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip)
498{ 496{
499 return ps->info->family == MV88E6XXX_FAMILY_6095; 497 return chip->info->family == MV88E6XXX_FAMILY_6095;
500} 498}
501 499
502static bool mv88e6xxx_6097_family(struct mv88e6xxx_priv_state *ps) 500static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip)
503{ 501{
504 return ps->info->family == MV88E6XXX_FAMILY_6097; 502 return chip->info->family == MV88E6XXX_FAMILY_6097;
505} 503}
506 504
507static bool mv88e6xxx_6165_family(struct mv88e6xxx_priv_state *ps) 505static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip)
508{ 506{
509 return ps->info->family == MV88E6XXX_FAMILY_6165; 507 return chip->info->family == MV88E6XXX_FAMILY_6165;
510} 508}
511 509
512static bool mv88e6xxx_6185_family(struct mv88e6xxx_priv_state *ps) 510static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip)
513{ 511{
514 return ps->info->family == MV88E6XXX_FAMILY_6185; 512 return chip->info->family == MV88E6XXX_FAMILY_6185;
515} 513}
516 514
517static bool mv88e6xxx_6320_family(struct mv88e6xxx_priv_state *ps) 515static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip)
518{ 516{
519 return ps->info->family == MV88E6XXX_FAMILY_6320; 517 return chip->info->family == MV88E6XXX_FAMILY_6320;
520} 518}
521 519
522static bool mv88e6xxx_6351_family(struct mv88e6xxx_priv_state *ps) 520static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip)
523{ 521{
524 return ps->info->family == MV88E6XXX_FAMILY_6351; 522 return chip->info->family == MV88E6XXX_FAMILY_6351;
525} 523}
526 524
527static bool mv88e6xxx_6352_family(struct mv88e6xxx_priv_state *ps) 525static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip)
528{ 526{
529 return ps->info->family == MV88E6XXX_FAMILY_6352; 527 return chip->info->family == MV88E6XXX_FAMILY_6352;
530} 528}
531 529
532static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_priv_state *ps) 530static unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
533{ 531{
534 return ps->info->num_databases; 532 return chip->info->num_databases;
535} 533}
536 534
537static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps) 535static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_chip *chip)
538{ 536{
539 /* Does the device have dedicated FID registers for ATU and VTU ops? */ 537 /* Does the device have dedicated FID registers for ATU and VTU ops? */
540 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) || 538 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
541 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) 539 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip))
542 return true; 540 return true;
543 541
544 return false; 542 return false;
@@ -551,16 +549,16 @@ static bool mv88e6xxx_has_fid_reg(struct mv88e6xxx_priv_state *ps)
551static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 549static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
552 struct phy_device *phydev) 550 struct phy_device *phydev)
553{ 551{
554 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 552 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
555 u32 reg; 553 u32 reg;
556 int ret; 554 int ret;
557 555
558 if (!phy_is_pseudo_fixed_link(phydev)) 556 if (!phy_is_pseudo_fixed_link(phydev))
559 return; 557 return;
560 558
561 mutex_lock(&ps->reg_lock); 559 mutex_lock(&chip->reg_lock);
562 560
563 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL); 561 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
564 if (ret < 0) 562 if (ret < 0)
565 goto out; 563 goto out;
566 564
@@ -574,7 +572,7 @@ static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
574 if (phydev->link) 572 if (phydev->link)
575 reg |= PORT_PCS_CTRL_LINK_UP; 573 reg |= PORT_PCS_CTRL_LINK_UP;
576 574
577 if (mv88e6xxx_6065_family(ps) && phydev->speed > SPEED_100) 575 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100)
578 goto out; 576 goto out;
579 577
580 switch (phydev->speed) { 578 switch (phydev->speed) {
@@ -596,8 +594,8 @@ static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
596 if (phydev->duplex == DUPLEX_FULL) 594 if (phydev->duplex == DUPLEX_FULL)
597 reg |= PORT_PCS_CTRL_DUPLEX_FULL; 595 reg |= PORT_PCS_CTRL_DUPLEX_FULL;
598 596
599 if ((mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps)) && 597 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) &&
600 (port >= ps->info->num_ports - 2)) { 598 (port >= chip->info->num_ports - 2)) {
601 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 599 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
602 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; 600 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK;
603 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 601 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
@@ -606,19 +604,19 @@ static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
606 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | 604 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK |
607 PORT_PCS_CTRL_RGMII_DELAY_TXCLK); 605 PORT_PCS_CTRL_RGMII_DELAY_TXCLK);
608 } 606 }
609 _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_PCS_CTRL, reg); 607 _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_PCS_CTRL, reg);
610 608
611out: 609out:
612 mutex_unlock(&ps->reg_lock); 610 mutex_unlock(&chip->reg_lock);
613} 611}
614 612
615static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps) 613static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip)
616{ 614{
617 int ret; 615 int ret;
618 int i; 616 int i;
619 617
620 for (i = 0; i < 10; i++) { 618 for (i = 0; i < 10; i++) {
621 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_OP); 619 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_OP);
622 if ((ret & GLOBAL_STATS_OP_BUSY) == 0) 620 if ((ret & GLOBAL_STATS_OP_BUSY) == 0)
623 return 0; 621 return 0;
624 } 622 }
@@ -626,30 +624,29 @@ static int _mv88e6xxx_stats_wait(struct mv88e6xxx_priv_state *ps)
626 return -ETIMEDOUT; 624 return -ETIMEDOUT;
627} 625}
628 626
629static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_priv_state *ps, 627static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
630 int port)
631{ 628{
632 int ret; 629 int ret;
633 630
634 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps)) 631 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
635 port = (port + 1) << 5; 632 port = (port + 1) << 5;
636 633
637 /* Snapshot the hardware statistics counters for this port. */ 634 /* Snapshot the hardware statistics counters for this port. */
638 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, 635 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
639 GLOBAL_STATS_OP_CAPTURE_PORT | 636 GLOBAL_STATS_OP_CAPTURE_PORT |
640 GLOBAL_STATS_OP_HIST_RX_TX | port); 637 GLOBAL_STATS_OP_HIST_RX_TX | port);
641 if (ret < 0) 638 if (ret < 0)
642 return ret; 639 return ret;
643 640
644 /* Wait for the snapshotting to complete. */ 641 /* Wait for the snapshotting to complete. */
645 ret = _mv88e6xxx_stats_wait(ps); 642 ret = _mv88e6xxx_stats_wait(chip);
646 if (ret < 0) 643 if (ret < 0)
647 return ret; 644 return ret;
648 645
649 return 0; 646 return 0;
650} 647}
651 648
652static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps, 649static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip,
653 int stat, u32 *val) 650 int stat, u32 *val)
654{ 651{
655 u32 _val; 652 u32 _val;
@@ -657,23 +654,23 @@ static void _mv88e6xxx_stats_read(struct mv88e6xxx_priv_state *ps,
657 654
658 *val = 0; 655 *val = 0;
659 656
660 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, 657 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
661 GLOBAL_STATS_OP_READ_CAPTURED | 658 GLOBAL_STATS_OP_READ_CAPTURED |
662 GLOBAL_STATS_OP_HIST_RX_TX | stat); 659 GLOBAL_STATS_OP_HIST_RX_TX | stat);
663 if (ret < 0) 660 if (ret < 0)
664 return; 661 return;
665 662
666 ret = _mv88e6xxx_stats_wait(ps); 663 ret = _mv88e6xxx_stats_wait(chip);
667 if (ret < 0) 664 if (ret < 0)
668 return; 665 return;
669 666
670 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_32); 667 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_32);
671 if (ret < 0) 668 if (ret < 0)
672 return; 669 return;
673 670
674 _val = ret << 16; 671 _val = ret << 16;
675 672
676 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_STATS_COUNTER_01); 673 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_STATS_COUNTER_01);
677 if (ret < 0) 674 if (ret < 0)
678 return; 675 return;
679 676
@@ -742,26 +739,26 @@ static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
742 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, 739 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, },
743}; 740};
744 741
745static bool mv88e6xxx_has_stat(struct mv88e6xxx_priv_state *ps, 742static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip,
746 struct mv88e6xxx_hw_stat *stat) 743 struct mv88e6xxx_hw_stat *stat)
747{ 744{
748 switch (stat->type) { 745 switch (stat->type) {
749 case BANK0: 746 case BANK0:
750 return true; 747 return true;
751 case BANK1: 748 case BANK1:
752 return mv88e6xxx_6320_family(ps); 749 return mv88e6xxx_6320_family(chip);
753 case PORT: 750 case PORT:
754 return mv88e6xxx_6095_family(ps) || 751 return mv88e6xxx_6095_family(chip) ||
755 mv88e6xxx_6185_family(ps) || 752 mv88e6xxx_6185_family(chip) ||
756 mv88e6xxx_6097_family(ps) || 753 mv88e6xxx_6097_family(chip) ||
757 mv88e6xxx_6165_family(ps) || 754 mv88e6xxx_6165_family(chip) ||
758 mv88e6xxx_6351_family(ps) || 755 mv88e6xxx_6351_family(chip) ||
759 mv88e6xxx_6352_family(ps); 756 mv88e6xxx_6352_family(chip);
760 } 757 }
761 return false; 758 return false;
762} 759}
763 760
764static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps, 761static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
765 struct mv88e6xxx_hw_stat *s, 762 struct mv88e6xxx_hw_stat *s,
766 int port) 763 int port)
767{ 764{
@@ -772,13 +769,13 @@ static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
772 769
773 switch (s->type) { 770 switch (s->type) {
774 case PORT: 771 case PORT:
775 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), s->reg); 772 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), s->reg);
776 if (ret < 0) 773 if (ret < 0)
777 return UINT64_MAX; 774 return UINT64_MAX;
778 775
779 low = ret; 776 low = ret;
780 if (s->sizeof_stat == 4) { 777 if (s->sizeof_stat == 4) {
781 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), 778 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port),
782 s->reg + 1); 779 s->reg + 1);
783 if (ret < 0) 780 if (ret < 0)
784 return UINT64_MAX; 781 return UINT64_MAX;
@@ -787,9 +784,9 @@ static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
787 break; 784 break;
788 case BANK0: 785 case BANK0:
789 case BANK1: 786 case BANK1:
790 _mv88e6xxx_stats_read(ps, s->reg, &low); 787 _mv88e6xxx_stats_read(chip, s->reg, &low);
791 if (s->sizeof_stat == 8) 788 if (s->sizeof_stat == 8)
792 _mv88e6xxx_stats_read(ps, s->reg + 1, &high); 789 _mv88e6xxx_stats_read(chip, s->reg + 1, &high);
793 } 790 }
794 value = (((u64)high) << 16) | low; 791 value = (((u64)high) << 16) | low;
795 return value; 792 return value;
@@ -798,13 +795,13 @@ static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_priv_state *ps,
798static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 795static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
799 uint8_t *data) 796 uint8_t *data)
800{ 797{
801 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 798 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
802 struct mv88e6xxx_hw_stat *stat; 799 struct mv88e6xxx_hw_stat *stat;
803 int i, j; 800 int i, j;
804 801
805 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 802 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
806 stat = &mv88e6xxx_hw_stats[i]; 803 stat = &mv88e6xxx_hw_stats[i];
807 if (mv88e6xxx_has_stat(ps, stat)) { 804 if (mv88e6xxx_has_stat(chip, stat)) {
808 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 805 memcpy(data + j * ETH_GSTRING_LEN, stat->string,
809 ETH_GSTRING_LEN); 806 ETH_GSTRING_LEN);
810 j++; 807 j++;
@@ -814,13 +811,13 @@ static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
814 811
815static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 812static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
816{ 813{
817 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 814 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
818 struct mv88e6xxx_hw_stat *stat; 815 struct mv88e6xxx_hw_stat *stat;
819 int i, j; 816 int i, j;
820 817
821 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 818 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
822 stat = &mv88e6xxx_hw_stats[i]; 819 stat = &mv88e6xxx_hw_stats[i];
823 if (mv88e6xxx_has_stat(ps, stat)) 820 if (mv88e6xxx_has_stat(chip, stat))
824 j++; 821 j++;
825 } 822 }
826 return j; 823 return j;
@@ -829,27 +826,27 @@ static int mv88e6xxx_get_sset_count(struct dsa_switch *ds)
829static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 826static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
830 uint64_t *data) 827 uint64_t *data)
831{ 828{
832 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 829 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
833 struct mv88e6xxx_hw_stat *stat; 830 struct mv88e6xxx_hw_stat *stat;
834 int ret; 831 int ret;
835 int i, j; 832 int i, j;
836 833
837 mutex_lock(&ps->reg_lock); 834 mutex_lock(&chip->reg_lock);
838 835
839 ret = _mv88e6xxx_stats_snapshot(ps, port); 836 ret = _mv88e6xxx_stats_snapshot(chip, port);
840 if (ret < 0) { 837 if (ret < 0) {
841 mutex_unlock(&ps->reg_lock); 838 mutex_unlock(&chip->reg_lock);
842 return; 839 return;
843 } 840 }
844 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 841 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
845 stat = &mv88e6xxx_hw_stats[i]; 842 stat = &mv88e6xxx_hw_stats[i];
846 if (mv88e6xxx_has_stat(ps, stat)) { 843 if (mv88e6xxx_has_stat(chip, stat)) {
847 data[j] = _mv88e6xxx_get_ethtool_stat(ps, stat, port); 844 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port);
848 j++; 845 j++;
849 } 846 }
850 } 847 }
851 848
852 mutex_unlock(&ps->reg_lock); 849 mutex_unlock(&chip->reg_lock);
853} 850}
854 851
855static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 852static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
@@ -860,7 +857,7 @@ static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
860static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 857static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
861 struct ethtool_regs *regs, void *_p) 858 struct ethtool_regs *regs, void *_p)
862{ 859{
863 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 860 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
864 u16 *p = _p; 861 u16 *p = _p;
865 int i; 862 int i;
866 863
@@ -868,20 +865,20 @@ static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
868 865
869 memset(p, 0xff, 32 * sizeof(u16)); 866 memset(p, 0xff, 32 * sizeof(u16));
870 867
871 mutex_lock(&ps->reg_lock); 868 mutex_lock(&chip->reg_lock);
872 869
873 for (i = 0; i < 32; i++) { 870 for (i = 0; i < 32; i++) {
874 int ret; 871 int ret;
875 872
876 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), i); 873 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), i);
877 if (ret >= 0) 874 if (ret >= 0)
878 p[i] = ret; 875 p[i] = ret;
879 } 876 }
880 877
881 mutex_unlock(&ps->reg_lock); 878 mutex_unlock(&chip->reg_lock);
882} 879}
883 880
884static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset, 881static int _mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg, int offset,
885 u16 mask) 882 u16 mask)
886{ 883{
887 unsigned long timeout = jiffies + HZ / 10; 884 unsigned long timeout = jiffies + HZ / 10;
@@ -889,7 +886,7 @@ static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
889 while (time_before(jiffies, timeout)) { 886 while (time_before(jiffies, timeout)) {
890 int ret; 887 int ret;
891 888
892 ret = _mv88e6xxx_reg_read(ps, reg, offset); 889 ret = _mv88e6xxx_reg_read(chip, reg, offset);
893 if (ret < 0) 890 if (ret < 0)
894 return ret; 891 return ret;
895 if (!(ret & mask)) 892 if (!(ret & mask))
@@ -900,48 +897,48 @@ static int _mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, int offset,
900 return -ETIMEDOUT; 897 return -ETIMEDOUT;
901} 898}
902 899
903static int mv88e6xxx_wait(struct mv88e6xxx_priv_state *ps, int reg, 900static int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int reg,
904 int offset, u16 mask) 901 int offset, u16 mask)
905{ 902{
906 int ret; 903 int ret;
907 904
908 mutex_lock(&ps->reg_lock); 905 mutex_lock(&chip->reg_lock);
909 ret = _mv88e6xxx_wait(ps, reg, offset, mask); 906 ret = _mv88e6xxx_wait(chip, reg, offset, mask);
910 mutex_unlock(&ps->reg_lock); 907 mutex_unlock(&chip->reg_lock);
911 908
912 return ret; 909 return ret;
913} 910}
914 911
915static int mv88e6xxx_mdio_wait(struct mv88e6xxx_priv_state *ps) 912static int mv88e6xxx_mdio_wait(struct mv88e6xxx_chip *chip)
916{ 913{
917 return _mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, 914 return _mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
918 GLOBAL2_SMI_OP_BUSY); 915 GLOBAL2_SMI_OP_BUSY);
919} 916}
920 917
921static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds) 918static int mv88e6xxx_eeprom_load_wait(struct dsa_switch *ds)
922{ 919{
923 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 920 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
924 921
925 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, 922 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
926 GLOBAL2_EEPROM_OP_LOAD); 923 GLOBAL2_EEPROM_OP_LOAD);
927} 924}
928 925
929static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds) 926static int mv88e6xxx_eeprom_busy_wait(struct dsa_switch *ds)
930{ 927{
931 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 928 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
932 929
933 return mv88e6xxx_wait(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, 930 return mv88e6xxx_wait(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
934 GLOBAL2_EEPROM_OP_BUSY); 931 GLOBAL2_EEPROM_OP_BUSY);
935} 932}
936 933
937static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr) 934static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
938{ 935{
939 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 936 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
940 int ret; 937 int ret;
941 938
942 mutex_lock(&ps->eeprom_mutex); 939 mutex_lock(&chip->eeprom_mutex);
943 940
944 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, 941 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
945 GLOBAL2_EEPROM_OP_READ | 942 GLOBAL2_EEPROM_OP_READ |
946 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK)); 943 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
947 if (ret < 0) 944 if (ret < 0)
@@ -951,18 +948,18 @@ static int mv88e6xxx_read_eeprom_word(struct dsa_switch *ds, int addr)
951 if (ret < 0) 948 if (ret < 0)
952 goto error; 949 goto error;
953 950
954 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA); 951 ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA);
955error: 952error:
956 mutex_unlock(&ps->eeprom_mutex); 953 mutex_unlock(&chip->eeprom_mutex);
957 return ret; 954 return ret;
958} 955}
959 956
960static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 957static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
961{ 958{
962 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 959 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
963 960
964 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) 961 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
965 return ps->eeprom_len; 962 return chip->eeprom_len;
966 963
967 return 0; 964 return 0;
968} 965}
@@ -970,12 +967,12 @@ static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
970static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 967static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
971 struct ethtool_eeprom *eeprom, u8 *data) 968 struct ethtool_eeprom *eeprom, u8 *data)
972{ 969{
973 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 970 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
974 int offset; 971 int offset;
975 int len; 972 int len;
976 int ret; 973 int ret;
977 974
978 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) 975 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
979 return -EOPNOTSUPP; 976 return -EOPNOTSUPP;
980 977
981 offset = eeprom->offset; 978 offset = eeprom->offset;
@@ -1036,10 +1033,10 @@ static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
1036 1033
1037static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds) 1034static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
1038{ 1035{
1039 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 1036 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1040 int ret; 1037 int ret;
1041 1038
1042 ret = mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP); 1039 ret = mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP);
1043 if (ret < 0) 1040 if (ret < 0)
1044 return ret; 1041 return ret;
1045 1042
@@ -1052,16 +1049,16 @@ static int mv88e6xxx_eeprom_is_readonly(struct dsa_switch *ds)
1052static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr, 1049static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
1053 u16 data) 1050 u16 data)
1054{ 1051{
1055 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 1052 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1056 int ret; 1053 int ret;
1057 1054
1058 mutex_lock(&ps->eeprom_mutex); 1055 mutex_lock(&chip->eeprom_mutex);
1059 1056
1060 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data); 1057 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_DATA, data);
1061 if (ret < 0) 1058 if (ret < 0)
1062 goto error; 1059 goto error;
1063 1060
1064 ret = mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_EEPROM_OP, 1061 ret = mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_EEPROM_OP,
1065 GLOBAL2_EEPROM_OP_WRITE | 1062 GLOBAL2_EEPROM_OP_WRITE |
1066 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK)); 1063 (addr & GLOBAL2_EEPROM_OP_ADDR_MASK));
1067 if (ret < 0) 1064 if (ret < 0)
@@ -1069,19 +1066,19 @@ static int mv88e6xxx_write_eeprom_word(struct dsa_switch *ds, int addr,
1069 1066
1070 ret = mv88e6xxx_eeprom_busy_wait(ds); 1067 ret = mv88e6xxx_eeprom_busy_wait(ds);
1071error: 1068error:
1072 mutex_unlock(&ps->eeprom_mutex); 1069 mutex_unlock(&chip->eeprom_mutex);
1073 return ret; 1070 return ret;
1074} 1071}
1075 1072
1076static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 1073static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
1077 struct ethtool_eeprom *eeprom, u8 *data) 1074 struct ethtool_eeprom *eeprom, u8 *data)
1078{ 1075{
1079 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 1076 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1080 int offset; 1077 int offset;
1081 int ret; 1078 int ret;
1082 int len; 1079 int len;
1083 1080
1084 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) 1081 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
1085 return -EOPNOTSUPP; 1082 return -EOPNOTSUPP;
1086 1083
1087 if (eeprom->magic != 0xc3ec4951) 1084 if (eeprom->magic != 0xc3ec4951)
@@ -1153,67 +1150,67 @@ static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
1153 return 0; 1150 return 0;
1154} 1151}
1155 1152
1156static int _mv88e6xxx_atu_wait(struct mv88e6xxx_priv_state *ps) 1153static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip)
1157{ 1154{
1158 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_ATU_OP, 1155 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_ATU_OP,
1159 GLOBAL_ATU_OP_BUSY); 1156 GLOBAL_ATU_OP_BUSY);
1160} 1157}
1161 1158
1162static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_priv_state *ps, 1159static int mv88e6xxx_mdio_read_indirect(struct mv88e6xxx_chip *chip,
1163 int addr, int regnum) 1160 int addr, int regnum)
1164{ 1161{
1165 int ret; 1162 int ret;
1166 1163
1167 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, 1164 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
1168 GLOBAL2_SMI_OP_22_READ | (addr << 5) | 1165 GLOBAL2_SMI_OP_22_READ | (addr << 5) |
1169 regnum); 1166 regnum);
1170 if (ret < 0) 1167 if (ret < 0)
1171 return ret; 1168 return ret;
1172 1169
1173 ret = mv88e6xxx_mdio_wait(ps); 1170 ret = mv88e6xxx_mdio_wait(chip);
1174 if (ret < 0) 1171 if (ret < 0)
1175 return ret; 1172 return ret;
1176 1173
1177 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA); 1174 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA);
1178 1175
1179 return ret; 1176 return ret;
1180} 1177}
1181 1178
1182static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_priv_state *ps, 1179static int mv88e6xxx_mdio_write_indirect(struct mv88e6xxx_chip *chip,
1183 int addr, int regnum, u16 val) 1180 int addr, int regnum, u16 val)
1184{ 1181{
1185 int ret; 1182 int ret;
1186 1183
1187 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_DATA, val); 1184 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_DATA, val);
1188 if (ret < 0) 1185 if (ret < 0)
1189 return ret; 1186 return ret;
1190 1187
1191 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SMI_OP, 1188 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SMI_OP,
1192 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) | 1189 GLOBAL2_SMI_OP_22_WRITE | (addr << 5) |
1193 regnum); 1190 regnum);
1194 1191
1195 return mv88e6xxx_mdio_wait(ps); 1192 return mv88e6xxx_mdio_wait(chip);
1196} 1193}
1197 1194
1198static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 1195static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1199 struct ethtool_eee *e) 1196 struct ethtool_eee *e)
1200{ 1197{
1201 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 1198 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1202 int reg; 1199 int reg;
1203 1200
1204 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE)) 1201 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1205 return -EOPNOTSUPP; 1202 return -EOPNOTSUPP;
1206 1203
1207 mutex_lock(&ps->reg_lock); 1204 mutex_lock(&chip->reg_lock);
1208 1205
1209 reg = mv88e6xxx_mdio_read_indirect(ps, port, 16); 1206 reg = mv88e6xxx_mdio_read_indirect(chip, port, 16);
1210 if (reg < 0) 1207 if (reg < 0)
1211 goto out; 1208 goto out;
1212 1209
1213 e->eee_enabled = !!(reg & 0x0200); 1210 e->eee_enabled = !!(reg & 0x0200);
1214 e->tx_lpi_enabled = !!(reg & 0x0100); 1211 e->tx_lpi_enabled = !!(reg & 0x0100);
1215 1212
1216 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS); 1213 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
1217 if (reg < 0) 1214 if (reg < 0)
1218 goto out; 1215 goto out;
1219 1216
@@ -1221,23 +1218,23 @@ static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port,
1221 reg = 0; 1218 reg = 0;
1222 1219
1223out: 1220out:
1224 mutex_unlock(&ps->reg_lock); 1221 mutex_unlock(&chip->reg_lock);
1225 return reg; 1222 return reg;
1226} 1223}
1227 1224
1228static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 1225static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1229 struct phy_device *phydev, struct ethtool_eee *e) 1226 struct phy_device *phydev, struct ethtool_eee *e)
1230{ 1227{
1231 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 1228 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1232 int reg; 1229 int reg;
1233 int ret; 1230 int ret;
1234 1231
1235 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEE)) 1232 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE))
1236 return -EOPNOTSUPP; 1233 return -EOPNOTSUPP;
1237 1234
1238 mutex_lock(&ps->reg_lock); 1235 mutex_lock(&chip->reg_lock);
1239 1236
1240 ret = mv88e6xxx_mdio_read_indirect(ps, port, 16); 1237 ret = mv88e6xxx_mdio_read_indirect(chip, port, 16);
1241 if (ret < 0) 1238 if (ret < 0)
1242 goto out; 1239 goto out;
1243 1240
@@ -1247,28 +1244,29 @@ static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port,
1247 if (e->tx_lpi_enabled) 1244 if (e->tx_lpi_enabled)
1248 reg |= 0x0100; 1245 reg |= 0x0100;
1249 1246
1250 ret = mv88e6xxx_mdio_write_indirect(ps, port, 16, reg); 1247 ret = mv88e6xxx_mdio_write_indirect(chip, port, 16, reg);
1251out: 1248out:
1252 mutex_unlock(&ps->reg_lock); 1249 mutex_unlock(&chip->reg_lock);
1253 1250
1254 return ret; 1251 return ret;
1255} 1252}
1256 1253
1257static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd) 1254static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd)
1258{ 1255{
1259 int ret; 1256 int ret;
1260 1257
1261 if (mv88e6xxx_has_fid_reg(ps)) { 1258 if (mv88e6xxx_has_fid_reg(chip)) {
1262 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_FID, fid); 1259 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_FID,
1260 fid);
1263 if (ret < 0) 1261 if (ret < 0)
1264 return ret; 1262 return ret;
1265 } else if (mv88e6xxx_num_databases(ps) == 256) { 1263 } else if (mv88e6xxx_num_databases(chip) == 256) {
1266 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 1264 /* ATU DBNum[7:4] are located in ATU Control 15:12 */
1267 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL); 1265 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL);
1268 if (ret < 0) 1266 if (ret < 0)
1269 return ret; 1267 return ret;
1270 1268
1271 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL, 1269 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
1272 (ret & 0xfff) | 1270 (ret & 0xfff) |
1273 ((fid << 8) & 0xf000)); 1271 ((fid << 8) & 0xf000));
1274 if (ret < 0) 1272 if (ret < 0)
@@ -1278,14 +1276,14 @@ static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_priv_state *ps, u16 fid, u16 cmd)
1278 cmd |= fid & 0xf; 1276 cmd |= fid & 0xf;
1279 } 1277 }
1280 1278
1281 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_OP, cmd); 1279 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_OP, cmd);
1282 if (ret < 0) 1280 if (ret < 0)
1283 return ret; 1281 return ret;
1284 1282
1285 return _mv88e6xxx_atu_wait(ps); 1283 return _mv88e6xxx_atu_wait(chip);
1286} 1284}
1287 1285
1288static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps, 1286static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip,
1289 struct mv88e6xxx_atu_entry *entry) 1287 struct mv88e6xxx_atu_entry *entry)
1290{ 1288{
1291 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; 1289 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK;
@@ -1305,21 +1303,21 @@ static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_priv_state *ps,
1305 data |= (entry->portv_trunkid << shift) & mask; 1303 data |= (entry->portv_trunkid << shift) & mask;
1306 } 1304 }
1307 1305
1308 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_DATA, data); 1306 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_DATA, data);
1309} 1307}
1310 1308
1311static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps, 1309static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip,
1312 struct mv88e6xxx_atu_entry *entry, 1310 struct mv88e6xxx_atu_entry *entry,
1313 bool static_too) 1311 bool static_too)
1314{ 1312{
1315 int op; 1313 int op;
1316 int err; 1314 int err;
1317 1315
1318 err = _mv88e6xxx_atu_wait(ps); 1316 err = _mv88e6xxx_atu_wait(chip);
1319 if (err) 1317 if (err)
1320 return err; 1318 return err;
1321 1319
1322 err = _mv88e6xxx_atu_data_write(ps, entry); 1320 err = _mv88e6xxx_atu_data_write(chip, entry);
1323 if (err) 1321 if (err)
1324 return err; 1322 return err;
1325 1323
@@ -1331,10 +1329,10 @@ static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_priv_state *ps,
1331 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; 1329 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC;
1332 } 1330 }
1333 1331
1334 return _mv88e6xxx_atu_cmd(ps, entry->fid, op); 1332 return _mv88e6xxx_atu_cmd(chip, entry->fid, op);
1335} 1333}
1336 1334
1337static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps, 1335static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip,
1338 u16 fid, bool static_too) 1336 u16 fid, bool static_too)
1339{ 1337{
1340 struct mv88e6xxx_atu_entry entry = { 1338 struct mv88e6xxx_atu_entry entry = {
@@ -1342,10 +1340,10 @@ static int _mv88e6xxx_atu_flush(struct mv88e6xxx_priv_state *ps,
1342 .state = 0, /* EntryState bits must be 0 */ 1340 .state = 0, /* EntryState bits must be 0 */
1343 }; 1341 };
1344 1342
1345 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too); 1343 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1346} 1344}
1347 1345
1348static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid, 1346static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid,
1349 int from_port, int to_port, bool static_too) 1347 int from_port, int to_port, bool static_too)
1350{ 1348{
1351 struct mv88e6xxx_atu_entry entry = { 1349 struct mv88e6xxx_atu_entry entry = {
@@ -1360,14 +1358,14 @@ static int _mv88e6xxx_atu_move(struct mv88e6xxx_priv_state *ps, u16 fid,
1360 entry.portv_trunkid = (to_port & 0x0f) << 4; 1358 entry.portv_trunkid = (to_port & 0x0f) << 4;
1361 entry.portv_trunkid |= from_port & 0x0f; 1359 entry.portv_trunkid |= from_port & 0x0f;
1362 1360
1363 return _mv88e6xxx_atu_flush_move(ps, &entry, static_too); 1361 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too);
1364} 1362}
1365 1363
1366static int _mv88e6xxx_atu_remove(struct mv88e6xxx_priv_state *ps, u16 fid, 1364static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid,
1367 int port, bool static_too) 1365 int port, bool static_too)
1368{ 1366{
1369 /* Destination port 0xF means remove the entries */ 1367 /* Destination port 0xF means remove the entries */
1370 return _mv88e6xxx_atu_move(ps, fid, port, 0x0f, static_too); 1368 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too);
1371} 1369}
1372 1370
1373static const char * const mv88e6xxx_port_state_names[] = { 1371static const char * const mv88e6xxx_port_state_names[] = {
@@ -1377,14 +1375,14 @@ static const char * const mv88e6xxx_port_state_names[] = {
1377 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", 1375 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding",
1378}; 1376};
1379 1377
1380static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port, 1378static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port,
1381 u8 state) 1379 u8 state)
1382{ 1380{
1383 struct dsa_switch *ds = ps->ds; 1381 struct dsa_switch *ds = chip->ds;
1384 int reg, ret = 0; 1382 int reg, ret = 0;
1385 u8 oldstate; 1383 u8 oldstate;
1386 1384
1387 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL); 1385 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL);
1388 if (reg < 0) 1386 if (reg < 0)
1389 return reg; 1387 return reg;
1390 1388
@@ -1399,13 +1397,13 @@ static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1399 oldstate == PORT_CONTROL_STATE_FORWARDING) && 1397 oldstate == PORT_CONTROL_STATE_FORWARDING) &&
1400 (state == PORT_CONTROL_STATE_DISABLED || 1398 (state == PORT_CONTROL_STATE_DISABLED ||
1401 state == PORT_CONTROL_STATE_BLOCKING)) { 1399 state == PORT_CONTROL_STATE_BLOCKING)) {
1402 ret = _mv88e6xxx_atu_remove(ps, 0, port, false); 1400 ret = _mv88e6xxx_atu_remove(chip, 0, port, false);
1403 if (ret) 1401 if (ret)
1404 return ret; 1402 return ret;
1405 } 1403 }
1406 1404
1407 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state; 1405 reg = (reg & ~PORT_CONTROL_STATE_MASK) | state;
1408 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL, 1406 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL,
1409 reg); 1407 reg);
1410 if (ret) 1408 if (ret)
1411 return ret; 1409 return ret;
@@ -1418,12 +1416,11 @@ static int _mv88e6xxx_port_state(struct mv88e6xxx_priv_state *ps, int port,
1418 return ret; 1416 return ret;
1419} 1417}
1420 1418
1421static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps, 1419static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port)
1422 int port)
1423{ 1420{
1424 struct net_device *bridge = ps->ports[port].bridge_dev; 1421 struct net_device *bridge = chip->ports[port].bridge_dev;
1425 const u16 mask = (1 << ps->info->num_ports) - 1; 1422 const u16 mask = (1 << chip->info->num_ports) - 1;
1426 struct dsa_switch *ds = ps->ds; 1423 struct dsa_switch *ds = chip->ds;
1427 u16 output_ports = 0; 1424 u16 output_ports = 0;
1428 int reg; 1425 int reg;
1429 int i; 1426 int i;
@@ -1432,9 +1429,9 @@ static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1432 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 1429 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
1433 output_ports = mask; 1430 output_ports = mask;
1434 } else { 1431 } else {
1435 for (i = 0; i < ps->info->num_ports; ++i) { 1432 for (i = 0; i < chip->info->num_ports; ++i) {
1436 /* allow sending frames to every group member */ 1433 /* allow sending frames to every group member */
1437 if (bridge && ps->ports[i].bridge_dev == bridge) 1434 if (bridge && chip->ports[i].bridge_dev == bridge)
1438 output_ports |= BIT(i); 1435 output_ports |= BIT(i);
1439 1436
1440 /* allow sending frames to CPU port and DSA link(s) */ 1437 /* allow sending frames to CPU port and DSA link(s) */
@@ -1446,24 +1443,24 @@ static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_priv_state *ps,
1446 /* prevent frames from going back out of the port they came in on */ 1443 /* prevent frames from going back out of the port they came in on */
1447 output_ports &= ~BIT(port); 1444 output_ports &= ~BIT(port);
1448 1445
1449 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN); 1446 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1450 if (reg < 0) 1447 if (reg < 0)
1451 return reg; 1448 return reg;
1452 1449
1453 reg &= ~mask; 1450 reg &= ~mask;
1454 reg |= output_ports & mask; 1451 reg |= output_ports & mask;
1455 1452
1456 return _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, reg); 1453 return _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN, reg);
1457} 1454}
1458 1455
1459static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1456static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1460 u8 state) 1457 u8 state)
1461{ 1458{
1462 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 1459 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1463 int stp_state; 1460 int stp_state;
1464 int err; 1461 int err;
1465 1462
1466 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_PORTSTATE)) 1463 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PORTSTATE))
1467 return; 1464 return;
1468 1465
1469 switch (state) { 1466 switch (state) {
@@ -1483,9 +1480,9 @@ static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1483 break; 1480 break;
1484 } 1481 }
1485 1482
1486 mutex_lock(&ps->reg_lock); 1483 mutex_lock(&chip->reg_lock);
1487 err = _mv88e6xxx_port_state(ps, port, stp_state); 1484 err = _mv88e6xxx_port_state(chip, port, stp_state);
1488 mutex_unlock(&ps->reg_lock); 1485 mutex_unlock(&chip->reg_lock);
1489 1486
1490 if (err) 1487 if (err)
1491 netdev_err(ds->ports[port].netdev, 1488 netdev_err(ds->ports[port].netdev,
@@ -1493,14 +1490,14 @@ static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1493 mv88e6xxx_port_state_names[stp_state]); 1490 mv88e6xxx_port_state_names[stp_state]);
1494} 1491}
1495 1492
1496static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port, 1493static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port,
1497 u16 *new, u16 *old) 1494 u16 *new, u16 *old)
1498{ 1495{
1499 struct dsa_switch *ds = ps->ds; 1496 struct dsa_switch *ds = chip->ds;
1500 u16 pvid; 1497 u16 pvid;
1501 int ret; 1498 int ret;
1502 1499
1503 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_DEFAULT_VLAN); 1500 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_DEFAULT_VLAN);
1504 if (ret < 0) 1501 if (ret < 0)
1505 return ret; 1502 return ret;
1506 1503
@@ -1510,7 +1507,7 @@ static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1510 ret &= ~PORT_DEFAULT_VLAN_MASK; 1507 ret &= ~PORT_DEFAULT_VLAN_MASK;
1511 ret |= *new & PORT_DEFAULT_VLAN_MASK; 1508 ret |= *new & PORT_DEFAULT_VLAN_MASK;
1512 1509
1513 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 1510 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
1514 PORT_DEFAULT_VLAN, ret); 1511 PORT_DEFAULT_VLAN, ret);
1515 if (ret < 0) 1512 if (ret < 0)
1516 return ret; 1513 return ret;
@@ -1525,47 +1522,47 @@ static int _mv88e6xxx_port_pvid(struct mv88e6xxx_priv_state *ps, int port,
1525 return 0; 1522 return 0;
1526} 1523}
1527 1524
1528static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_priv_state *ps, 1525static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip,
1529 int port, u16 *pvid) 1526 int port, u16 *pvid)
1530{ 1527{
1531 return _mv88e6xxx_port_pvid(ps, port, NULL, pvid); 1528 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid);
1532} 1529}
1533 1530
1534static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_priv_state *ps, 1531static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip,
1535 int port, u16 pvid) 1532 int port, u16 pvid)
1536{ 1533{
1537 return _mv88e6xxx_port_pvid(ps, port, &pvid, NULL); 1534 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL);
1538} 1535}
1539 1536
1540static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_priv_state *ps) 1537static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip)
1541{ 1538{
1542 return _mv88e6xxx_wait(ps, REG_GLOBAL, GLOBAL_VTU_OP, 1539 return _mv88e6xxx_wait(chip, REG_GLOBAL, GLOBAL_VTU_OP,
1543 GLOBAL_VTU_OP_BUSY); 1540 GLOBAL_VTU_OP_BUSY);
1544} 1541}
1545 1542
1546static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_priv_state *ps, u16 op) 1543static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op)
1547{ 1544{
1548 int ret; 1545 int ret;
1549 1546
1550 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_OP, op); 1547 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_OP, op);
1551 if (ret < 0) 1548 if (ret < 0)
1552 return ret; 1549 return ret;
1553 1550
1554 return _mv88e6xxx_vtu_wait(ps); 1551 return _mv88e6xxx_vtu_wait(chip);
1555} 1552}
1556 1553
1557static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_priv_state *ps) 1554static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip)
1558{ 1555{
1559 int ret; 1556 int ret;
1560 1557
1561 ret = _mv88e6xxx_vtu_wait(ps); 1558 ret = _mv88e6xxx_vtu_wait(chip);
1562 if (ret < 0) 1559 if (ret < 0)
1563 return ret; 1560 return ret;
1564 1561
1565 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_FLUSH_ALL); 1562 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL);
1566} 1563}
1567 1564
1568static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps, 1565static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip,
1569 struct mv88e6xxx_vtu_stu_entry *entry, 1566 struct mv88e6xxx_vtu_stu_entry *entry,
1570 unsigned int nibble_offset) 1567 unsigned int nibble_offset)
1571{ 1568{
@@ -1574,7 +1571,7 @@ static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
1574 int ret; 1571 int ret;
1575 1572
1576 for (i = 0; i < 3; ++i) { 1573 for (i = 0; i < 3; ++i) {
1577 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 1574 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1578 GLOBAL_VTU_DATA_0_3 + i); 1575 GLOBAL_VTU_DATA_0_3 + i);
1579 if (ret < 0) 1576 if (ret < 0)
1580 return ret; 1577 return ret;
@@ -1582,7 +1579,7 @@ static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
1582 regs[i] = ret; 1579 regs[i] = ret;
1583 } 1580 }
1584 1581
1585 for (i = 0; i < ps->info->num_ports; ++i) { 1582 for (i = 0; i < chip->info->num_ports; ++i) {
1586 unsigned int shift = (i % 4) * 4 + nibble_offset; 1583 unsigned int shift = (i % 4) * 4 + nibble_offset;
1587 u16 reg = regs[i / 4]; 1584 u16 reg = regs[i / 4];
1588 1585
@@ -1592,19 +1589,19 @@ static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_priv_state *ps,
1592 return 0; 1589 return 0;
1593} 1590}
1594 1591
1595static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_priv_state *ps, 1592static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip,
1596 struct mv88e6xxx_vtu_stu_entry *entry) 1593 struct mv88e6xxx_vtu_stu_entry *entry)
1597{ 1594{
1598 return _mv88e6xxx_vtu_stu_data_read(ps, entry, 0); 1595 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0);
1599} 1596}
1600 1597
1601static int mv88e6xxx_stu_data_read(struct mv88e6xxx_priv_state *ps, 1598static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip,
1602 struct mv88e6xxx_vtu_stu_entry *entry) 1599 struct mv88e6xxx_vtu_stu_entry *entry)
1603{ 1600{
1604 return _mv88e6xxx_vtu_stu_data_read(ps, entry, 2); 1601 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2);
1605} 1602}
1606 1603
1607static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps, 1604static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip,
1608 struct mv88e6xxx_vtu_stu_entry *entry, 1605 struct mv88e6xxx_vtu_stu_entry *entry,
1609 unsigned int nibble_offset) 1606 unsigned int nibble_offset)
1610{ 1607{
@@ -1612,7 +1609,7 @@ static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
1612 int i; 1609 int i;
1613 int ret; 1610 int ret;
1614 1611
1615 for (i = 0; i < ps->info->num_ports; ++i) { 1612 for (i = 0; i < chip->info->num_ports; ++i) {
1616 unsigned int shift = (i % 4) * 4 + nibble_offset; 1613 unsigned int shift = (i % 4) * 4 + nibble_offset;
1617 u8 data = entry->data[i]; 1614 u8 data = entry->data[i];
1618 1615
@@ -1620,7 +1617,7 @@ static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
1620 } 1617 }
1621 1618
1622 for (i = 0; i < 3; ++i) { 1619 for (i = 0; i < 3; ++i) {
1623 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 1620 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL,
1624 GLOBAL_VTU_DATA_0_3 + i, regs[i]); 1621 GLOBAL_VTU_DATA_0_3 + i, regs[i]);
1625 if (ret < 0) 1622 if (ret < 0)
1626 return ret; 1623 return ret;
@@ -1629,39 +1626,39 @@ static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_priv_state *ps,
1629 return 0; 1626 return 0;
1630} 1627}
1631 1628
1632static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_priv_state *ps, 1629static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip,
1633 struct mv88e6xxx_vtu_stu_entry *entry) 1630 struct mv88e6xxx_vtu_stu_entry *entry)
1634{ 1631{
1635 return _mv88e6xxx_vtu_stu_data_write(ps, entry, 0); 1632 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0);
1636} 1633}
1637 1634
1638static int mv88e6xxx_stu_data_write(struct mv88e6xxx_priv_state *ps, 1635static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip,
1639 struct mv88e6xxx_vtu_stu_entry *entry) 1636 struct mv88e6xxx_vtu_stu_entry *entry)
1640{ 1637{
1641 return _mv88e6xxx_vtu_stu_data_write(ps, entry, 2); 1638 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2);
1642} 1639}
1643 1640
1644static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_priv_state *ps, u16 vid) 1641static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid)
1645{ 1642{
1646 return _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, 1643 return _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID,
1647 vid & GLOBAL_VTU_VID_MASK); 1644 vid & GLOBAL_VTU_VID_MASK);
1648} 1645}
1649 1646
1650static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps, 1647static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1651 struct mv88e6xxx_vtu_stu_entry *entry) 1648 struct mv88e6xxx_vtu_stu_entry *entry)
1652{ 1649{
1653 struct mv88e6xxx_vtu_stu_entry next = { 0 }; 1650 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1654 int ret; 1651 int ret;
1655 1652
1656 ret = _mv88e6xxx_vtu_wait(ps); 1653 ret = _mv88e6xxx_vtu_wait(chip);
1657 if (ret < 0) 1654 if (ret < 0)
1658 return ret; 1655 return ret;
1659 1656
1660 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_VTU_GET_NEXT); 1657 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
1661 if (ret < 0) 1658 if (ret < 0)
1662 return ret; 1659 return ret;
1663 1660
1664 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID); 1661 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1665 if (ret < 0) 1662 if (ret < 0)
1666 return ret; 1663 return ret;
1667 1664
@@ -1669,22 +1666,22 @@ static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
1669 next.valid = !!(ret & GLOBAL_VTU_VID_VALID); 1666 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1670 1667
1671 if (next.valid) { 1668 if (next.valid) {
1672 ret = mv88e6xxx_vtu_data_read(ps, &next); 1669 ret = mv88e6xxx_vtu_data_read(chip, &next);
1673 if (ret < 0) 1670 if (ret < 0)
1674 return ret; 1671 return ret;
1675 1672
1676 if (mv88e6xxx_has_fid_reg(ps)) { 1673 if (mv88e6xxx_has_fid_reg(chip)) {
1677 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 1674 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1678 GLOBAL_VTU_FID); 1675 GLOBAL_VTU_FID);
1679 if (ret < 0) 1676 if (ret < 0)
1680 return ret; 1677 return ret;
1681 1678
1682 next.fid = ret & GLOBAL_VTU_FID_MASK; 1679 next.fid = ret & GLOBAL_VTU_FID_MASK;
1683 } else if (mv88e6xxx_num_databases(ps) == 256) { 1680 } else if (mv88e6xxx_num_databases(chip) == 256) {
1684 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1681 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1685 * VTU DBNum[3:0] are located in VTU Operation 3:0 1682 * VTU DBNum[3:0] are located in VTU Operation 3:0
1686 */ 1683 */
1687 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 1684 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1688 GLOBAL_VTU_OP); 1685 GLOBAL_VTU_OP);
1689 if (ret < 0) 1686 if (ret < 0)
1690 return ret; 1687 return ret;
@@ -1693,8 +1690,8 @@ static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_priv_state *ps,
1693 next.fid |= ret & 0xf; 1690 next.fid |= ret & 0xf;
1694 } 1691 }
1695 1692
1696 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) { 1693 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1697 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 1694 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
1698 GLOBAL_VTU_SID); 1695 GLOBAL_VTU_SID);
1699 if (ret < 0) 1696 if (ret < 0)
1700 return ret; 1697 return ret;
@@ -1711,26 +1708,26 @@ static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1711 struct switchdev_obj_port_vlan *vlan, 1708 struct switchdev_obj_port_vlan *vlan,
1712 int (*cb)(struct switchdev_obj *obj)) 1709 int (*cb)(struct switchdev_obj *obj))
1713{ 1710{
1714 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 1711 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
1715 struct mv88e6xxx_vtu_stu_entry next; 1712 struct mv88e6xxx_vtu_stu_entry next;
1716 u16 pvid; 1713 u16 pvid;
1717 int err; 1714 int err;
1718 1715
1719 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) 1716 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
1720 return -EOPNOTSUPP; 1717 return -EOPNOTSUPP;
1721 1718
1722 mutex_lock(&ps->reg_lock); 1719 mutex_lock(&chip->reg_lock);
1723 1720
1724 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid); 1721 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
1725 if (err) 1722 if (err)
1726 goto unlock; 1723 goto unlock;
1727 1724
1728 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK); 1725 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1729 if (err) 1726 if (err)
1730 goto unlock; 1727 goto unlock;
1731 1728
1732 do { 1729 do {
1733 err = _mv88e6xxx_vtu_getnext(ps, &next); 1730 err = _mv88e6xxx_vtu_getnext(chip, &next);
1734 if (err) 1731 if (err)
1735 break; 1732 break;
1736 1733
@@ -1757,19 +1754,19 @@ static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port,
1757 } while (next.vid < GLOBAL_VTU_VID_MASK); 1754 } while (next.vid < GLOBAL_VTU_VID_MASK);
1758 1755
1759unlock: 1756unlock:
1760 mutex_unlock(&ps->reg_lock); 1757 mutex_unlock(&chip->reg_lock);
1761 1758
1762 return err; 1759 return err;
1763} 1760}
1764 1761
1765static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps, 1762static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1766 struct mv88e6xxx_vtu_stu_entry *entry) 1763 struct mv88e6xxx_vtu_stu_entry *entry)
1767{ 1764{
1768 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; 1765 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
1769 u16 reg = 0; 1766 u16 reg = 0;
1770 int ret; 1767 int ret;
1771 1768
1772 ret = _mv88e6xxx_vtu_wait(ps); 1769 ret = _mv88e6xxx_vtu_wait(chip);
1773 if (ret < 0) 1770 if (ret < 0)
1774 return ret; 1771 return ret;
1775 1772
@@ -1777,23 +1774,25 @@ static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
1777 goto loadpurge; 1774 goto loadpurge;
1778 1775
1779 /* Write port member tags */ 1776 /* Write port member tags */
1780 ret = mv88e6xxx_vtu_data_write(ps, entry); 1777 ret = mv88e6xxx_vtu_data_write(chip, entry);
1781 if (ret < 0) 1778 if (ret < 0)
1782 return ret; 1779 return ret;
1783 1780
1784 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_STU)) { 1781 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) {
1785 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1782 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1786 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg); 1783 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1784 reg);
1787 if (ret < 0) 1785 if (ret < 0)
1788 return ret; 1786 return ret;
1789 } 1787 }
1790 1788
1791 if (mv88e6xxx_has_fid_reg(ps)) { 1789 if (mv88e6xxx_has_fid_reg(chip)) {
1792 reg = entry->fid & GLOBAL_VTU_FID_MASK; 1790 reg = entry->fid & GLOBAL_VTU_FID_MASK;
1793 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_FID, reg); 1791 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_FID,
1792 reg);
1794 if (ret < 0) 1793 if (ret < 0)
1795 return ret; 1794 return ret;
1796 } else if (mv88e6xxx_num_databases(ps) == 256) { 1795 } else if (mv88e6xxx_num_databases(chip) == 256) {
1797 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1796 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and
1798 * VTU DBNum[3:0] are located in VTU Operation 3:0 1797 * VTU DBNum[3:0] are located in VTU Operation 3:0
1799 */ 1798 */
@@ -1804,46 +1803,46 @@ static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_priv_state *ps,
1804 reg = GLOBAL_VTU_VID_VALID; 1803 reg = GLOBAL_VTU_VID_VALID;
1805loadpurge: 1804loadpurge:
1806 reg |= entry->vid & GLOBAL_VTU_VID_MASK; 1805 reg |= entry->vid & GLOBAL_VTU_VID_MASK;
1807 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg); 1806 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1808 if (ret < 0) 1807 if (ret < 0)
1809 return ret; 1808 return ret;
1810 1809
1811 return _mv88e6xxx_vtu_cmd(ps, op); 1810 return _mv88e6xxx_vtu_cmd(chip, op);
1812} 1811}
1813 1812
1814static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid, 1813static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid,
1815 struct mv88e6xxx_vtu_stu_entry *entry) 1814 struct mv88e6xxx_vtu_stu_entry *entry)
1816{ 1815{
1817 struct mv88e6xxx_vtu_stu_entry next = { 0 }; 1816 struct mv88e6xxx_vtu_stu_entry next = { 0 };
1818 int ret; 1817 int ret;
1819 1818
1820 ret = _mv88e6xxx_vtu_wait(ps); 1819 ret = _mv88e6xxx_vtu_wait(chip);
1821 if (ret < 0) 1820 if (ret < 0)
1822 return ret; 1821 return ret;
1823 1822
1824 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, 1823 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID,
1825 sid & GLOBAL_VTU_SID_MASK); 1824 sid & GLOBAL_VTU_SID_MASK);
1826 if (ret < 0) 1825 if (ret < 0)
1827 return ret; 1826 return ret;
1828 1827
1829 ret = _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_GET_NEXT); 1828 ret = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
1830 if (ret < 0) 1829 if (ret < 0)
1831 return ret; 1830 return ret;
1832 1831
1833 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_SID); 1832 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_SID);
1834 if (ret < 0) 1833 if (ret < 0)
1835 return ret; 1834 return ret;
1836 1835
1837 next.sid = ret & GLOBAL_VTU_SID_MASK; 1836 next.sid = ret & GLOBAL_VTU_SID_MASK;
1838 1837
1839 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_VTU_VID); 1838 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_VTU_VID);
1840 if (ret < 0) 1839 if (ret < 0)
1841 return ret; 1840 return ret;
1842 1841
1843 next.valid = !!(ret & GLOBAL_VTU_VID_VALID); 1842 next.valid = !!(ret & GLOBAL_VTU_VID_VALID);
1844 1843
1845 if (next.valid) { 1844 if (next.valid) {
1846 ret = mv88e6xxx_stu_data_read(ps, &next); 1845 ret = mv88e6xxx_stu_data_read(chip, &next);
1847 if (ret < 0) 1846 if (ret < 0)
1848 return ret; 1847 return ret;
1849 } 1848 }
@@ -1852,13 +1851,13 @@ static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_priv_state *ps, u8 sid,
1852 return 0; 1851 return 0;
1853} 1852}
1854 1853
1855static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps, 1854static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip,
1856 struct mv88e6xxx_vtu_stu_entry *entry) 1855 struct mv88e6xxx_vtu_stu_entry *entry)
1857{ 1856{
1858 u16 reg = 0; 1857 u16 reg = 0;
1859 int ret; 1858 int ret;
1860 1859
1861 ret = _mv88e6xxx_vtu_wait(ps); 1860 ret = _mv88e6xxx_vtu_wait(chip);
1862 if (ret < 0) 1861 if (ret < 0)
1863 return ret; 1862 return ret;
1864 1863
@@ -1866,41 +1865,41 @@ static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_priv_state *ps,
1866 goto loadpurge; 1865 goto loadpurge;
1867 1866
1868 /* Write port states */ 1867 /* Write port states */
1869 ret = mv88e6xxx_stu_data_write(ps, entry); 1868 ret = mv88e6xxx_stu_data_write(chip, entry);
1870 if (ret < 0) 1869 if (ret < 0)
1871 return ret; 1870 return ret;
1872 1871
1873 reg = GLOBAL_VTU_VID_VALID; 1872 reg = GLOBAL_VTU_VID_VALID;
1874loadpurge: 1873loadpurge:
1875 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_VID, reg); 1874 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_VID, reg);
1876 if (ret < 0) 1875 if (ret < 0)
1877 return ret; 1876 return ret;
1878 1877
1879 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1878 reg = entry->sid & GLOBAL_VTU_SID_MASK;
1880 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_VTU_SID, reg); 1879 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_VTU_SID, reg);
1881 if (ret < 0) 1880 if (ret < 0)
1882 return ret; 1881 return ret;
1883 1882
1884 return _mv88e6xxx_vtu_cmd(ps, GLOBAL_VTU_OP_STU_LOAD_PURGE); 1883 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
1885} 1884}
1886 1885
1887static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port, 1886static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port,
1888 u16 *new, u16 *old) 1887 u16 *new, u16 *old)
1889{ 1888{
1890 struct dsa_switch *ds = ps->ds; 1889 struct dsa_switch *ds = chip->ds;
1891 u16 upper_mask; 1890 u16 upper_mask;
1892 u16 fid; 1891 u16 fid;
1893 int ret; 1892 int ret;
1894 1893
1895 if (mv88e6xxx_num_databases(ps) == 4096) 1894 if (mv88e6xxx_num_databases(chip) == 4096)
1896 upper_mask = 0xff; 1895 upper_mask = 0xff;
1897 else if (mv88e6xxx_num_databases(ps) == 256) 1896 else if (mv88e6xxx_num_databases(chip) == 256)
1898 upper_mask = 0xf; 1897 upper_mask = 0xf;
1899 else 1898 else
1900 return -EOPNOTSUPP; 1899 return -EOPNOTSUPP;
1901 1900
1902 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */ 1901 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */
1903 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_BASE_VLAN); 1902 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_BASE_VLAN);
1904 if (ret < 0) 1903 if (ret < 0)
1905 return ret; 1904 return ret;
1906 1905
@@ -1910,14 +1909,14 @@ static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1910 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK; 1909 ret &= ~PORT_BASE_VLAN_FID_3_0_MASK;
1911 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK; 1910 ret |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK;
1912 1911
1913 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_BASE_VLAN, 1912 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_BASE_VLAN,
1914 ret); 1913 ret);
1915 if (ret < 0) 1914 if (ret < 0)
1916 return ret; 1915 return ret;
1917 } 1916 }
1918 1917
1919 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */ 1918 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */
1920 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_1); 1919 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_1);
1921 if (ret < 0) 1920 if (ret < 0)
1922 return ret; 1921 return ret;
1923 1922
@@ -1927,7 +1926,7 @@ static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1927 ret &= ~upper_mask; 1926 ret &= ~upper_mask;
1928 ret |= (*new >> 4) & upper_mask; 1927 ret |= (*new >> 4) & upper_mask;
1929 1928
1930 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 1929 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
1931 ret); 1930 ret);
1932 if (ret < 0) 1931 if (ret < 0)
1933 return ret; 1932 return ret;
@@ -1942,19 +1941,19 @@ static int _mv88e6xxx_port_fid(struct mv88e6xxx_priv_state *ps, int port,
1942 return 0; 1941 return 0;
1943} 1942}
1944 1943
1945static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_priv_state *ps, 1944static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip,
1946 int port, u16 *fid) 1945 int port, u16 *fid)
1947{ 1946{
1948 return _mv88e6xxx_port_fid(ps, port, NULL, fid); 1947 return _mv88e6xxx_port_fid(chip, port, NULL, fid);
1949} 1948}
1950 1949
1951static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_priv_state *ps, 1950static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip,
1952 int port, u16 fid) 1951 int port, u16 fid)
1953{ 1952{
1954 return _mv88e6xxx_port_fid(ps, port, &fid, NULL); 1953 return _mv88e6xxx_port_fid(chip, port, &fid, NULL);
1955} 1954}
1956 1955
1957static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid) 1956static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid)
1958{ 1957{
1959 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1958 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1960 struct mv88e6xxx_vtu_stu_entry vlan; 1959 struct mv88e6xxx_vtu_stu_entry vlan;
@@ -1963,8 +1962,8 @@ static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
1963 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1962 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1964 1963
1965 /* Set every FID bit used by the (un)bridged ports */ 1964 /* Set every FID bit used by the (un)bridged ports */
1966 for (i = 0; i < ps->info->num_ports; ++i) { 1965 for (i = 0; i < chip->info->num_ports; ++i) {
1967 err = _mv88e6xxx_port_fid_get(ps, i, fid); 1966 err = _mv88e6xxx_port_fid_get(chip, i, fid);
1968 if (err) 1967 if (err)
1969 return err; 1968 return err;
1970 1969
@@ -1972,12 +1971,12 @@ static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
1972 } 1971 }
1973 1972
1974 /* Set every FID bit used by the VLAN entries */ 1973 /* Set every FID bit used by the VLAN entries */
1975 err = _mv88e6xxx_vtu_vid_write(ps, GLOBAL_VTU_VID_MASK); 1974 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK);
1976 if (err) 1975 if (err)
1977 return err; 1976 return err;
1978 1977
1979 do { 1978 do {
1980 err = _mv88e6xxx_vtu_getnext(ps, &vlan); 1979 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
1981 if (err) 1980 if (err)
1982 return err; 1981 return err;
1983 1982
@@ -1991,35 +1990,35 @@ static int _mv88e6xxx_fid_new(struct mv88e6xxx_priv_state *ps, u16 *fid)
1991 * databases are not needed. Return the next positive available. 1990 * databases are not needed. Return the next positive available.
1992 */ 1991 */
1993 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1992 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1994 if (unlikely(*fid >= mv88e6xxx_num_databases(ps))) 1993 if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1995 return -ENOSPC; 1994 return -ENOSPC;
1996 1995
1997 /* Clear the database */ 1996 /* Clear the database */
1998 return _mv88e6xxx_atu_flush(ps, *fid, true); 1997 return _mv88e6xxx_atu_flush(chip, *fid, true);
1999} 1998}
2000 1999
2001static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid, 2000static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid,
2002 struct mv88e6xxx_vtu_stu_entry *entry) 2001 struct mv88e6xxx_vtu_stu_entry *entry)
2003{ 2002{
2004 struct dsa_switch *ds = ps->ds; 2003 struct dsa_switch *ds = chip->ds;
2005 struct mv88e6xxx_vtu_stu_entry vlan = { 2004 struct mv88e6xxx_vtu_stu_entry vlan = {
2006 .valid = true, 2005 .valid = true,
2007 .vid = vid, 2006 .vid = vid,
2008 }; 2007 };
2009 int i, err; 2008 int i, err;
2010 2009
2011 err = _mv88e6xxx_fid_new(ps, &vlan.fid); 2010 err = _mv88e6xxx_fid_new(chip, &vlan.fid);
2012 if (err) 2011 if (err)
2013 return err; 2012 return err;
2014 2013
2015 /* exclude all ports except the CPU and DSA ports */ 2014 /* exclude all ports except the CPU and DSA ports */
2016 for (i = 0; i < ps->info->num_ports; ++i) 2015 for (i = 0; i < chip->info->num_ports; ++i)
2017 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) 2016 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)
2018 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 2017 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED
2019 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2018 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER;
2020 2019
2021 if (mv88e6xxx_6097_family(ps) || mv88e6xxx_6165_family(ps) || 2020 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) ||
2022 mv88e6xxx_6351_family(ps) || mv88e6xxx_6352_family(ps)) { 2021 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) {
2023 struct mv88e6xxx_vtu_stu_entry vstp; 2022 struct mv88e6xxx_vtu_stu_entry vstp;
2024 2023
2025 /* Adding a VTU entry requires a valid STU entry. As VSTP is not 2024 /* Adding a VTU entry requires a valid STU entry. As VSTP is not
@@ -2027,7 +2026,7 @@ static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
2027 * entries. Thus, validate the SID 0. 2026 * entries. Thus, validate the SID 0.
2028 */ 2027 */
2029 vlan.sid = 0; 2028 vlan.sid = 0;
2030 err = _mv88e6xxx_stu_getnext(ps, GLOBAL_VTU_SID_MASK, &vstp); 2029 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp);
2031 if (err) 2030 if (err)
2032 return err; 2031 return err;
2033 2032
@@ -2036,7 +2035,7 @@ static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
2036 vstp.valid = true; 2035 vstp.valid = true;
2037 vstp.sid = vlan.sid; 2036 vstp.sid = vlan.sid;
2038 2037
2039 err = _mv88e6xxx_stu_loadpurge(ps, &vstp); 2038 err = _mv88e6xxx_stu_loadpurge(chip, &vstp);
2040 if (err) 2039 if (err)
2041 return err; 2040 return err;
2042 } 2041 }
@@ -2046,7 +2045,7 @@ static int _mv88e6xxx_vtu_new(struct mv88e6xxx_priv_state *ps, u16 vid,
2046 return 0; 2045 return 0;
2047} 2046}
2048 2047
2049static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid, 2048static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
2050 struct mv88e6xxx_vtu_stu_entry *entry, bool creat) 2049 struct mv88e6xxx_vtu_stu_entry *entry, bool creat)
2051{ 2050{
2052 int err; 2051 int err;
@@ -2054,11 +2053,11 @@ static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
2054 if (!vid) 2053 if (!vid)
2055 return -EINVAL; 2054 return -EINVAL;
2056 2055
2057 err = _mv88e6xxx_vtu_vid_write(ps, vid - 1); 2056 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1);
2058 if (err) 2057 if (err)
2059 return err; 2058 return err;
2060 2059
2061 err = _mv88e6xxx_vtu_getnext(ps, entry); 2060 err = _mv88e6xxx_vtu_getnext(chip, entry);
2062 if (err) 2061 if (err)
2063 return err; 2062 return err;
2064 2063
@@ -2069,7 +2068,7 @@ static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
2069 * -EOPNOTSUPP to inform bridge about an eventual software VLAN. 2068 * -EOPNOTSUPP to inform bridge about an eventual software VLAN.
2070 */ 2069 */
2071 2070
2072 err = _mv88e6xxx_vtu_new(ps, vid, entry); 2071 err = _mv88e6xxx_vtu_new(chip, vid, entry);
2073 } 2072 }
2074 2073
2075 return err; 2074 return err;
@@ -2078,21 +2077,21 @@ static int _mv88e6xxx_vtu_get(struct mv88e6xxx_priv_state *ps, u16 vid,
2078static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2077static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2079 u16 vid_begin, u16 vid_end) 2078 u16 vid_begin, u16 vid_end)
2080{ 2079{
2081 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2080 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2082 struct mv88e6xxx_vtu_stu_entry vlan; 2081 struct mv88e6xxx_vtu_stu_entry vlan;
2083 int i, err; 2082 int i, err;
2084 2083
2085 if (!vid_begin) 2084 if (!vid_begin)
2086 return -EOPNOTSUPP; 2085 return -EOPNOTSUPP;
2087 2086
2088 mutex_lock(&ps->reg_lock); 2087 mutex_lock(&chip->reg_lock);
2089 2088
2090 err = _mv88e6xxx_vtu_vid_write(ps, vid_begin - 1); 2089 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1);
2091 if (err) 2090 if (err)
2092 goto unlock; 2091 goto unlock;
2093 2092
2094 do { 2093 do {
2095 err = _mv88e6xxx_vtu_getnext(ps, &vlan); 2094 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2096 if (err) 2095 if (err)
2097 goto unlock; 2096 goto unlock;
2098 2097
@@ -2102,7 +2101,7 @@ static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2102 if (vlan.vid > vid_end) 2101 if (vlan.vid > vid_end)
2103 break; 2102 break;
2104 2103
2105 for (i = 0; i < ps->info->num_ports; ++i) { 2104 for (i = 0; i < chip->info->num_ports; ++i) {
2106 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 2105 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
2107 continue; 2106 continue;
2108 2107
@@ -2110,21 +2109,21 @@ static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
2110 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2109 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER)
2111 continue; 2110 continue;
2112 2111
2113 if (ps->ports[i].bridge_dev == 2112 if (chip->ports[i].bridge_dev ==
2114 ps->ports[port].bridge_dev) 2113 chip->ports[port].bridge_dev)
2115 break; /* same bridge, check next VLAN */ 2114 break; /* same bridge, check next VLAN */
2116 2115
2117 netdev_warn(ds->ports[port].netdev, 2116 netdev_warn(ds->ports[port].netdev,
2118 "hardware VLAN %d already used by %s\n", 2117 "hardware VLAN %d already used by %s\n",
2119 vlan.vid, 2118 vlan.vid,
2120 netdev_name(ps->ports[i].bridge_dev)); 2119 netdev_name(chip->ports[i].bridge_dev));
2121 err = -EOPNOTSUPP; 2120 err = -EOPNOTSUPP;
2122 goto unlock; 2121 goto unlock;
2123 } 2122 }
2124 } while (vlan.vid < vid_end); 2123 } while (vlan.vid < vid_end);
2125 2124
2126unlock: 2125unlock:
2127 mutex_unlock(&ps->reg_lock); 2126 mutex_unlock(&chip->reg_lock);
2128 2127
2129 return err; 2128 return err;
2130} 2129}
@@ -2139,17 +2138,17 @@ static const char * const mv88e6xxx_port_8021q_mode_names[] = {
2139static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2138static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2140 bool vlan_filtering) 2139 bool vlan_filtering)
2141{ 2140{
2142 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2141 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2143 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : 2142 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE :
2144 PORT_CONTROL_2_8021Q_DISABLED; 2143 PORT_CONTROL_2_8021Q_DISABLED;
2145 int ret; 2144 int ret;
2146 2145
2147 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) 2146 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2148 return -EOPNOTSUPP; 2147 return -EOPNOTSUPP;
2149 2148
2150 mutex_lock(&ps->reg_lock); 2149 mutex_lock(&chip->reg_lock);
2151 2150
2152 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_CONTROL_2); 2151 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_CONTROL_2);
2153 if (ret < 0) 2152 if (ret < 0)
2154 goto unlock; 2153 goto unlock;
2155 2154
@@ -2159,7 +2158,7 @@ static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2159 ret &= ~PORT_CONTROL_2_8021Q_MASK; 2158 ret &= ~PORT_CONTROL_2_8021Q_MASK;
2160 ret |= new & PORT_CONTROL_2_8021Q_MASK; 2159 ret |= new & PORT_CONTROL_2_8021Q_MASK;
2161 2160
2162 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_2, 2161 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_2,
2163 ret); 2162 ret);
2164 if (ret < 0) 2163 if (ret < 0)
2165 goto unlock; 2164 goto unlock;
@@ -2171,7 +2170,7 @@ static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
2171 2170
2172 ret = 0; 2171 ret = 0;
2173unlock: 2172unlock:
2174 mutex_unlock(&ps->reg_lock); 2173 mutex_unlock(&chip->reg_lock);
2175 2174
2176 return ret; 2175 return ret;
2177} 2176}
@@ -2181,10 +2180,10 @@ mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2181 const struct switchdev_obj_port_vlan *vlan, 2180 const struct switchdev_obj_port_vlan *vlan,
2182 struct switchdev_trans *trans) 2181 struct switchdev_trans *trans)
2183{ 2182{
2184 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2183 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2185 int err; 2184 int err;
2186 2185
2187 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) 2186 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2188 return -EOPNOTSUPP; 2187 return -EOPNOTSUPP;
2189 2188
2190 /* If the requested port doesn't belong to the same bridge as the VLAN 2189 /* If the requested port doesn't belong to the same bridge as the VLAN
@@ -2201,13 +2200,13 @@ mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
2201 return 0; 2200 return 0;
2202} 2201}
2203 2202
2204static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port, 2203static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
2205 u16 vid, bool untagged) 2204 u16 vid, bool untagged)
2206{ 2205{
2207 struct mv88e6xxx_vtu_stu_entry vlan; 2206 struct mv88e6xxx_vtu_stu_entry vlan;
2208 int err; 2207 int err;
2209 2208
2210 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, true); 2209 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true);
2211 if (err) 2210 if (err)
2212 return err; 2211 return err;
2213 2212
@@ -2215,44 +2214,44 @@ static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_priv_state *ps, int port,
2215 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : 2214 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED :
2216 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; 2215 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED;
2217 2216
2218 return _mv88e6xxx_vtu_loadpurge(ps, &vlan); 2217 return _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2219} 2218}
2220 2219
2221static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2220static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
2222 const struct switchdev_obj_port_vlan *vlan, 2221 const struct switchdev_obj_port_vlan *vlan,
2223 struct switchdev_trans *trans) 2222 struct switchdev_trans *trans)
2224{ 2223{
2225 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2224 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2226 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2225 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
2227 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2226 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
2228 u16 vid; 2227 u16 vid;
2229 2228
2230 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) 2229 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2231 return; 2230 return;
2232 2231
2233 mutex_lock(&ps->reg_lock); 2232 mutex_lock(&chip->reg_lock);
2234 2233
2235 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 2234 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
2236 if (_mv88e6xxx_port_vlan_add(ps, port, vid, untagged)) 2235 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged))
2237 netdev_err(ds->ports[port].netdev, 2236 netdev_err(ds->ports[port].netdev,
2238 "failed to add VLAN %d%c\n", 2237 "failed to add VLAN %d%c\n",
2239 vid, untagged ? 'u' : 't'); 2238 vid, untagged ? 'u' : 't');
2240 2239
2241 if (pvid && _mv88e6xxx_port_pvid_set(ps, port, vlan->vid_end)) 2240 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end))
2242 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", 2241 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n",
2243 vlan->vid_end); 2242 vlan->vid_end);
2244 2243
2245 mutex_unlock(&ps->reg_lock); 2244 mutex_unlock(&chip->reg_lock);
2246} 2245}
2247 2246
2248static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps, 2247static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
2249 int port, u16 vid) 2248 int port, u16 vid)
2250{ 2249{
2251 struct dsa_switch *ds = ps->ds; 2250 struct dsa_switch *ds = chip->ds;
2252 struct mv88e6xxx_vtu_stu_entry vlan; 2251 struct mv88e6xxx_vtu_stu_entry vlan;
2253 int i, err; 2252 int i, err;
2254 2253
2255 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false); 2254 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2256 if (err) 2255 if (err)
2257 return err; 2256 return err;
2258 2257
@@ -2264,7 +2263,7 @@ static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2264 2263
2265 /* keep the VLAN unless all ports are excluded */ 2264 /* keep the VLAN unless all ports are excluded */
2266 vlan.valid = false; 2265 vlan.valid = false;
2267 for (i = 0; i < ps->info->num_ports; ++i) { 2266 for (i = 0; i < chip->info->num_ports; ++i) {
2268 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 2267 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i))
2269 continue; 2268 continue;
2270 2269
@@ -2274,55 +2273,55 @@ static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_priv_state *ps,
2274 } 2273 }
2275 } 2274 }
2276 2275
2277 err = _mv88e6xxx_vtu_loadpurge(ps, &vlan); 2276 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan);
2278 if (err) 2277 if (err)
2279 return err; 2278 return err;
2280 2279
2281 return _mv88e6xxx_atu_remove(ps, vlan.fid, port, false); 2280 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false);
2282} 2281}
2283 2282
2284static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2283static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
2285 const struct switchdev_obj_port_vlan *vlan) 2284 const struct switchdev_obj_port_vlan *vlan)
2286{ 2285{
2287 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2286 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2288 u16 pvid, vid; 2287 u16 pvid, vid;
2289 int err = 0; 2288 int err = 0;
2290 2289
2291 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VTU)) 2290 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU))
2292 return -EOPNOTSUPP; 2291 return -EOPNOTSUPP;
2293 2292
2294 mutex_lock(&ps->reg_lock); 2293 mutex_lock(&chip->reg_lock);
2295 2294
2296 err = _mv88e6xxx_port_pvid_get(ps, port, &pvid); 2295 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid);
2297 if (err) 2296 if (err)
2298 goto unlock; 2297 goto unlock;
2299 2298
2300 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2299 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
2301 err = _mv88e6xxx_port_vlan_del(ps, port, vid); 2300 err = _mv88e6xxx_port_vlan_del(chip, port, vid);
2302 if (err) 2301 if (err)
2303 goto unlock; 2302 goto unlock;
2304 2303
2305 if (vid == pvid) { 2304 if (vid == pvid) {
2306 err = _mv88e6xxx_port_pvid_set(ps, port, 0); 2305 err = _mv88e6xxx_port_pvid_set(chip, port, 0);
2307 if (err) 2306 if (err)
2308 goto unlock; 2307 goto unlock;
2309 } 2308 }
2310 } 2309 }
2311 2310
2312unlock: 2311unlock:
2313 mutex_unlock(&ps->reg_lock); 2312 mutex_unlock(&chip->reg_lock);
2314 2313
2315 return err; 2314 return err;
2316} 2315}
2317 2316
2318static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps, 2317static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip,
2319 const unsigned char *addr) 2318 const unsigned char *addr)
2320{ 2319{
2321 int i, ret; 2320 int i, ret;
2322 2321
2323 for (i = 0; i < 3; i++) { 2322 for (i = 0; i < 3; i++) {
2324 ret = _mv88e6xxx_reg_write( 2323 ret = _mv88e6xxx_reg_write(
2325 ps, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i, 2324 chip, REG_GLOBAL, GLOBAL_ATU_MAC_01 + i,
2326 (addr[i * 2] << 8) | addr[i * 2 + 1]); 2325 (addr[i * 2] << 8) | addr[i * 2 + 1]);
2327 if (ret < 0) 2326 if (ret < 0)
2328 return ret; 2327 return ret;
@@ -2331,13 +2330,13 @@ static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_priv_state *ps,
2331 return 0; 2330 return 0;
2332} 2331}
2333 2332
2334static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps, 2333static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip,
2335 unsigned char *addr) 2334 unsigned char *addr)
2336{ 2335{
2337 int i, ret; 2336 int i, ret;
2338 2337
2339 for (i = 0; i < 3; i++) { 2338 for (i = 0; i < 3; i++) {
2340 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 2339 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL,
2341 GLOBAL_ATU_MAC_01 + i); 2340 GLOBAL_ATU_MAC_01 + i);
2342 if (ret < 0) 2341 if (ret < 0)
2343 return ret; 2342 return ret;
@@ -2348,27 +2347,27 @@ static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_priv_state *ps,
2348 return 0; 2347 return 0;
2349} 2348}
2350 2349
2351static int _mv88e6xxx_atu_load(struct mv88e6xxx_priv_state *ps, 2350static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip,
2352 struct mv88e6xxx_atu_entry *entry) 2351 struct mv88e6xxx_atu_entry *entry)
2353{ 2352{
2354 int ret; 2353 int ret;
2355 2354
2356 ret = _mv88e6xxx_atu_wait(ps); 2355 ret = _mv88e6xxx_atu_wait(chip);
2357 if (ret < 0) 2356 if (ret < 0)
2358 return ret; 2357 return ret;
2359 2358
2360 ret = _mv88e6xxx_atu_mac_write(ps, entry->mac); 2359 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac);
2361 if (ret < 0) 2360 if (ret < 0)
2362 return ret; 2361 return ret;
2363 2362
2364 ret = _mv88e6xxx_atu_data_write(ps, entry); 2363 ret = _mv88e6xxx_atu_data_write(chip, entry);
2365 if (ret < 0) 2364 if (ret < 0)
2366 return ret; 2365 return ret;
2367 2366
2368 return _mv88e6xxx_atu_cmd(ps, entry->fid, GLOBAL_ATU_OP_LOAD_DB); 2367 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB);
2369} 2368}
2370 2369
2371static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port, 2370static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_chip *chip, int port,
2372 const unsigned char *addr, u16 vid, 2371 const unsigned char *addr, u16 vid,
2373 u8 state) 2372 u8 state)
2374{ 2373{
@@ -2378,9 +2377,9 @@ static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
2378 2377
2379 /* Null VLAN ID corresponds to the port private database */ 2378 /* Null VLAN ID corresponds to the port private database */
2380 if (vid == 0) 2379 if (vid == 0)
2381 err = _mv88e6xxx_port_fid_get(ps, port, &vlan.fid); 2380 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid);
2382 else 2381 else
2383 err = _mv88e6xxx_vtu_get(ps, vid, &vlan, false); 2382 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false);
2384 if (err) 2383 if (err)
2385 return err; 2384 return err;
2386 2385
@@ -2392,16 +2391,16 @@ static int _mv88e6xxx_port_fdb_load(struct mv88e6xxx_priv_state *ps, int port,
2392 entry.portv_trunkid = BIT(port); 2391 entry.portv_trunkid = BIT(port);
2393 } 2392 }
2394 2393
2395 return _mv88e6xxx_atu_load(ps, &entry); 2394 return _mv88e6xxx_atu_load(chip, &entry);
2396} 2395}
2397 2396
2398static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 2397static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port,
2399 const struct switchdev_obj_port_fdb *fdb, 2398 const struct switchdev_obj_port_fdb *fdb,
2400 struct switchdev_trans *trans) 2399 struct switchdev_trans *trans)
2401{ 2400{
2402 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2401 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2403 2402
2404 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) 2403 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_ATU))
2405 return -EOPNOTSUPP; 2404 return -EOPNOTSUPP;
2406 2405
2407 /* We don't need any dynamic resource from the kernel (yet), 2406 /* We don't need any dynamic resource from the kernel (yet),
@@ -2417,36 +2416,36 @@ static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
2417 int state = is_multicast_ether_addr(fdb->addr) ? 2416 int state = is_multicast_ether_addr(fdb->addr) ?
2418 GLOBAL_ATU_DATA_STATE_MC_STATIC : 2417 GLOBAL_ATU_DATA_STATE_MC_STATIC :
2419 GLOBAL_ATU_DATA_STATE_UC_STATIC; 2418 GLOBAL_ATU_DATA_STATE_UC_STATIC;
2420 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2419 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2421 2420
2422 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) 2421 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_ATU))
2423 return; 2422 return;
2424 2423
2425 mutex_lock(&ps->reg_lock); 2424 mutex_lock(&chip->reg_lock);
2426 if (_mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, state)) 2425 if (_mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid, state))
2427 netdev_err(ds->ports[port].netdev, 2426 netdev_err(ds->ports[port].netdev,
2428 "failed to load MAC address\n"); 2427 "failed to load MAC address\n");
2429 mutex_unlock(&ps->reg_lock); 2428 mutex_unlock(&chip->reg_lock);
2430} 2429}
2431 2430
2432static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2431static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
2433 const struct switchdev_obj_port_fdb *fdb) 2432 const struct switchdev_obj_port_fdb *fdb)
2434{ 2433{
2435 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2434 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2436 int ret; 2435 int ret;
2437 2436
2438 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) 2437 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_ATU))
2439 return -EOPNOTSUPP; 2438 return -EOPNOTSUPP;
2440 2439
2441 mutex_lock(&ps->reg_lock); 2440 mutex_lock(&chip->reg_lock);
2442 ret = _mv88e6xxx_port_fdb_load(ps, port, fdb->addr, fdb->vid, 2441 ret = _mv88e6xxx_port_fdb_load(chip, port, fdb->addr, fdb->vid,
2443 GLOBAL_ATU_DATA_STATE_UNUSED); 2442 GLOBAL_ATU_DATA_STATE_UNUSED);
2444 mutex_unlock(&ps->reg_lock); 2443 mutex_unlock(&chip->reg_lock);
2445 2444
2446 return ret; 2445 return ret;
2447} 2446}
2448 2447
2449static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid, 2448static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
2450 struct mv88e6xxx_atu_entry *entry) 2449 struct mv88e6xxx_atu_entry *entry)
2451{ 2450{
2452 struct mv88e6xxx_atu_entry next = { 0 }; 2451 struct mv88e6xxx_atu_entry next = { 0 };
@@ -2454,19 +2453,19 @@ static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
2454 2453
2455 next.fid = fid; 2454 next.fid = fid;
2456 2455
2457 ret = _mv88e6xxx_atu_wait(ps); 2456 ret = _mv88e6xxx_atu_wait(chip);
2458 if (ret < 0) 2457 if (ret < 0)
2459 return ret; 2458 return ret;
2460 2459
2461 ret = _mv88e6xxx_atu_cmd(ps, fid, GLOBAL_ATU_OP_GET_NEXT_DB); 2460 ret = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB);
2462 if (ret < 0) 2461 if (ret < 0)
2463 return ret; 2462 return ret;
2464 2463
2465 ret = _mv88e6xxx_atu_mac_read(ps, next.mac); 2464 ret = _mv88e6xxx_atu_mac_read(chip, next.mac);
2466 if (ret < 0) 2465 if (ret < 0)
2467 return ret; 2466 return ret;
2468 2467
2469 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, GLOBAL_ATU_DATA); 2468 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, GLOBAL_ATU_DATA);
2470 if (ret < 0) 2469 if (ret < 0)
2471 return ret; 2470 return ret;
2472 2471
@@ -2491,7 +2490,7 @@ static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_priv_state *ps, u16 fid,
2491 return 0; 2490 return 0;
2492} 2491}
2493 2492
2494static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps, 2493static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_chip *chip,
2495 u16 fid, u16 vid, int port, 2494 u16 fid, u16 vid, int port,
2496 struct switchdev_obj_port_fdb *fdb, 2495 struct switchdev_obj_port_fdb *fdb,
2497 int (*cb)(struct switchdev_obj *obj)) 2496 int (*cb)(struct switchdev_obj *obj))
@@ -2501,12 +2500,12 @@ static int _mv88e6xxx_port_fdb_dump_one(struct mv88e6xxx_priv_state *ps,
2501 }; 2500 };
2502 int err; 2501 int err;
2503 2502
2504 err = _mv88e6xxx_atu_mac_write(ps, addr.mac); 2503 err = _mv88e6xxx_atu_mac_write(chip, addr.mac);
2505 if (err) 2504 if (err)
2506 return err; 2505 return err;
2507 2506
2508 do { 2507 do {
2509 err = _mv88e6xxx_atu_getnext(ps, fid, &addr); 2508 err = _mv88e6xxx_atu_getnext(chip, fid, &addr);
2510 if (err) 2509 if (err)
2511 break; 2510 break;
2512 2511
@@ -2536,48 +2535,48 @@ static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
2536 struct switchdev_obj_port_fdb *fdb, 2535 struct switchdev_obj_port_fdb *fdb,
2537 int (*cb)(struct switchdev_obj *obj)) 2536 int (*cb)(struct switchdev_obj *obj))
2538{ 2537{
2539 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2538 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2540 struct mv88e6xxx_vtu_stu_entry vlan = { 2539 struct mv88e6xxx_vtu_stu_entry vlan = {
2541 .vid = GLOBAL_VTU_VID_MASK, /* all ones */ 2540 .vid = GLOBAL_VTU_VID_MASK, /* all ones */
2542 }; 2541 };
2543 u16 fid; 2542 u16 fid;
2544 int err; 2543 int err;
2545 2544
2546 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_ATU)) 2545 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_ATU))
2547 return -EOPNOTSUPP; 2546 return -EOPNOTSUPP;
2548 2547
2549 mutex_lock(&ps->reg_lock); 2548 mutex_lock(&chip->reg_lock);
2550 2549
2551 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2550 /* Dump port's default Filtering Information Database (VLAN ID 0) */
2552 err = _mv88e6xxx_port_fid_get(ps, port, &fid); 2551 err = _mv88e6xxx_port_fid_get(chip, port, &fid);
2553 if (err) 2552 if (err)
2554 goto unlock; 2553 goto unlock;
2555 2554
2556 err = _mv88e6xxx_port_fdb_dump_one(ps, fid, 0, port, fdb, cb); 2555 err = _mv88e6xxx_port_fdb_dump_one(chip, fid, 0, port, fdb, cb);
2557 if (err) 2556 if (err)
2558 goto unlock; 2557 goto unlock;
2559 2558
2560 /* Dump VLANs' Filtering Information Databases */ 2559 /* Dump VLANs' Filtering Information Databases */
2561 err = _mv88e6xxx_vtu_vid_write(ps, vlan.vid); 2560 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid);
2562 if (err) 2561 if (err)
2563 goto unlock; 2562 goto unlock;
2564 2563
2565 do { 2564 do {
2566 err = _mv88e6xxx_vtu_getnext(ps, &vlan); 2565 err = _mv88e6xxx_vtu_getnext(chip, &vlan);
2567 if (err) 2566 if (err)
2568 break; 2567 break;
2569 2568
2570 if (!vlan.valid) 2569 if (!vlan.valid)
2571 break; 2570 break;
2572 2571
2573 err = _mv88e6xxx_port_fdb_dump_one(ps, vlan.fid, vlan.vid, port, 2572 err = _mv88e6xxx_port_fdb_dump_one(chip, vlan.fid, vlan.vid,
2574 fdb, cb); 2573 port, fdb, cb);
2575 if (err) 2574 if (err)
2576 break; 2575 break;
2577 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 2576 } while (vlan.vid < GLOBAL_VTU_VID_MASK);
2578 2577
2579unlock: 2578unlock:
2580 mutex_unlock(&ps->reg_lock); 2579 mutex_unlock(&chip->reg_lock);
2581 2580
2582 return err; 2581 return err;
2583} 2582}
@@ -2585,101 +2584,101 @@ unlock:
2585static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2584static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
2586 struct net_device *bridge) 2585 struct net_device *bridge)
2587{ 2586{
2588 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2587 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2589 int i, err = 0; 2588 int i, err = 0;
2590 2589
2591 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE)) 2590 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VLANTABLE))
2592 return -EOPNOTSUPP; 2591 return -EOPNOTSUPP;
2593 2592
2594 mutex_lock(&ps->reg_lock); 2593 mutex_lock(&chip->reg_lock);
2595 2594
2596 /* Assign the bridge and remap each port's VLANTable */ 2595 /* Assign the bridge and remap each port's VLANTable */
2597 ps->ports[port].bridge_dev = bridge; 2596 chip->ports[port].bridge_dev = bridge;
2598 2597
2599 for (i = 0; i < ps->info->num_ports; ++i) { 2598 for (i = 0; i < chip->info->num_ports; ++i) {
2600 if (ps->ports[i].bridge_dev == bridge) { 2599 if (chip->ports[i].bridge_dev == bridge) {
2601 err = _mv88e6xxx_port_based_vlan_map(ps, i); 2600 err = _mv88e6xxx_port_based_vlan_map(chip, i);
2602 if (err) 2601 if (err)
2603 break; 2602 break;
2604 } 2603 }
2605 } 2604 }
2606 2605
2607 mutex_unlock(&ps->reg_lock); 2606 mutex_unlock(&chip->reg_lock);
2608 2607
2609 return err; 2608 return err;
2610} 2609}
2611 2610
2612static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) 2611static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port)
2613{ 2612{
2614 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 2613 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
2615 struct net_device *bridge = ps->ports[port].bridge_dev; 2614 struct net_device *bridge = chip->ports[port].bridge_dev;
2616 int i; 2615 int i;
2617 2616
2618 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_VLANTABLE)) 2617 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VLANTABLE))
2619 return; 2618 return;
2620 2619
2621 mutex_lock(&ps->reg_lock); 2620 mutex_lock(&chip->reg_lock);
2622 2621
2623 /* Unassign the bridge and remap each port's VLANTable */ 2622 /* Unassign the bridge and remap each port's VLANTable */
2624 ps->ports[port].bridge_dev = NULL; 2623 chip->ports[port].bridge_dev = NULL;
2625 2624
2626 for (i = 0; i < ps->info->num_ports; ++i) 2625 for (i = 0; i < chip->info->num_ports; ++i)
2627 if (i == port || ps->ports[i].bridge_dev == bridge) 2626 if (i == port || chip->ports[i].bridge_dev == bridge)
2628 if (_mv88e6xxx_port_based_vlan_map(ps, i)) 2627 if (_mv88e6xxx_port_based_vlan_map(chip, i))
2629 netdev_warn(ds->ports[i].netdev, 2628 netdev_warn(ds->ports[i].netdev,
2630 "failed to remap\n"); 2629 "failed to remap\n");
2631 2630
2632 mutex_unlock(&ps->reg_lock); 2631 mutex_unlock(&chip->reg_lock);
2633} 2632}
2634 2633
2635static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_priv_state *ps, 2634static int _mv88e6xxx_mdio_page_write(struct mv88e6xxx_chip *chip,
2636 int port, int page, int reg, int val) 2635 int port, int page, int reg, int val)
2637{ 2636{
2638 int ret; 2637 int ret;
2639 2638
2640 ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page); 2639 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2641 if (ret < 0) 2640 if (ret < 0)
2642 goto restore_page_0; 2641 goto restore_page_0;
2643 2642
2644 ret = mv88e6xxx_mdio_write_indirect(ps, port, reg, val); 2643 ret = mv88e6xxx_mdio_write_indirect(chip, port, reg, val);
2645restore_page_0: 2644restore_page_0:
2646 mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0); 2645 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2647 2646
2648 return ret; 2647 return ret;
2649} 2648}
2650 2649
2651static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_priv_state *ps, 2650static int _mv88e6xxx_mdio_page_read(struct mv88e6xxx_chip *chip,
2652 int port, int page, int reg) 2651 int port, int page, int reg)
2653{ 2652{
2654 int ret; 2653 int ret;
2655 2654
2656 ret = mv88e6xxx_mdio_write_indirect(ps, port, 0x16, page); 2655 ret = mv88e6xxx_mdio_write_indirect(chip, port, 0x16, page);
2657 if (ret < 0) 2656 if (ret < 0)
2658 goto restore_page_0; 2657 goto restore_page_0;
2659 2658
2660 ret = mv88e6xxx_mdio_read_indirect(ps, port, reg); 2659 ret = mv88e6xxx_mdio_read_indirect(chip, port, reg);
2661restore_page_0: 2660restore_page_0:
2662 mv88e6xxx_mdio_write_indirect(ps, port, 0x16, 0x0); 2661 mv88e6xxx_mdio_write_indirect(chip, port, 0x16, 0x0);
2663 2662
2664 return ret; 2663 return ret;
2665} 2664}
2666 2665
2667static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps) 2666static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2668{ 2667{
2669 bool ppu_active = mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE); 2668 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE);
2670 u16 is_reset = (ppu_active ? 0x8800 : 0xc800); 2669 u16 is_reset = (ppu_active ? 0x8800 : 0xc800);
2671 struct gpio_desc *gpiod = ps->reset; 2670 struct gpio_desc *gpiod = chip->reset;
2672 unsigned long timeout; 2671 unsigned long timeout;
2673 int ret; 2672 int ret;
2674 int i; 2673 int i;
2675 2674
2676 /* Set all ports to the disabled state. */ 2675 /* Set all ports to the disabled state. */
2677 for (i = 0; i < ps->info->num_ports; i++) { 2676 for (i = 0; i < chip->info->num_ports; i++) {
2678 ret = _mv88e6xxx_reg_read(ps, REG_PORT(i), PORT_CONTROL); 2677 ret = _mv88e6xxx_reg_read(chip, REG_PORT(i), PORT_CONTROL);
2679 if (ret < 0) 2678 if (ret < 0)
2680 return ret; 2679 return ret;
2681 2680
2682 ret = _mv88e6xxx_reg_write(ps, REG_PORT(i), PORT_CONTROL, 2681 ret = _mv88e6xxx_reg_write(chip, REG_PORT(i), PORT_CONTROL,
2683 ret & 0xfffc); 2682 ret & 0xfffc);
2684 if (ret) 2683 if (ret)
2685 return ret; 2684 return ret;
@@ -2701,16 +2700,16 @@ static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps)
2701 * through global registers 0x18 and 0x19. 2700 * through global registers 0x18 and 0x19.
2702 */ 2701 */
2703 if (ppu_active) 2702 if (ppu_active)
2704 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc000); 2703 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc000);
2705 else 2704 else
2706 ret = _mv88e6xxx_reg_write(ps, REG_GLOBAL, 0x04, 0xc400); 2705 ret = _mv88e6xxx_reg_write(chip, REG_GLOBAL, 0x04, 0xc400);
2707 if (ret) 2706 if (ret)
2708 return ret; 2707 return ret;
2709 2708
2710 /* Wait up to one second for reset to complete. */ 2709 /* Wait up to one second for reset to complete. */
2711 timeout = jiffies + 1 * HZ; 2710 timeout = jiffies + 1 * HZ;
2712 while (time_before(jiffies, timeout)) { 2711 while (time_before(jiffies, timeout)) {
2713 ret = _mv88e6xxx_reg_read(ps, REG_GLOBAL, 0x00); 2712 ret = _mv88e6xxx_reg_read(chip, REG_GLOBAL, 0x00);
2714 if (ret < 0) 2713 if (ret < 0)
2715 return ret; 2714 return ret;
2716 2715
@@ -2726,18 +2725,18 @@ static int mv88e6xxx_switch_reset(struct mv88e6xxx_priv_state *ps)
2726 return ret; 2725 return ret;
2727} 2726}
2728 2727
2729static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps) 2728static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_chip *chip)
2730{ 2729{
2731 int ret; 2730 int ret;
2732 2731
2733 ret = _mv88e6xxx_mdio_page_read(ps, REG_FIBER_SERDES, 2732 ret = _mv88e6xxx_mdio_page_read(chip, REG_FIBER_SERDES,
2734 PAGE_FIBER_SERDES, MII_BMCR); 2733 PAGE_FIBER_SERDES, MII_BMCR);
2735 if (ret < 0) 2734 if (ret < 0)
2736 return ret; 2735 return ret;
2737 2736
2738 if (ret & BMCR_PDOWN) { 2737 if (ret & BMCR_PDOWN) {
2739 ret &= ~BMCR_PDOWN; 2738 ret &= ~BMCR_PDOWN;
2740 ret = _mv88e6xxx_mdio_page_write(ps, REG_FIBER_SERDES, 2739 ret = _mv88e6xxx_mdio_page_write(chip, REG_FIBER_SERDES,
2741 PAGE_FIBER_SERDES, MII_BMCR, 2740 PAGE_FIBER_SERDES, MII_BMCR,
2742 ret); 2741 ret);
2743 } 2742 }
@@ -2745,30 +2744,30 @@ static int mv88e6xxx_power_on_serdes(struct mv88e6xxx_priv_state *ps)
2745 return ret; 2744 return ret;
2746} 2745}
2747 2746
2748static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port) 2747static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2749{ 2748{
2750 struct dsa_switch *ds = ps->ds; 2749 struct dsa_switch *ds = chip->ds;
2751 int ret; 2750 int ret;
2752 u16 reg; 2751 u16 reg;
2753 2752
2754 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2753 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2755 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2754 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2756 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || 2755 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2757 mv88e6xxx_6065_family(ps) || mv88e6xxx_6320_family(ps)) { 2756 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) {
2758 /* MAC Forcing register: don't force link, speed, 2757 /* MAC Forcing register: don't force link, speed,
2759 * duplex or flow control state to any particular 2758 * duplex or flow control state to any particular
2760 * values on physical ports, but force the CPU port 2759 * values on physical ports, but force the CPU port
2761 * and all DSA ports to their maximum bandwidth and 2760 * and all DSA ports to their maximum bandwidth and
2762 * full duplex. 2761 * full duplex.
2763 */ 2762 */
2764 reg = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_PCS_CTRL); 2763 reg = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_PCS_CTRL);
2765 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 2764 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) {
2766 reg &= ~PORT_PCS_CTRL_UNFORCED; 2765 reg &= ~PORT_PCS_CTRL_UNFORCED;
2767 reg |= PORT_PCS_CTRL_FORCE_LINK | 2766 reg |= PORT_PCS_CTRL_FORCE_LINK |
2768 PORT_PCS_CTRL_LINK_UP | 2767 PORT_PCS_CTRL_LINK_UP |
2769 PORT_PCS_CTRL_DUPLEX_FULL | 2768 PORT_PCS_CTRL_DUPLEX_FULL |
2770 PORT_PCS_CTRL_FORCE_DUPLEX; 2769 PORT_PCS_CTRL_FORCE_DUPLEX;
2771 if (mv88e6xxx_6065_family(ps)) 2770 if (mv88e6xxx_6065_family(chip))
2772 reg |= PORT_PCS_CTRL_100; 2771 reg |= PORT_PCS_CTRL_100;
2773 else 2772 else
2774 reg |= PORT_PCS_CTRL_1000; 2773 reg |= PORT_PCS_CTRL_1000;
@@ -2776,7 +2775,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2776 reg |= PORT_PCS_CTRL_UNFORCED; 2775 reg |= PORT_PCS_CTRL_UNFORCED;
2777 } 2776 }
2778 2777
2779 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2778 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2780 PORT_PCS_CTRL, reg); 2779 PORT_PCS_CTRL, reg);
2781 if (ret) 2780 if (ret)
2782 return ret; 2781 return ret;
@@ -2797,37 +2796,46 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2797 * forwarding of unknown unicasts and multicasts. 2796 * forwarding of unknown unicasts and multicasts.
2798 */ 2797 */
2799 reg = 0; 2798 reg = 0;
2800 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2799 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2801 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2800 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2802 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) || 2801 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) ||
2803 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) 2802 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip))
2804 reg = PORT_CONTROL_IGMP_MLD_SNOOP | 2803 reg = PORT_CONTROL_IGMP_MLD_SNOOP |
2805 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | 2804 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP |
2806 PORT_CONTROL_STATE_FORWARDING; 2805 PORT_CONTROL_STATE_FORWARDING;
2807 if (dsa_is_cpu_port(ds, port)) { 2806 if (dsa_is_cpu_port(ds, port)) {
2808 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) 2807 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip))
2809 reg |= PORT_CONTROL_DSA_TAG; 2808 reg |= PORT_CONTROL_DSA_TAG;
2810 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2809 if (mv88e6xxx_6352_family(chip) ||
2811 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2810 mv88e6xxx_6351_family(chip) ||
2812 mv88e6xxx_6320_family(ps)) { 2811 mv88e6xxx_6165_family(chip) ||
2812 mv88e6xxx_6097_family(chip) ||
2813 mv88e6xxx_6320_family(chip)) {
2813 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | 2814 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA |
2814 PORT_CONTROL_FORWARD_UNKNOWN | 2815 PORT_CONTROL_FORWARD_UNKNOWN |
2815 PORT_CONTROL_FORWARD_UNKNOWN_MC; 2816 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2816 } 2817 }
2817 2818
2818 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2819 if (mv88e6xxx_6352_family(chip) ||
2819 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2820 mv88e6xxx_6351_family(chip) ||
2820 mv88e6xxx_6095_family(ps) || mv88e6xxx_6065_family(ps) || 2821 mv88e6xxx_6165_family(chip) ||
2821 mv88e6xxx_6185_family(ps) || mv88e6xxx_6320_family(ps)) { 2822 mv88e6xxx_6097_family(chip) ||
2823 mv88e6xxx_6095_family(chip) ||
2824 mv88e6xxx_6065_family(chip) ||
2825 mv88e6xxx_6185_family(chip) ||
2826 mv88e6xxx_6320_family(chip)) {
2822 reg |= PORT_CONTROL_EGRESS_ADD_TAG; 2827 reg |= PORT_CONTROL_EGRESS_ADD_TAG;
2823 } 2828 }
2824 } 2829 }
2825 if (dsa_is_dsa_port(ds, port)) { 2830 if (dsa_is_dsa_port(ds, port)) {
2826 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) 2831 if (mv88e6xxx_6095_family(chip) ||
2832 mv88e6xxx_6185_family(chip))
2827 reg |= PORT_CONTROL_DSA_TAG; 2833 reg |= PORT_CONTROL_DSA_TAG;
2828 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2834 if (mv88e6xxx_6352_family(chip) ||
2829 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2835 mv88e6xxx_6351_family(chip) ||
2830 mv88e6xxx_6320_family(ps)) { 2836 mv88e6xxx_6165_family(chip) ||
2837 mv88e6xxx_6097_family(chip) ||
2838 mv88e6xxx_6320_family(chip)) {
2831 reg |= PORT_CONTROL_FRAME_MODE_DSA; 2839 reg |= PORT_CONTROL_FRAME_MODE_DSA;
2832 } 2840 }
2833 2841
@@ -2836,7 +2844,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2836 PORT_CONTROL_FORWARD_UNKNOWN_MC; 2844 PORT_CONTROL_FORWARD_UNKNOWN_MC;
2837 } 2845 }
2838 if (reg) { 2846 if (reg) {
2839 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2847 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2840 PORT_CONTROL, reg); 2848 PORT_CONTROL, reg);
2841 if (ret) 2849 if (ret)
2842 return ret; 2850 return ret;
@@ -2845,15 +2853,15 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2845 /* If this port is connected to a SerDes, make sure the SerDes is not 2853 /* If this port is connected to a SerDes, make sure the SerDes is not
2846 * powered down. 2854 * powered down.
2847 */ 2855 */
2848 if (mv88e6xxx_6352_family(ps)) { 2856 if (mv88e6xxx_6352_family(chip)) {
2849 ret = _mv88e6xxx_reg_read(ps, REG_PORT(port), PORT_STATUS); 2857 ret = _mv88e6xxx_reg_read(chip, REG_PORT(port), PORT_STATUS);
2850 if (ret < 0) 2858 if (ret < 0)
2851 return ret; 2859 return ret;
2852 ret &= PORT_STATUS_CMODE_MASK; 2860 ret &= PORT_STATUS_CMODE_MASK;
2853 if ((ret == PORT_STATUS_CMODE_100BASE_X) || 2861 if ((ret == PORT_STATUS_CMODE_100BASE_X) ||
2854 (ret == PORT_STATUS_CMODE_1000BASE_X) || 2862 (ret == PORT_STATUS_CMODE_1000BASE_X) ||
2855 (ret == PORT_STATUS_CMODE_SGMII)) { 2863 (ret == PORT_STATUS_CMODE_SGMII)) {
2856 ret = mv88e6xxx_power_on_serdes(ps); 2864 ret = mv88e6xxx_power_on_serdes(chip);
2857 if (ret < 0) 2865 if (ret < 0)
2858 return ret; 2866 return ret;
2859 } 2867 }
@@ -2866,17 +2874,17 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2866 * copy of all transmitted/received frames on this port to the CPU. 2874 * copy of all transmitted/received frames on this port to the CPU.
2867 */ 2875 */
2868 reg = 0; 2876 reg = 0;
2869 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2877 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2870 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2878 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2871 mv88e6xxx_6095_family(ps) || mv88e6xxx_6320_family(ps) || 2879 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) ||
2872 mv88e6xxx_6185_family(ps)) 2880 mv88e6xxx_6185_family(chip))
2873 reg = PORT_CONTROL_2_MAP_DA; 2881 reg = PORT_CONTROL_2_MAP_DA;
2874 2882
2875 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2883 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2876 mv88e6xxx_6165_family(ps) || mv88e6xxx_6320_family(ps)) 2884 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip))
2877 reg |= PORT_CONTROL_2_JUMBO_10240; 2885 reg |= PORT_CONTROL_2_JUMBO_10240;
2878 2886
2879 if (mv88e6xxx_6095_family(ps) || mv88e6xxx_6185_family(ps)) { 2887 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) {
2880 /* Set the upstream port this port should use */ 2888 /* Set the upstream port this port should use */
2881 reg |= dsa_upstream_port(ds); 2889 reg |= dsa_upstream_port(ds);
2882 /* enable forwarding of unknown multicast addresses to 2890 /* enable forwarding of unknown multicast addresses to
@@ -2889,7 +2897,7 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2889 reg |= PORT_CONTROL_2_8021Q_DISABLED; 2897 reg |= PORT_CONTROL_2_8021Q_DISABLED;
2890 2898
2891 if (reg) { 2899 if (reg) {
2892 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2900 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2893 PORT_CONTROL_2, reg); 2901 PORT_CONTROL_2, reg);
2894 if (ret) 2902 if (ret)
2895 return ret; 2903 return ret;
@@ -2905,24 +2913,25 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2905 if (dsa_is_cpu_port(ds, port)) 2913 if (dsa_is_cpu_port(ds, port))
2906 reg = 0; 2914 reg = 0;
2907 2915
2908 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_ASSOC_VECTOR, reg); 2916 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_ASSOC_VECTOR,
2917 reg);
2909 if (ret) 2918 if (ret)
2910 return ret; 2919 return ret;
2911 2920
2912 /* Egress rate control 2: disable egress rate control. */ 2921 /* Egress rate control 2: disable egress rate control. */
2913 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_RATE_CONTROL_2, 2922 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_RATE_CONTROL_2,
2914 0x0000); 2923 0x0000);
2915 if (ret) 2924 if (ret)
2916 return ret; 2925 return ret;
2917 2926
2918 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2927 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2919 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2928 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2920 mv88e6xxx_6320_family(ps)) { 2929 mv88e6xxx_6320_family(chip)) {
2921 /* Do not limit the period of time that this port can 2930 /* Do not limit the period of time that this port can
2922 * be paused for by the remote end or the period of 2931 * be paused for by the remote end or the period of
2923 * time that this port can pause the remote end. 2932 * time that this port can pause the remote end.
2924 */ 2933 */
2925 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2934 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2926 PORT_PAUSE_CTRL, 0x0000); 2935 PORT_PAUSE_CTRL, 0x0000);
2927 if (ret) 2936 if (ret)
2928 return ret; 2937 return ret;
@@ -2931,12 +2940,12 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2931 * address database entries that this port is allowed 2940 * address database entries that this port is allowed
2932 * to use. 2941 * to use.
2933 */ 2942 */
2934 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2943 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2935 PORT_ATU_CONTROL, 0x0000); 2944 PORT_ATU_CONTROL, 0x0000);
2936 /* Priority Override: disable DA, SA and VTU priority 2945 /* Priority Override: disable DA, SA and VTU priority
2937 * override. 2946 * override.
2938 */ 2947 */
2939 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2948 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2940 PORT_PRI_OVERRIDE, 0x0000); 2949 PORT_PRI_OVERRIDE, 0x0000);
2941 if (ret) 2950 if (ret)
2942 return ret; 2951 return ret;
@@ -2944,14 +2953,14 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2944 /* Port Ethertype: use the Ethertype DSA Ethertype 2953 /* Port Ethertype: use the Ethertype DSA Ethertype
2945 * value. 2954 * value.
2946 */ 2955 */
2947 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2956 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2948 PORT_ETH_TYPE, ETH_P_EDSA); 2957 PORT_ETH_TYPE, ETH_P_EDSA);
2949 if (ret) 2958 if (ret)
2950 return ret; 2959 return ret;
2951 /* Tag Remap: use an identity 802.1p prio -> switch 2960 /* Tag Remap: use an identity 802.1p prio -> switch
2952 * prio mapping. 2961 * prio mapping.
2953 */ 2962 */
2954 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2963 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2955 PORT_TAG_REGMAP_0123, 0x3210); 2964 PORT_TAG_REGMAP_0123, 0x3210);
2956 if (ret) 2965 if (ret)
2957 return ret; 2966 return ret;
@@ -2959,18 +2968,18 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2959 /* Tag Remap 2: use an identity 802.1p prio -> switch 2968 /* Tag Remap 2: use an identity 802.1p prio -> switch
2960 * prio mapping. 2969 * prio mapping.
2961 */ 2970 */
2962 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2971 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2963 PORT_TAG_REGMAP_4567, 0x7654); 2972 PORT_TAG_REGMAP_4567, 0x7654);
2964 if (ret) 2973 if (ret)
2965 return ret; 2974 return ret;
2966 } 2975 }
2967 2976
2968 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 2977 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
2969 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 2978 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
2970 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || 2979 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
2971 mv88e6xxx_6320_family(ps)) { 2980 mv88e6xxx_6320_family(chip)) {
2972 /* Rate Control: disable ingress rate limiting. */ 2981 /* Rate Control: disable ingress rate limiting. */
2973 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), 2982 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port),
2974 PORT_RATE_CONTROL, 0x0001); 2983 PORT_RATE_CONTROL, 0x0001);
2975 if (ret) 2984 if (ret)
2976 return ret; 2985 return ret;
@@ -2979,7 +2988,8 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2979 /* Port Control 1: disable trunking, disable sending 2988 /* Port Control 1: disable trunking, disable sending
2980 * learning messages to this port. 2989 * learning messages to this port.
2981 */ 2990 */
2982 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_CONTROL_1, 0x0000); 2991 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_CONTROL_1,
2992 0x0000);
2983 if (ret) 2993 if (ret)
2984 return ret; 2994 return ret;
2985 2995
@@ -2987,18 +2997,18 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
2987 * database, and allow bidirectional communication between the 2997 * database, and allow bidirectional communication between the
2988 * CPU and DSA port(s), and the other ports. 2998 * CPU and DSA port(s), and the other ports.
2989 */ 2999 */
2990 ret = _mv88e6xxx_port_fid_set(ps, port, 0); 3000 ret = _mv88e6xxx_port_fid_set(chip, port, 0);
2991 if (ret) 3001 if (ret)
2992 return ret; 3002 return ret;
2993 3003
2994 ret = _mv88e6xxx_port_based_vlan_map(ps, port); 3004 ret = _mv88e6xxx_port_based_vlan_map(chip, port);
2995 if (ret) 3005 if (ret)
2996 return ret; 3006 return ret;
2997 3007
2998 /* Default VLAN ID and priority: don't set a default VLAN 3008 /* Default VLAN ID and priority: don't set a default VLAN
2999 * ID, and set the default packet priority to zero. 3009 * ID, and set the default packet priority to zero.
3000 */ 3010 */
3001 ret = _mv88e6xxx_reg_write(ps, REG_PORT(port), PORT_DEFAULT_VLAN, 3011 ret = _mv88e6xxx_reg_write(chip, REG_PORT(port), PORT_DEFAULT_VLAN,
3002 0x0000); 3012 0x0000);
3003 if (ret) 3013 if (ret)
3004 return ret; 3014 return ret;
@@ -3006,9 +3016,9 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_priv_state *ps, int port)
3006 return 0; 3016 return 0;
3007} 3017}
3008 3018
3009static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps) 3019static int mv88e6xxx_setup_global(struct mv88e6xxx_chip *chip)
3010{ 3020{
3011 struct dsa_switch *ds = ps->ds; 3021 struct dsa_switch *ds = chip->ds;
3012 u32 upstream_port = dsa_upstream_port(ds); 3022 u32 upstream_port = dsa_upstream_port(ds);
3013 u16 reg; 3023 u16 reg;
3014 int err; 3024 int err;
@@ -3018,11 +3028,11 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3018 * and mask all interrupt sources. 3028 * and mask all interrupt sources.
3019 */ 3029 */
3020 reg = 0; 3030 reg = 0;
3021 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU) || 3031 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) ||
3022 mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU_ACTIVE)) 3032 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE))
3023 reg |= GLOBAL_CONTROL_PPU_ENABLE; 3033 reg |= GLOBAL_CONTROL_PPU_ENABLE;
3024 3034
3025 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL, reg); 3035 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL, reg);
3026 if (err) 3036 if (err)
3027 return err; 3037 return err;
3028 3038
@@ -3032,12 +3042,13 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3032 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | 3042 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT |
3033 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | 3043 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT |
3034 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; 3044 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT;
3035 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_MONITOR_CONTROL, reg); 3045 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_MONITOR_CONTROL,
3046 reg);
3036 if (err) 3047 if (err)
3037 return err; 3048 return err;
3038 3049
3039 /* Disable remote management, and set the switch's DSA device number. */ 3050 /* Disable remote management, and set the switch's DSA device number. */
3040 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_CONTROL_2, 3051 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_CONTROL_2,
3041 GLOBAL_CONTROL_2_MULTIPLE_CASCADE | 3052 GLOBAL_CONTROL_2_MULTIPLE_CASCADE |
3042 (ds->index & 0x1f)); 3053 (ds->index & 0x1f));
3043 if (err) 3054 if (err)
@@ -3047,46 +3058,47 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3047 * enable address learn messages to be sent to all message 3058 * enable address learn messages to be sent to all message
3048 * ports. 3059 * ports.
3049 */ 3060 */
3050 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_ATU_CONTROL, 3061 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_ATU_CONTROL,
3051 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL); 3062 0x0140 | GLOBAL_ATU_CONTROL_LEARN2ALL);
3052 if (err) 3063 if (err)
3053 return err; 3064 return err;
3054 3065
3055 /* Configure the IP ToS mapping registers. */ 3066 /* Configure the IP ToS mapping registers. */
3056 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000); 3067 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_0, 0x0000);
3057 if (err) 3068 if (err)
3058 return err; 3069 return err;
3059 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000); 3070 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_1, 0x0000);
3060 if (err) 3071 if (err)
3061 return err; 3072 return err;
3062 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555); 3073 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_2, 0x5555);
3063 if (err) 3074 if (err)
3064 return err; 3075 return err;
3065 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555); 3076 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_3, 0x5555);
3066 if (err) 3077 if (err)
3067 return err; 3078 return err;
3068 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa); 3079 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_4, 0xaaaa);
3069 if (err) 3080 if (err)
3070 return err; 3081 return err;
3071 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa); 3082 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_5, 0xaaaa);
3072 if (err) 3083 if (err)
3073 return err; 3084 return err;
3074 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff); 3085 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_6, 0xffff);
3075 if (err) 3086 if (err)
3076 return err; 3087 return err;
3077 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff); 3088 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IP_PRI_7, 0xffff);
3078 if (err) 3089 if (err)
3079 return err; 3090 return err;
3080 3091
3081 /* Configure the IEEE 802.1p priority mapping register. */ 3092 /* Configure the IEEE 802.1p priority mapping register. */
3082 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41); 3093 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_IEEE_PRI, 0xfa41);
3083 if (err) 3094 if (err)
3084 return err; 3095 return err;
3085 3096
3086 /* Send all frames with destination addresses matching 3097 /* Send all frames with destination addresses matching
3087 * 01:80:c2:00:00:0x to the CPU port. 3098 * 01:80:c2:00:00:0x to the CPU port.
3088 */ 3099 */
3089 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X, 0xffff); 3100 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_MGMT_EN_0X,
3101 0xffff);
3090 if (err) 3102 if (err)
3091 return err; 3103 return err;
3092 3104
@@ -3095,7 +3107,7 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3095 * highest, and send all special multicast frames to the CPU 3107 * highest, and send all special multicast frames to the CPU
3096 * port at the highest priority. 3108 * port at the highest priority.
3097 */ 3109 */
3098 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT, 3110 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2, GLOBAL2_SWITCH_MGMT,
3099 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 | 3111 0x7 | GLOBAL2_SWITCH_MGMT_RSVD2CPU | 0x70 |
3100 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI); 3112 GLOBAL2_SWITCH_MGMT_FORCE_FLOW_CTRL_PRI);
3101 if (err) 3113 if (err)
@@ -3109,7 +3121,7 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3109 nexthop = ds->rtable[i] & 0x1f; 3121 nexthop = ds->rtable[i] & 0x1f;
3110 3122
3111 err = _mv88e6xxx_reg_write( 3123 err = _mv88e6xxx_reg_write(
3112 ps, REG_GLOBAL2, 3124 chip, REG_GLOBAL2,
3113 GLOBAL2_DEVICE_MAPPING, 3125 GLOBAL2_DEVICE_MAPPING,
3114 GLOBAL2_DEVICE_MAPPING_UPDATE | 3126 GLOBAL2_DEVICE_MAPPING_UPDATE |
3115 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop); 3127 (i << GLOBAL2_DEVICE_MAPPING_TARGET_SHIFT) | nexthop);
@@ -3119,10 +3131,11 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3119 3131
3120 /* Clear all trunk masks. */ 3132 /* Clear all trunk masks. */
3121 for (i = 0; i < 8; i++) { 3133 for (i = 0; i < 8; i++) {
3122 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, GLOBAL2_TRUNK_MASK, 3134 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3135 GLOBAL2_TRUNK_MASK,
3123 0x8000 | 3136 0x8000 |
3124 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) | 3137 (i << GLOBAL2_TRUNK_MASK_NUM_SHIFT) |
3125 ((1 << ps->info->num_ports) - 1)); 3138 ((1 << chip->info->num_ports) - 1));
3126 if (err) 3139 if (err)
3127 return err; 3140 return err;
3128 } 3141 }
@@ -3130,7 +3143,7 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3130 /* Clear all trunk mappings. */ 3143 /* Clear all trunk mappings. */
3131 for (i = 0; i < 16; i++) { 3144 for (i = 0; i < 16; i++) {
3132 err = _mv88e6xxx_reg_write( 3145 err = _mv88e6xxx_reg_write(
3133 ps, REG_GLOBAL2, 3146 chip, REG_GLOBAL2,
3134 GLOBAL2_TRUNK_MAPPING, 3147 GLOBAL2_TRUNK_MAPPING,
3135 GLOBAL2_TRUNK_MAPPING_UPDATE | 3148 GLOBAL2_TRUNK_MAPPING_UPDATE |
3136 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT)); 3149 (i << GLOBAL2_TRUNK_MAPPING_ID_SHIFT));
@@ -3138,13 +3151,13 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3138 return err; 3151 return err;
3139 } 3152 }
3140 3153
3141 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 3154 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
3142 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 3155 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
3143 mv88e6xxx_6320_family(ps)) { 3156 mv88e6xxx_6320_family(chip)) {
3144 /* Send all frames with destination addresses matching 3157 /* Send all frames with destination addresses matching
3145 * 01:80:c2:00:00:2x to the CPU port. 3158 * 01:80:c2:00:00:2x to the CPU port.
3146 */ 3159 */
3147 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, 3160 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3148 GLOBAL2_MGMT_EN_2X, 0xffff); 3161 GLOBAL2_MGMT_EN_2X, 0xffff);
3149 if (err) 3162 if (err)
3150 return err; 3163 return err;
@@ -3152,14 +3165,14 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3152 /* Initialise cross-chip port VLAN table to reset 3165 /* Initialise cross-chip port VLAN table to reset
3153 * defaults. 3166 * defaults.
3154 */ 3167 */
3155 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, 3168 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3156 GLOBAL2_PVT_ADDR, 0x9000); 3169 GLOBAL2_PVT_ADDR, 0x9000);
3157 if (err) 3170 if (err)
3158 return err; 3171 return err;
3159 3172
3160 /* Clear the priority override table. */ 3173 /* Clear the priority override table. */
3161 for (i = 0; i < 16; i++) { 3174 for (i = 0; i < 16; i++) {
3162 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, 3175 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3163 GLOBAL2_PRIO_OVERRIDE, 3176 GLOBAL2_PRIO_OVERRIDE,
3164 0x8000 | (i << 8)); 3177 0x8000 | (i << 8));
3165 if (err) 3178 if (err)
@@ -3167,16 +3180,16 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3167 } 3180 }
3168 } 3181 }
3169 3182
3170 if (mv88e6xxx_6352_family(ps) || mv88e6xxx_6351_family(ps) || 3183 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) ||
3171 mv88e6xxx_6165_family(ps) || mv88e6xxx_6097_family(ps) || 3184 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) ||
3172 mv88e6xxx_6185_family(ps) || mv88e6xxx_6095_family(ps) || 3185 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) ||
3173 mv88e6xxx_6320_family(ps)) { 3186 mv88e6xxx_6320_family(chip)) {
3174 /* Disable ingress rate limiting by resetting all 3187 /* Disable ingress rate limiting by resetting all
3175 * ingress rate limit registers to their initial 3188 * ingress rate limit registers to their initial
3176 * state. 3189 * state.
3177 */ 3190 */
3178 for (i = 0; i < ps->info->num_ports; i++) { 3191 for (i = 0; i < chip->info->num_ports; i++) {
3179 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL2, 3192 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL2,
3180 GLOBAL2_INGRESS_OP, 3193 GLOBAL2_INGRESS_OP,
3181 0x9000 | (i << 8)); 3194 0x9000 | (i << 8));
3182 if (err) 3195 if (err)
@@ -3185,23 +3198,23 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3185 } 3198 }
3186 3199
3187 /* Clear the statistics counters for all ports */ 3200 /* Clear the statistics counters for all ports */
3188 err = _mv88e6xxx_reg_write(ps, REG_GLOBAL, GLOBAL_STATS_OP, 3201 err = _mv88e6xxx_reg_write(chip, REG_GLOBAL, GLOBAL_STATS_OP,
3189 GLOBAL_STATS_OP_FLUSH_ALL); 3202 GLOBAL_STATS_OP_FLUSH_ALL);
3190 if (err) 3203 if (err)
3191 return err; 3204 return err;
3192 3205
3193 /* Wait for the flush to complete. */ 3206 /* Wait for the flush to complete. */
3194 err = _mv88e6xxx_stats_wait(ps); 3207 err = _mv88e6xxx_stats_wait(chip);
3195 if (err) 3208 if (err)
3196 return err; 3209 return err;
3197 3210
3198 /* Clear all ATU entries */ 3211 /* Clear all ATU entries */
3199 err = _mv88e6xxx_atu_flush(ps, 0, true); 3212 err = _mv88e6xxx_atu_flush(chip, 0, true);
3200 if (err) 3213 if (err)
3201 return err; 3214 return err;
3202 3215
3203 /* Clear all the VTU and STU entries */ 3216 /* Clear all the VTU and STU entries */
3204 err = _mv88e6xxx_vtu_stu_flush(ps); 3217 err = _mv88e6xxx_vtu_stu_flush(chip);
3205 if (err < 0) 3218 if (err < 0)
3206 return err; 3219 return err;
3207 3220
@@ -3210,34 +3223,34 @@ static int mv88e6xxx_setup_global(struct mv88e6xxx_priv_state *ps)
3210 3223
3211static int mv88e6xxx_setup(struct dsa_switch *ds) 3224static int mv88e6xxx_setup(struct dsa_switch *ds)
3212{ 3225{
3213 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3226 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3214 int err; 3227 int err;
3215 int i; 3228 int i;
3216 3229
3217 ps->ds = ds; 3230 chip->ds = ds;
3218 ds->slave_mii_bus = ps->mdio_bus; 3231 ds->slave_mii_bus = chip->mdio_bus;
3219 3232
3220 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM)) 3233 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM))
3221 mutex_init(&ps->eeprom_mutex); 3234 mutex_init(&chip->eeprom_mutex);
3222 3235
3223 mutex_lock(&ps->reg_lock); 3236 mutex_lock(&chip->reg_lock);
3224 3237
3225 err = mv88e6xxx_switch_reset(ps); 3238 err = mv88e6xxx_switch_reset(chip);
3226 if (err) 3239 if (err)
3227 goto unlock; 3240 goto unlock;
3228 3241
3229 err = mv88e6xxx_setup_global(ps); 3242 err = mv88e6xxx_setup_global(chip);
3230 if (err) 3243 if (err)
3231 goto unlock; 3244 goto unlock;
3232 3245
3233 for (i = 0; i < ps->info->num_ports; i++) { 3246 for (i = 0; i < chip->info->num_ports; i++) {
3234 err = mv88e6xxx_setup_port(ps, i); 3247 err = mv88e6xxx_setup_port(chip, i);
3235 if (err) 3248 if (err)
3236 goto unlock; 3249 goto unlock;
3237 } 3250 }
3238 3251
3239unlock: 3252unlock:
3240 mutex_unlock(&ps->reg_lock); 3253 mutex_unlock(&chip->reg_lock);
3241 3254
3242 return err; 3255 return err;
3243} 3256}
@@ -3245,12 +3258,12 @@ unlock:
3245static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page, 3258static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3246 int reg) 3259 int reg)
3247{ 3260{
3248 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3261 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3249 int ret; 3262 int ret;
3250 3263
3251 mutex_lock(&ps->reg_lock); 3264 mutex_lock(&chip->reg_lock);
3252 ret = _mv88e6xxx_mdio_page_read(ps, port, page, reg); 3265 ret = _mv88e6xxx_mdio_page_read(chip, port, page, reg);
3253 mutex_unlock(&ps->reg_lock); 3266 mutex_unlock(&chip->reg_lock);
3254 3267
3255 return ret; 3268 return ret;
3256} 3269}
@@ -3258,87 +3271,86 @@ static int mv88e6xxx_mdio_page_read(struct dsa_switch *ds, int port, int page,
3258static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page, 3271static int mv88e6xxx_mdio_page_write(struct dsa_switch *ds, int port, int page,
3259 int reg, int val) 3272 int reg, int val)
3260{ 3273{
3261 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3274 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3262 int ret; 3275 int ret;
3263 3276
3264 mutex_lock(&ps->reg_lock); 3277 mutex_lock(&chip->reg_lock);
3265 ret = _mv88e6xxx_mdio_page_write(ps, port, page, reg, val); 3278 ret = _mv88e6xxx_mdio_page_write(chip, port, page, reg, val);
3266 mutex_unlock(&ps->reg_lock); 3279 mutex_unlock(&chip->reg_lock);
3267 3280
3268 return ret; 3281 return ret;
3269} 3282}
3270 3283
3271static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_priv_state *ps, 3284static int mv88e6xxx_port_to_mdio_addr(struct mv88e6xxx_chip *chip, int port)
3272 int port)
3273{ 3285{
3274 if (port >= 0 && port < ps->info->num_ports) 3286 if (port >= 0 && port < chip->info->num_ports)
3275 return port; 3287 return port;
3276 return -EINVAL; 3288 return -EINVAL;
3277} 3289}
3278 3290
3279static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum) 3291static int mv88e6xxx_mdio_read(struct mii_bus *bus, int port, int regnum)
3280{ 3292{
3281 struct mv88e6xxx_priv_state *ps = bus->priv; 3293 struct mv88e6xxx_chip *chip = bus->priv;
3282 int addr = mv88e6xxx_port_to_mdio_addr(ps, port); 3294 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3283 int ret; 3295 int ret;
3284 3296
3285 if (addr < 0) 3297 if (addr < 0)
3286 return 0xffff; 3298 return 0xffff;
3287 3299
3288 mutex_lock(&ps->reg_lock); 3300 mutex_lock(&chip->reg_lock);
3289 3301
3290 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) 3302 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3291 ret = mv88e6xxx_mdio_read_ppu(ps, addr, regnum); 3303 ret = mv88e6xxx_mdio_read_ppu(chip, addr, regnum);
3292 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY)) 3304 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3293 ret = mv88e6xxx_mdio_read_indirect(ps, addr, regnum); 3305 ret = mv88e6xxx_mdio_read_indirect(chip, addr, regnum);
3294 else 3306 else
3295 ret = mv88e6xxx_mdio_read_direct(ps, addr, regnum); 3307 ret = mv88e6xxx_mdio_read_direct(chip, addr, regnum);
3296 3308
3297 mutex_unlock(&ps->reg_lock); 3309 mutex_unlock(&chip->reg_lock);
3298 return ret; 3310 return ret;
3299} 3311}
3300 3312
3301static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum, 3313static int mv88e6xxx_mdio_write(struct mii_bus *bus, int port, int regnum,
3302 u16 val) 3314 u16 val)
3303{ 3315{
3304 struct mv88e6xxx_priv_state *ps = bus->priv; 3316 struct mv88e6xxx_chip *chip = bus->priv;
3305 int addr = mv88e6xxx_port_to_mdio_addr(ps, port); 3317 int addr = mv88e6xxx_port_to_mdio_addr(chip, port);
3306 int ret; 3318 int ret;
3307 3319
3308 if (addr < 0) 3320 if (addr < 0)
3309 return 0xffff; 3321 return 0xffff;
3310 3322
3311 mutex_lock(&ps->reg_lock); 3323 mutex_lock(&chip->reg_lock);
3312 3324
3313 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) 3325 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3314 ret = mv88e6xxx_mdio_write_ppu(ps, addr, regnum, val); 3326 ret = mv88e6xxx_mdio_write_ppu(chip, addr, regnum, val);
3315 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_SMI_PHY)) 3327 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_SMI_PHY))
3316 ret = mv88e6xxx_mdio_write_indirect(ps, addr, regnum, val); 3328 ret = mv88e6xxx_mdio_write_indirect(chip, addr, regnum, val);
3317 else 3329 else
3318 ret = mv88e6xxx_mdio_write_direct(ps, addr, regnum, val); 3330 ret = mv88e6xxx_mdio_write_direct(chip, addr, regnum, val);
3319 3331
3320 mutex_unlock(&ps->reg_lock); 3332 mutex_unlock(&chip->reg_lock);
3321 return ret; 3333 return ret;
3322} 3334}
3323 3335
3324static int mv88e6xxx_mdio_register(struct mv88e6xxx_priv_state *ps, 3336static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
3325 struct device_node *np) 3337 struct device_node *np)
3326{ 3338{
3327 static int index; 3339 static int index;
3328 struct mii_bus *bus; 3340 struct mii_bus *bus;
3329 int err; 3341 int err;
3330 3342
3331 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_PPU)) 3343 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU))
3332 mv88e6xxx_ppu_state_init(ps); 3344 mv88e6xxx_ppu_state_init(chip);
3333 3345
3334 if (np) 3346 if (np)
3335 ps->mdio_np = of_get_child_by_name(np, "mdio"); 3347 chip->mdio_np = of_get_child_by_name(np, "mdio");
3336 3348
3337 bus = devm_mdiobus_alloc(ps->dev); 3349 bus = devm_mdiobus_alloc(chip->dev);
3338 if (!bus) 3350 if (!bus)
3339 return -ENOMEM; 3351 return -ENOMEM;
3340 3352
3341 bus->priv = (void *)ps; 3353 bus->priv = (void *)chip;
3342 if (np) { 3354 if (np) {
3343 bus->name = np->full_name; 3355 bus->name = np->full_name;
3344 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 3356 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name);
@@ -3349,89 +3361,89 @@ static int mv88e6xxx_mdio_register(struct mv88e6xxx_priv_state *ps,
3349 3361
3350 bus->read = mv88e6xxx_mdio_read; 3362 bus->read = mv88e6xxx_mdio_read;
3351 bus->write = mv88e6xxx_mdio_write; 3363 bus->write = mv88e6xxx_mdio_write;
3352 bus->parent = ps->dev; 3364 bus->parent = chip->dev;
3353 3365
3354 if (ps->mdio_np) 3366 if (chip->mdio_np)
3355 err = of_mdiobus_register(bus, ps->mdio_np); 3367 err = of_mdiobus_register(bus, chip->mdio_np);
3356 else 3368 else
3357 err = mdiobus_register(bus); 3369 err = mdiobus_register(bus);
3358 if (err) { 3370 if (err) {
3359 dev_err(ps->dev, "Cannot register MDIO bus (%d)\n", err); 3371 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
3360 goto out; 3372 goto out;
3361 } 3373 }
3362 ps->mdio_bus = bus; 3374 chip->mdio_bus = bus;
3363 3375
3364 return 0; 3376 return 0;
3365 3377
3366out: 3378out:
3367 if (ps->mdio_np) 3379 if (chip->mdio_np)
3368 of_node_put(ps->mdio_np); 3380 of_node_put(chip->mdio_np);
3369 3381
3370 return err; 3382 return err;
3371} 3383}
3372 3384
3373static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_priv_state *ps) 3385static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip)
3374 3386
3375{ 3387{
3376 struct mii_bus *bus = ps->mdio_bus; 3388 struct mii_bus *bus = chip->mdio_bus;
3377 3389
3378 mdiobus_unregister(bus); 3390 mdiobus_unregister(bus);
3379 3391
3380 if (ps->mdio_np) 3392 if (chip->mdio_np)
3381 of_node_put(ps->mdio_np); 3393 of_node_put(chip->mdio_np);
3382} 3394}
3383 3395
3384#ifdef CONFIG_NET_DSA_HWMON 3396#ifdef CONFIG_NET_DSA_HWMON
3385 3397
3386static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) 3398static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp)
3387{ 3399{
3388 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3400 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3389 int ret; 3401 int ret;
3390 int val; 3402 int val;
3391 3403
3392 *temp = 0; 3404 *temp = 0;
3393 3405
3394 mutex_lock(&ps->reg_lock); 3406 mutex_lock(&chip->reg_lock);
3395 3407
3396 ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x6); 3408 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x6);
3397 if (ret < 0) 3409 if (ret < 0)
3398 goto error; 3410 goto error;
3399 3411
3400 /* Enable temperature sensor */ 3412 /* Enable temperature sensor */
3401 ret = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a); 3413 ret = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3402 if (ret < 0) 3414 if (ret < 0)
3403 goto error; 3415 goto error;
3404 3416
3405 ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret | (1 << 5)); 3417 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret | (1 << 5));
3406 if (ret < 0) 3418 if (ret < 0)
3407 goto error; 3419 goto error;
3408 3420
3409 /* Wait for temperature to stabilize */ 3421 /* Wait for temperature to stabilize */
3410 usleep_range(10000, 12000); 3422 usleep_range(10000, 12000);
3411 3423
3412 val = mv88e6xxx_mdio_read_direct(ps, 0x0, 0x1a); 3424 val = mv88e6xxx_mdio_read_direct(chip, 0x0, 0x1a);
3413 if (val < 0) { 3425 if (val < 0) {
3414 ret = val; 3426 ret = val;
3415 goto error; 3427 goto error;
3416 } 3428 }
3417 3429
3418 /* Disable temperature sensor */ 3430 /* Disable temperature sensor */
3419 ret = mv88e6xxx_mdio_write_direct(ps, 0x0, 0x1a, ret & ~(1 << 5)); 3431 ret = mv88e6xxx_mdio_write_direct(chip, 0x0, 0x1a, ret & ~(1 << 5));
3420 if (ret < 0) 3432 if (ret < 0)
3421 goto error; 3433 goto error;
3422 3434
3423 *temp = ((val & 0x1f) - 5) * 5; 3435 *temp = ((val & 0x1f) - 5) * 5;
3424 3436
3425error: 3437error:
3426 mv88e6xxx_mdio_write_direct(ps, 0x0, 0x16, 0x0); 3438 mv88e6xxx_mdio_write_direct(chip, 0x0, 0x16, 0x0);
3427 mutex_unlock(&ps->reg_lock); 3439 mutex_unlock(&chip->reg_lock);
3428 return ret; 3440 return ret;
3429} 3441}
3430 3442
3431static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) 3443static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3432{ 3444{
3433 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3445 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3434 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; 3446 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3435 int ret; 3447 int ret;
3436 3448
3437 *temp = 0; 3449 *temp = 0;
@@ -3447,12 +3459,12 @@ static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp)
3447 3459
3448static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) 3460static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3449{ 3461{
3450 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3462 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3451 3463
3452 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP)) 3464 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP))
3453 return -EOPNOTSUPP; 3465 return -EOPNOTSUPP;
3454 3466
3455 if (mv88e6xxx_6320_family(ps) || mv88e6xxx_6352_family(ps)) 3467 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip))
3456 return mv88e63xx_get_temp(ds, temp); 3468 return mv88e63xx_get_temp(ds, temp);
3457 3469
3458 return mv88e61xx_get_temp(ds, temp); 3470 return mv88e61xx_get_temp(ds, temp);
@@ -3460,11 +3472,11 @@ static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp)
3460 3472
3461static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) 3473static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3462{ 3474{
3463 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3475 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3464 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; 3476 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3465 int ret; 3477 int ret;
3466 3478
3467 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) 3479 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3468 return -EOPNOTSUPP; 3480 return -EOPNOTSUPP;
3469 3481
3470 *temp = 0; 3482 *temp = 0;
@@ -3480,11 +3492,11 @@ static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp)
3480 3492
3481static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) 3493static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3482{ 3494{
3483 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3495 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3484 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; 3496 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3485 int ret; 3497 int ret;
3486 3498
3487 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) 3499 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3488 return -EOPNOTSUPP; 3500 return -EOPNOTSUPP;
3489 3501
3490 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26); 3502 ret = mv88e6xxx_mdio_page_read(ds, phy, 6, 26);
@@ -3497,11 +3509,11 @@ static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp)
3497 3509
3498static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) 3510static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm)
3499{ 3511{
3500 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3512 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3501 int phy = mv88e6xxx_6320_family(ps) ? 3 : 0; 3513 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0;
3502 int ret; 3514 int ret;
3503 3515
3504 if (!mv88e6xxx_has(ps, MV88E6XXX_FLAG_TEMP_LIMIT)) 3516 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT))
3505 return -EOPNOTSUPP; 3517 return -EOPNOTSUPP;
3506 3518
3507 *alarm = false; 3519 *alarm = false;
@@ -3699,12 +3711,13 @@ static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
3699 return NULL; 3711 return NULL;
3700} 3712}
3701 3713
3702static int mv88e6xxx_detect(struct mv88e6xxx_priv_state *ps) 3714static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
3703{ 3715{
3704 const struct mv88e6xxx_info *info; 3716 const struct mv88e6xxx_info *info;
3705 int id, prod_num, rev; 3717 int id, prod_num, rev;
3706 3718
3707 id = mv88e6xxx_reg_read(ps, ps->info->port_base_addr, PORT_SWITCH_ID); 3719 id = mv88e6xxx_reg_read(chip, chip->info->port_base_addr,
3720 PORT_SWITCH_ID);
3708 if (id < 0) 3721 if (id < 0)
3709 return id; 3722 return id;
3710 3723
@@ -3716,30 +3729,30 @@ static int mv88e6xxx_detect(struct mv88e6xxx_priv_state *ps)
3716 return -ENODEV; 3729 return -ENODEV;
3717 3730
3718 /* Update the compatible info with the probed one */ 3731 /* Update the compatible info with the probed one */
3719 ps->info = info; 3732 chip->info = info;
3720 3733
3721 dev_info(ps->dev, "switch 0x%x detected: %s, revision %u\n", 3734 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
3722 ps->info->prod_num, ps->info->name, rev); 3735 chip->info->prod_num, chip->info->name, rev);
3723 3736
3724 return 0; 3737 return 0;
3725} 3738}
3726 3739
3727static struct mv88e6xxx_priv_state *mv88e6xxx_alloc_chip(struct device *dev) 3740static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
3728{ 3741{
3729 struct mv88e6xxx_priv_state *ps; 3742 struct mv88e6xxx_chip *chip;
3730 3743
3731 ps = devm_kzalloc(dev, sizeof(*ps), GFP_KERNEL); 3744 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
3732 if (!ps) 3745 if (!chip)
3733 return NULL; 3746 return NULL;
3734 3747
3735 ps->dev = dev; 3748 chip->dev = dev;
3736 3749
3737 mutex_init(&ps->reg_lock); 3750 mutex_init(&chip->reg_lock);
3738 3751
3739 return ps; 3752 return chip;
3740} 3753}
3741 3754
3742static int mv88e6xxx_smi_init(struct mv88e6xxx_priv_state *ps, 3755static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
3743 struct mii_bus *bus, int sw_addr) 3756 struct mii_bus *bus, int sw_addr)
3744{ 3757{
3745 /* ADDR[0] pin is unavailable externally and considered zero */ 3758 /* ADDR[0] pin is unavailable externally and considered zero */
@@ -3747,14 +3760,14 @@ static int mv88e6xxx_smi_init(struct mv88e6xxx_priv_state *ps,
3747 return -EINVAL; 3760 return -EINVAL;
3748 3761
3749 if (sw_addr == 0) 3762 if (sw_addr == 0)
3750 ps->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3763 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
3751 else if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_MULTI_CHIP)) 3764 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_MULTI_CHIP))
3752 ps->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3765 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
3753 else 3766 else
3754 return -EINVAL; 3767 return -EINVAL;
3755 3768
3756 ps->bus = bus; 3769 chip->bus = bus;
3757 ps->sw_addr = sw_addr; 3770 chip->sw_addr = sw_addr;
3758 3771
3759 return 0; 3772 return 0;
3760} 3773}
@@ -3763,7 +3776,7 @@ static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3763 struct device *host_dev, int sw_addr, 3776 struct device *host_dev, int sw_addr,
3764 void **priv) 3777 void **priv)
3765{ 3778{
3766 struct mv88e6xxx_priv_state *ps; 3779 struct mv88e6xxx_chip *chip;
3767 struct mii_bus *bus; 3780 struct mii_bus *bus;
3768 int err; 3781 int err;
3769 3782
@@ -3771,30 +3784,30 @@ static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
3771 if (!bus) 3784 if (!bus)
3772 return NULL; 3785 return NULL;
3773 3786
3774 ps = mv88e6xxx_alloc_chip(dsa_dev); 3787 chip = mv88e6xxx_alloc_chip(dsa_dev);
3775 if (!ps) 3788 if (!chip)
3776 return NULL; 3789 return NULL;
3777 3790
3778 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3791 /* Legacy SMI probing will only support chips similar to 88E6085 */
3779 ps->info = &mv88e6xxx_table[MV88E6085]; 3792 chip->info = &mv88e6xxx_table[MV88E6085];
3780 3793
3781 err = mv88e6xxx_smi_init(ps, bus, sw_addr); 3794 err = mv88e6xxx_smi_init(chip, bus, sw_addr);
3782 if (err) 3795 if (err)
3783 goto free; 3796 goto free;
3784 3797
3785 err = mv88e6xxx_detect(ps); 3798 err = mv88e6xxx_detect(chip);
3786 if (err) 3799 if (err)
3787 goto free; 3800 goto free;
3788 3801
3789 err = mv88e6xxx_mdio_register(ps, NULL); 3802 err = mv88e6xxx_mdio_register(chip, NULL);
3790 if (err) 3803 if (err)
3791 goto free; 3804 goto free;
3792 3805
3793 *priv = ps; 3806 *priv = chip;
3794 3807
3795 return ps->info->name; 3808 return chip->info->name;
3796free: 3809free:
3797 devm_kfree(dsa_dev, ps); 3810 devm_kfree(dsa_dev, chip);
3798 3811
3799 return NULL; 3812 return NULL;
3800} 3813}
@@ -3835,10 +3848,10 @@ static struct dsa_switch_driver mv88e6xxx_switch_driver = {
3835 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3848 .port_fdb_dump = mv88e6xxx_port_fdb_dump,
3836}; 3849};
3837 3850
3838static int mv88e6xxx_register_switch(struct mv88e6xxx_priv_state *ps, 3851static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip,
3839 struct device_node *np) 3852 struct device_node *np)
3840{ 3853{
3841 struct device *dev = ps->dev; 3854 struct device *dev = chip->dev;
3842 struct dsa_switch *ds; 3855 struct dsa_switch *ds;
3843 3856
3844 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 3857 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
@@ -3846,7 +3859,7 @@ static int mv88e6xxx_register_switch(struct mv88e6xxx_priv_state *ps,
3846 return -ENOMEM; 3859 return -ENOMEM;
3847 3860
3848 ds->dev = dev; 3861 ds->dev = dev;
3849 ds->priv = ps; 3862 ds->priv = chip;
3850 ds->drv = &mv88e6xxx_switch_driver; 3863 ds->drv = &mv88e6xxx_switch_driver;
3851 3864
3852 dev_set_drvdata(dev, ds); 3865 dev_set_drvdata(dev, ds);
@@ -3854,9 +3867,9 @@ static int mv88e6xxx_register_switch(struct mv88e6xxx_priv_state *ps,
3854 return dsa_register_switch(ds, np); 3867 return dsa_register_switch(ds, np);
3855} 3868}
3856 3869
3857static void mv88e6xxx_unregister_switch(struct mv88e6xxx_priv_state *ps) 3870static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
3858{ 3871{
3859 dsa_unregister_switch(ps->ds); 3872 dsa_unregister_switch(chip->ds);
3860} 3873}
3861 3874
3862static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3875static int mv88e6xxx_probe(struct mdio_device *mdiodev)
@@ -3864,7 +3877,7 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3864 struct device *dev = &mdiodev->dev; 3877 struct device *dev = &mdiodev->dev;
3865 struct device_node *np = dev->of_node; 3878 struct device_node *np = dev->of_node;
3866 const struct mv88e6xxx_info *compat_info; 3879 const struct mv88e6xxx_info *compat_info;
3867 struct mv88e6xxx_priv_state *ps; 3880 struct mv88e6xxx_chip *chip;
3868 u32 eeprom_len; 3881 u32 eeprom_len;
3869 int err; 3882 int err;
3870 3883
@@ -3872,35 +3885,35 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3872 if (!compat_info) 3885 if (!compat_info)
3873 return -EINVAL; 3886 return -EINVAL;
3874 3887
3875 ps = mv88e6xxx_alloc_chip(dev); 3888 chip = mv88e6xxx_alloc_chip(dev);
3876 if (!ps) 3889 if (!chip)
3877 return -ENOMEM; 3890 return -ENOMEM;
3878 3891
3879 ps->info = compat_info; 3892 chip->info = compat_info;
3880 3893
3881 err = mv88e6xxx_smi_init(ps, mdiodev->bus, mdiodev->addr); 3894 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
3882 if (err) 3895 if (err)
3883 return err; 3896 return err;
3884 3897
3885 err = mv88e6xxx_detect(ps); 3898 err = mv88e6xxx_detect(chip);
3886 if (err) 3899 if (err)
3887 return err; 3900 return err;
3888 3901
3889 ps->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); 3902 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS);
3890 if (IS_ERR(ps->reset)) 3903 if (IS_ERR(chip->reset))
3891 return PTR_ERR(ps->reset); 3904 return PTR_ERR(chip->reset);
3892 3905
3893 if (mv88e6xxx_has(ps, MV88E6XXX_FLAG_EEPROM) && 3906 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEPROM) &&
3894 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3907 !of_property_read_u32(np, "eeprom-length", &eeprom_len))
3895 ps->eeprom_len = eeprom_len; 3908 chip->eeprom_len = eeprom_len;
3896 3909
3897 err = mv88e6xxx_mdio_register(ps, np); 3910 err = mv88e6xxx_mdio_register(chip, np);
3898 if (err) 3911 if (err)
3899 return err; 3912 return err;
3900 3913
3901 err = mv88e6xxx_register_switch(ps, np); 3914 err = mv88e6xxx_register_switch(chip, np);
3902 if (err) { 3915 if (err) {
3903 mv88e6xxx_mdio_unregister(ps); 3916 mv88e6xxx_mdio_unregister(chip);
3904 return err; 3917 return err;
3905 } 3918 }
3906 3919
@@ -3910,10 +3923,10 @@ static int mv88e6xxx_probe(struct mdio_device *mdiodev)
3910static void mv88e6xxx_remove(struct mdio_device *mdiodev) 3923static void mv88e6xxx_remove(struct mdio_device *mdiodev)
3911{ 3924{
3912 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 3925 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
3913 struct mv88e6xxx_priv_state *ps = ds_to_priv(ds); 3926 struct mv88e6xxx_chip *chip = ds_to_priv(ds);
3914 3927
3915 mv88e6xxx_unregister_switch(ps); 3928 mv88e6xxx_unregister_switch(chip);
3916 mv88e6xxx_mdio_unregister(ps); 3929 mv88e6xxx_mdio_unregister(chip);
3917} 3930}
3918 3931
3919static const struct of_device_id mv88e6xxx_of_match[] = { 3932static const struct of_device_id mv88e6xxx_of_match[] = {
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
index 856c6e50565f..83f06620133d 100644
--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
@@ -563,7 +563,7 @@ struct mv88e6xxx_priv_port {
563 struct net_device *bridge_dev; 563 struct net_device *bridge_dev;
564}; 564};
565 565
566struct mv88e6xxx_priv_state { 566struct mv88e6xxx_chip {
567 const struct mv88e6xxx_info *info; 567 const struct mv88e6xxx_info *info;
568 568
569 /* The dsa_switch this private structure is related to */ 569 /* The dsa_switch this private structure is related to */
@@ -625,10 +625,8 @@ struct mv88e6xxx_priv_state {
625}; 625};
626 626
627struct mv88e6xxx_ops { 627struct mv88e6xxx_ops {
628 int (*read)(struct mv88e6xxx_priv_state *ps, 628 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
629 int addr, int reg, u16 *val); 629 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
630 int (*write)(struct mv88e6xxx_priv_state *ps,
631 int addr, int reg, u16 val);
632}; 630};
633 631
634enum stat_type { 632enum stat_type {
@@ -644,10 +642,10 @@ struct mv88e6xxx_hw_stat {
644 enum stat_type type; 642 enum stat_type type;
645}; 643};
646 644
647static inline bool mv88e6xxx_has(struct mv88e6xxx_priv_state *ps, 645static inline bool mv88e6xxx_has(struct mv88e6xxx_chip *chip,
648 unsigned long flags) 646 unsigned long flags)
649{ 647{
650 return (ps->info->flags & flags) == flags; 648 return (chip->info->flags & flags) == flags;
651} 649}
652 650
653#endif 651#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-09-03 06:52:29 -0400