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authorLinus Walleij <linus.walleij@linaro.org>2015-10-23 18:15:53 -0400
committerMarc Zyngier <marc.zyngier@arm.com>2015-12-16 10:30:50 -0500
commit58b8964990dc6b59198b25337624b8518cb1dd87 (patch)
treedbd46297ba24ba716217629aaa2b1cb830d1f853 /drivers/irqchip/irq-gic.c
parent8673c1d7e8f0cc69b84c1c3356d869b74385fca7 (diff)
irqchip/gic: Assign irqchip dynamically
Instead of having the irqchip being a static struct, make it part of the per-instance data so we can assign it a dynamic name. This has the usable side effect of displaying the GIC with an instance number as GIC0, GIC1 ... GICn in /proc/interrupts, which is helpful when debugging cascaded GICs, such as on the ARM PB11MPCore. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/irq-gic.c')
-rw-r--r--drivers/irqchip/irq-gic.c22
1 files changed, 13 insertions, 9 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 9736a1b9d7fd..174990c56d27 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -69,6 +69,7 @@ union gic_base {
69}; 69};
70 70
71struct gic_chip_data { 71struct gic_chip_data {
72 struct irq_chip chip;
72 union gic_base dist_base; 73 union gic_base dist_base;
73 union gic_base cpu_base; 74 union gic_base cpu_base;
74#ifdef CONFIG_CPU_PM 75#ifdef CONFIG_CPU_PM
@@ -383,7 +384,6 @@ static void gic_handle_cascade_irq(struct irq_desc *desc)
383} 384}
384 385
385static struct irq_chip gic_chip = { 386static struct irq_chip gic_chip = {
386 .name = "GIC",
387 .irq_mask = gic_mask_irq, 387 .irq_mask = gic_mask_irq,
388 .irq_unmask = gic_unmask_irq, 388 .irq_unmask = gic_unmask_irq,
389 .irq_eoi = gic_eoi_irq, 389 .irq_eoi = gic_eoi_irq,
@@ -925,20 +925,15 @@ void __init gic_init_physaddr(struct device_node *node)
925static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 925static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
926 irq_hw_number_t hw) 926 irq_hw_number_t hw)
927{ 927{
928 struct irq_chip *chip = &gic_chip; 928 struct gic_chip_data *gic = d->host_data;
929
930 if (static_key_true(&supports_deactivate)) {
931 if (d->host_data == (void *)&gic_data[0])
932 chip = &gic_eoimode1_chip;
933 }
934 929
935 if (hw < 32) { 930 if (hw < 32) {
936 irq_set_percpu_devid(irq); 931 irq_set_percpu_devid(irq);
937 irq_domain_set_info(d, irq, hw, chip, d->host_data, 932 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
938 handle_percpu_devid_irq, NULL, NULL); 933 handle_percpu_devid_irq, NULL, NULL);
939 irq_set_status_flags(irq, IRQ_NOAUTOEN); 934 irq_set_status_flags(irq, IRQ_NOAUTOEN);
940 } else { 935 } else {
941 irq_domain_set_info(d, irq, hw, chip, d->host_data, 936 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data,
942 handle_fasteoi_irq, NULL, NULL); 937 handle_fasteoi_irq, NULL, NULL);
943 irq_set_probe(irq); 938 irq_set_probe(irq);
944 } 939 }
@@ -1045,6 +1040,15 @@ static void __init __gic_init_bases(unsigned int gic_nr, int irq_start,
1045 gic_check_cpu_features(); 1040 gic_check_cpu_features();
1046 1041
1047 gic = &gic_data[gic_nr]; 1042 gic = &gic_data[gic_nr];
1043
1044 /* Initialize irq_chip */
1045 if (static_key_true(&supports_deactivate) && gic_nr == 0) {
1046 gic->chip = gic_eoimode1_chip;
1047 } else {
1048 gic->chip = gic_chip;
1049 gic->chip.name = kasprintf(GFP_KERNEL, "GIC-%d", gic_nr);
1050 }
1051
1048#ifdef CONFIG_GIC_NON_BANKED 1052#ifdef CONFIG_GIC_NON_BANKED
1049 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 1053 if (percpu_offset) { /* Frankein-GIC without banked registers... */
1050 unsigned int cpu; 1054 unsigned int cpu;