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authorMarc Zyngier <marc.zyngier@arm.com>2015-12-16 09:11:22 -0500
committerMarc Zyngier <marc.zyngier@arm.com>2015-12-16 10:30:51 -0500
commit327ebe1f3a9b7e20e298b39d0cff627169a28012 (patch)
tree88ef47c45126e62e307599d8d9955e1a6e834a57 /drivers/irqchip/irq-gic.c
parent86d14c72b7837589a4381b3bc2e117e7d842a92a (diff)
irqchip/gic: Make interrupt ID 1020 invalid
The GIC has no such thing as interrupt 1020: the last valid ID is 1019, and the range 1020-1023 is reserved - 1023 indicating that no interrupt is pending. So let's make sure we don't try to handle this ID. This bug has been in since the initial GIC code was introduced in 8ad68bbf7a06 ("[ARM] Add support for ARM RealView board"). Reported-by: Eric Auger <eric.auger@linaro.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Diffstat (limited to 'drivers/irqchip/irq-gic.c')
-rw-r--r--drivers/irqchip/irq-gic.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index 174990c56d27..7f5f91984c1b 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -337,7 +337,7 @@ static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
337 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 337 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
338 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 338 irqnr = irqstat & GICC_IAR_INT_ID_MASK;
339 339
340 if (likely(irqnr > 15 && irqnr < 1021)) { 340 if (likely(irqnr > 15 && irqnr < 1020)) {
341 if (static_key_true(&supports_deactivate)) 341 if (static_key_true(&supports_deactivate))
342 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 342 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
343 handle_domain_irq(gic->domain, irqnr, regs); 343 handle_domain_irq(gic->domain, irqnr, regs);