drm/i915: Move the min_pixclk[] handling to the end of readout

commit 00b2b7288299a8c73c0c37b531a075ba5c849e67 upstream.

Trying to determine the pixel rate of the pipe can't be done until we
know the clock, which means it can't be done until the encoder
.get_config() hooks have been called. So let's move the min_pixclk[]
stuff to the end of intel_modeset_readout_hw_state() when we actually
have gathered all the required infromation.

Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>
Fixes: 565602d7501a ("drm/i915: Do not acquire crtc state to check clock during modeset, v4.")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161220153902.15621-1-ville.syrjala@linux.intel.com
Reviewed-by: Ander Conselvan de Oliveira <conselvan2@gmail.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
(cherry picked from commit aca1ebf491518910df156f3dab6a66306bb52e28)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

1 files changed, 16 insertions, 16 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c9e83f39ec0a..869b29fe9ec4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -16749,7 +16749,6 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
 
         for_each_intel_crtc(dev, crtc) {
                 struct intel_crtc_state *crtc_state = crtc->config;
-                int pixclk = 0;
 
                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
                 memset(crtc_state, 0, sizeof(*crtc_state));
@@ -16761,23 +16760,9 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                 crtc->base.enabled = crtc_state->base.enable;
                 crtc->active = crtc_state->base.active;
 
-                if (crtc_state->base.active) {
+                if (crtc_state->base.active)
                         dev_priv->active_crtcs |= 1 << crtc->pipe;
 
-                        if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
-                                pixclk = ilk_pipe_pixel_rate(crtc_state);
-                        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
-                                pixclk = crtc_state->base.adjusted_mode.crtc_clock;
-                        else
-                                WARN_ON(dev_priv->display.modeset_calc_cdclk);
-
-                        /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-                        if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
-                                pixclk = DIV_ROUND_UP(pixclk * 100, 95);
-                }
-
-                dev_priv->min_pixclk[crtc->pipe] = pixclk;
-
                 readout_plane_state(crtc);
 
                 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
@@ -16851,6 +16836,8 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
         }
 
         for_each_intel_crtc(dev, crtc) {
+                int pixclk = 0;
+
                 crtc->base.hwmode = crtc->config->base.adjusted_mode;
 
                 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
@@ -16878,10 +16865,23 @@ static void intel_modeset_readout_hw_state(struct drm_device *dev)
                          */
                         crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
 
+                        if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
+                                pixclk = ilk_pipe_pixel_rate(crtc->config);
+                        else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
+                                pixclk = crtc->config->base.adjusted_mode.crtc_clock;
+                        else
+                                WARN_ON(dev_priv->display.modeset_calc_cdclk);
+
+                        /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
+                        if (IS_BROADWELL(dev_priv) && crtc->config->ips_enabled)
+                                pixclk = DIV_ROUND_UP(pixclk * 100, 95);
+
                         drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
                         update_scanline_offset(crtc);
                 }
 
+                dev_priv->min_pixclk[crtc->pipe] = pixclk;
+
                 intel_pipe_config_sanity_check(dev_priv, crtc->config);
         }
 }