aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpio/gpio-amdpt.c
diff options
context:
space:
mode:
authorAxel Lin <axel.lin@ingics.com>2016-02-29 09:00:01 -0500
committerLinus Walleij <linus.walleij@linaro.org>2016-03-30 04:38:51 -0400
commit574b782e7b632974e85e8629842746d0229c4aed (patch)
treef44bb54e95b820a3089e8edaf8c2846f7ea08ad5 /drivers/gpio/gpio-amdpt.c
parentf7aed67d632f6e316b9a9e2fe2818a07bfa42e81 (diff)
gpio: amdpt: Convert to use gpio-generic
Use gpio-generic to simplify this driver. Signed-off-by: Axel Lin <axel.lin@ingics.com> Tested-by: YD Tseng <Yd_Tseng@asmedia.com.tw> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers/gpio/gpio-amdpt.c')
-rw-r--r--drivers/gpio/gpio-amdpt.c122
1 files changed, 14 insertions, 108 deletions
diff --git a/drivers/gpio/gpio-amdpt.c b/drivers/gpio/gpio-amdpt.c
index c2484046e8e9..569b424efb5a 100644
--- a/drivers/gpio/gpio-amdpt.c
+++ b/drivers/gpio/gpio-amdpt.c
@@ -28,7 +28,6 @@
28struct pt_gpio_chip { 28struct pt_gpio_chip {
29 struct gpio_chip gc; 29 struct gpio_chip gc;
30 void __iomem *reg_base; 30 void __iomem *reg_base;
31 spinlock_t lock;
32}; 31};
33 32
34static int pt_gpio_request(struct gpio_chip *gc, unsigned offset) 33static int pt_gpio_request(struct gpio_chip *gc, unsigned offset)
@@ -39,19 +38,19 @@ static int pt_gpio_request(struct gpio_chip *gc, unsigned offset)
39 38
40 dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset); 39 dev_dbg(gc->parent, "pt_gpio_request offset=%x\n", offset);
41 40
42 spin_lock_irqsave(&pt_gpio->lock, flags); 41 spin_lock_irqsave(&gc->bgpio_lock, flags);
43 42
44 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 43 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
45 if (using_pins & BIT(offset)) { 44 if (using_pins & BIT(offset)) {
46 dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n", 45 dev_warn(gc->parent, "PT GPIO pin %x reconfigured\n",
47 offset); 46 offset);
48 spin_unlock_irqrestore(&pt_gpio->lock, flags); 47 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
49 return -EINVAL; 48 return -EINVAL;
50 } 49 }
51 50
52 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG); 51 writel(using_pins | BIT(offset), pt_gpio->reg_base + PT_SYNC_REG);
53 52
54 spin_unlock_irqrestore(&pt_gpio->lock, flags); 53 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
55 54
56 return 0; 55 return 0;
57} 56}
@@ -62,111 +61,17 @@ static void pt_gpio_free(struct gpio_chip *gc, unsigned offset)
62 unsigned long flags; 61 unsigned long flags;
63 u32 using_pins; 62 u32 using_pins;
64 63
65 spin_lock_irqsave(&pt_gpio->lock, flags); 64 spin_lock_irqsave(&gc->bgpio_lock, flags);
66 65
67 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG); 66 using_pins = readl(pt_gpio->reg_base + PT_SYNC_REG);
68 using_pins &= ~BIT(offset); 67 using_pins &= ~BIT(offset);
69 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG); 68 writel(using_pins, pt_gpio->reg_base + PT_SYNC_REG);
70 69
71 spin_unlock_irqrestore(&pt_gpio->lock, flags); 70 spin_unlock_irqrestore(&gc->bgpio_lock, flags);
72 71
73 dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset); 72 dev_dbg(gc->parent, "pt_gpio_free offset=%x\n", offset);
74} 73}
75 74
76static void pt_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
77{
78 struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
79 unsigned long flags;
80 u32 data;
81
82 dev_dbg(gc->parent, "pt_gpio_set_value offset=%x, value=%x\n",
83 offset, value);
84
85 spin_lock_irqsave(&pt_gpio->lock, flags);
86
87 data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
88 data &= ~BIT(offset);
89 if (value)
90 data |= BIT(offset);
91 writel(data, pt_gpio->reg_base + PT_OUTPUTDATA_REG);
92
93 spin_unlock_irqrestore(&pt_gpio->lock, flags);
94}
95
96static int pt_gpio_get_value(struct gpio_chip *gc, unsigned offset)
97{
98 struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
99 unsigned long flags;
100 u32 data;
101
102 spin_lock_irqsave(&pt_gpio->lock, flags);
103
104 data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
105
106 /* configure as output */
107 if (data & BIT(offset))
108 data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
109 else /* configure as input */
110 data = readl(pt_gpio->reg_base + PT_INPUTDATA_REG);
111
112 spin_unlock_irqrestore(&pt_gpio->lock, flags);
113
114 data >>= offset;
115 data &= 1;
116
117 dev_dbg(gc->parent, "pt_gpio_get_value offset=%x, value=%x\n",
118 offset, data);
119
120 return data;
121}
122
123static int pt_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
124{
125 struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
126 unsigned long flags;
127 u32 data;
128
129 dev_dbg(gc->parent, "pt_gpio_dirction_input offset=%x\n", offset);
130
131 spin_lock_irqsave(&pt_gpio->lock, flags);
132
133 data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
134 data &= ~BIT(offset);
135 writel(data, pt_gpio->reg_base + PT_DIRECTION_REG);
136
137 spin_unlock_irqrestore(&pt_gpio->lock, flags);
138
139 return 0;
140}
141
142static int pt_gpio_direction_output(struct gpio_chip *gc,
143 unsigned offset, int value)
144{
145 struct pt_gpio_chip *pt_gpio = gpiochip_get_data(gc);
146 unsigned long flags;
147 u32 data;
148
149 dev_dbg(gc->parent, "pt_gpio_direction_output offset=%x, value=%x\n",
150 offset, value);
151
152 spin_lock_irqsave(&pt_gpio->lock, flags);
153
154 data = readl(pt_gpio->reg_base + PT_OUTPUTDATA_REG);
155 if (value)
156 data |= BIT(offset);
157 else
158 data &= ~BIT(offset);
159 writel(data, pt_gpio->reg_base + PT_OUTPUTDATA_REG);
160
161 data = readl(pt_gpio->reg_base + PT_DIRECTION_REG);
162 data |= BIT(offset);
163 writel(data, pt_gpio->reg_base + PT_DIRECTION_REG);
164
165 spin_unlock_irqrestore(&pt_gpio->lock, flags);
166
167 return 0;
168}
169
170static int pt_gpio_probe(struct platform_device *pdev) 75static int pt_gpio_probe(struct platform_device *pdev)
171{ 76{
172 struct device *dev = &pdev->dev; 77 struct device *dev = &pdev->dev;
@@ -196,18 +101,19 @@ static int pt_gpio_probe(struct platform_device *pdev)
196 return PTR_ERR(pt_gpio->reg_base); 101 return PTR_ERR(pt_gpio->reg_base);
197 } 102 }
198 103
199 spin_lock_init(&pt_gpio->lock); 104 ret = bgpio_init(&pt_gpio->gc, dev, 4,
105 pt_gpio->reg_base + PT_INPUTDATA_REG,
106 pt_gpio->reg_base + PT_OUTPUTDATA_REG, NULL,
107 pt_gpio->reg_base + PT_DIRECTION_REG, NULL,
108 BGPIOF_READ_OUTPUT_REG_SET);
109 if (ret) {
110 dev_err(&pdev->dev, "bgpio_init failed\n");
111 return ret;
112 }
200 113
201 pt_gpio->gc.label = pdev->name;
202 pt_gpio->gc.owner = THIS_MODULE; 114 pt_gpio->gc.owner = THIS_MODULE;
203 pt_gpio->gc.parent = dev;
204 pt_gpio->gc.request = pt_gpio_request; 115 pt_gpio->gc.request = pt_gpio_request;
205 pt_gpio->gc.free = pt_gpio_free; 116 pt_gpio->gc.free = pt_gpio_free;
206 pt_gpio->gc.direction_input = pt_gpio_direction_input;
207 pt_gpio->gc.direction_output = pt_gpio_direction_output;
208 pt_gpio->gc.get = pt_gpio_get_value;
209 pt_gpio->gc.set = pt_gpio_set_value;
210 pt_gpio->gc.base = -1;
211 pt_gpio->gc.ngpio = PT_TOTAL_GPIO; 117 pt_gpio->gc.ngpio = PT_TOTAL_GPIO;
212#if defined(CONFIG_OF_GPIO) 118#if defined(CONFIG_OF_GPIO)
213 pt_gpio->gc.of_node = pdev->dev.of_node; 119 pt_gpio->gc.of_node = pdev->dev.of_node;